JPH08274099A - Wiring forming method - Google Patents

Abstract

PURPOSE: To suppress the production of Si nodules in an Al alloy layer containing Si and to raise the EM(electromigration) resistance. CONSTITUTION: After an Al alloy layer 18 containing Si is formed on an insulating film 12 which covers the surface of a semiconductor substrate 10, interposing a Ti layer 14, TiON (or TiN) layer 16, etc., between them as occasion demands, a Ti layer 20 is formed on the layer 18. And production of Si nodules is suppressed, since excessive Si in the layer 18 is absorbed by the Ti layer 20 if heat treatment is performed under the condition of 450-500 deg.C and 120sec. The EM resistance is also raised. After a TiN (or TiON) layer 22 for preventing reflection is formed on the Ti layer 20, wiring patterning is performed using resist layers 24A, 24B as masks. Since Si nodules are decreased, it becomes possible to reduce the wiring resistance and to shorten etching time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method suitable for forming fine wiring of an LSI or the like, and in particular, formation of a Si nodule by performing a heat treatment after forming a Ti layer on a Si-containing Al alloy layer. This is intended to suppress and improve EM (electromigration) resistance.

[0002]

2. Description of the Related Art Conventionally, as a wiring forming method for an LSI or the like,
6 to 8 are known (for example, Japanese Laid-Open Patent Publication No.
-190551 gazette).

In the process of FIG. 6, a Si-containing Al alloy (for example, Al--Si) is formed on the insulating film 2 covering the surface of the semiconductor substrate 1.
-Cu alloy) layer 3 is formed by sputtering, and then Ti
The layer 4 and the TiN layer 5 are sequentially formed by the sputtering method. Here, the Ti layer 4 prevents TiN layer 5 from nitriding the surface of the Al alloy layer 3 when the TiN layer 5 is formed by the reactive sputtering method, thereby avoiding an increase in contact resistance with the upper wiring.
Layer 5 prevents light reflection during the photolithography process.

Next, in the step shown in FIG. 7, photolithography is performed to form mask resist layers 6A and 6B in accordance with a desired wiring pattern.

After that, in the process of FIG.
Wiring layers 8A and 8B are formed by patterning the stack of TiN layer 5, Ti layer 4 and Al alloy layer 3 by dry etching using A and 6B as a mask and Cl ₂ + BCl ₃ or the like as an etching gas. Wiring layer 8A is made of TiN
The remaining portion 5A of the layer 5, the remaining portion 4A of the Ti layer 4 and the remaining portion 3A of the Al alloy layer 3 are formed, and the wiring layer 8B is the TiN layer 5
Remaining part 5B, remaining part 4B of Ti layer 4 and Al alloy layer 3
Of the remaining portion 3B. After this, the resist layers 6A and 6B
Is removed.

[0006]

According to the above-mentioned conventional technique, Ti is not formed after the Al alloy layer 3 is formed in order to improve the EM resistance.
When heat treatment is performed before forming the layer 4, the Si grains in the Al alloy layer 3 grow in the Al alloy layer 3 as Si nodules (lumps of excess Si) 3a having a large grain size, as shown in FIG.

When the Si nodules 3a are formed in this way, the wiring resistance increases. Further, in the patterning process of FIG. 8, the etching rate of the Si nodules 3a is slower than that of the Al alloy layer 3, so that it is necessary to lengthen the etching time. If the etching time is short, a part of the Si nodules 3a may remain and the wiring layers 8A and 8B may be short-circuited.

An object of the present invention is to provide a novel wiring forming method capable of improving the EM resistance while suppressing the generation of Si nodules.

[0009]

A wiring forming method according to the present invention comprises a step of forming a Si-containing Al alloy layer covering a wiring underlayer film, and a step of forming a Ti layer on the Al alloy layer. A step of performing a heat treatment on the Ti layer to absorb excess Si in the Al alloy layer; and a Ti layer on the Ti layer.
A step of forming an antireflection layer made of N or TiON,
Forming a mask layer on the antireflection layer according to a desired wiring pattern by photolithography, and patterning a stack of the antireflection layer, the Ti layer, and the Al alloy layer by selective etching using the mask layer. And a step of forming a wiring layer.

[0010]

According to the method of the present invention, after the Ti layer is formed, heat treatment is performed to remove excess Si in the Al alloy layer from T
Since it is absorbed in the i layer, the generation of Si nodules can be suppressed and the EM resistance can be improved.

In the method of the present invention, a barrier layer made of TiN or TiON may be provided below the Al alloy layer. In this case, if the heat treatment is performed before the formation of the antireflection layer, the antireflection layer does not prevent rearrangement of Al grains and increase in grain size, so that stress remains at the interface between the TiN layer or TiON layer and the Al alloy layer. Without this, deterioration of EM resistance and SM (stress migration) resistance can be prevented.

[0012]

1 to 4 show a wiring forming method according to an embodiment of the present invention. Steps (1) to (1) corresponding to the respective drawings are shown.
(4) will be sequentially described.

(1) An insulating film 12 made of BPSG (boron phosphosilicate glass) is formed on the surface of a semiconductor substrate 10 made of silicon by the CVD (Chemical Vapor Deposition) method. Then, in the insulating film 12, a connection hole (not shown) reaching a connection portion such as an impurity-doped region on the substrate surface is formed by well-known photolithography and etching processing.

The surface of the insulating film 12 is covered with Ti by covering the connection hole.
Layer 14, TiON layer 16, Al alloy layer 18, and Ti layer 2
0s are sequentially formed. As an example, the layers 14, 16, 18, and 20 were sequentially formed by a sputtering method using a clustering device in which a plurality of sputtering devices were combined. The pressure in the sputtering apparatus before the start of sputtering was set to 10 ^-8 Torr or less. The layers 14 and 16 have thicknesses of 20 nm and 100, respectively.
and the layer 18 is 400 nm thick Al-S
An i-Cu alloy layer was formed, and the layer 20 had a thickness of 7 nm. The layer 14 is for reducing contact resistance, the layer 16 is for barrier layer, and the layer 20 is for absorbing excess Si in the layer 18 and preventing nitriding of the surface of the layer 18.

(2) Next, excess Si in the Al alloy layer 18
Is heat-treated to be absorbed in the Ti layer 20 as indicated by an arrow A in FIG. As an example, 470 in another processing chamber without breaking the vacuum in the clustering device in step (1).
Heat treatment was performed at 120 ° C. for 120 seconds.

(3) Next, a TiN layer 22 is formed on the surface of the Ti layer 20 so as to cover the above-mentioned connection holes. As an example,
The layer 22 was formed to a thickness of 40 nm by the reactive sputtering method in another processing chamber without breaking the vacuum in the clustering apparatus in the step (2). At this time, the surface of the Al alloy layer 18 is not nitrided because it is covered with the Ti layer 20. Therefore, it is possible to avoid an increase in contact resistance with the upper wiring.

The resist layers 24A, 2A are formed on the upper surface of the substrate according to a desired wiring pattern by a known photolithography process.
4B is formed. As an example, the thickness of the layers 24A and 24B is 1.65 μm.

(4) After that, the resist layers 24A and 24B
Layer 1 by selective dry etching treatment using a mask as a mask
Wiring layers 26A, 26B are formed by patterning the laminated layers 4, 16, 18, 20, 22. Layer 26A is layer 1
Remaining part 14A, 1 of each of 4, 16, 18, 20, 22
6A, 18A, 20A, 22A, the layer 26B is
Remaining portion 14 of each of layers 14, 16, 18, 20, 22
B, 16B, 18B, 20B, 22B. An example of dry etching conditions is shown in Table 1 below.

[0019]

[Table 1] Here, “main etching” is etching up to the Al alloy layer 18, and “TiON etching” is Ti etching.
This is etching of the ON layer 16 and the Ti layer 14. These etchings are continuously performed in the same etching chamber. After etching, the resist layers 24A and 24B are removed.

According to the above-mentioned embodiment, assuming that the case where the heat treatment step of FIG. 2 is omitted is 1, the EM resistance is improved 5 to 10 times. As a reason why the EM resistance is improved, the inventor
I am thinking of the following (a) and (b).

(B) The rearrangement of Al grains and the increase in grain size are promoted by the heat treatment, and stress yielding occurs, so that the residual stress between the barrier layer and the Al alloy layer is reduced. As a result, the density of defects that deteriorate EM resistance is reduced.

(B) Since the precipitates at the Al grain boundaries are increased by the heat treatment, the diffusion of Al grain boundaries by EM can be reduced.

In a normal LSI manufacturing process, heat treatment may be performed at about 400 ° C. after forming a wiring layer. It is considered that such a heat treatment is used instead of the heat treatment of FIG. 2, but when this is done, the TiON layer 16A exists under the Al alloy layer 18A and the Al alloy layer 18A is present.
Since the TiN layer 22A exists above the above, stress remains at the interface between the Al alloy layer 18A and the TiON layer 16A due to the heat treatment, and the EM resistance and SM resistance deteriorate in the wiring having a width of 1.0 μm or less. On the other hand, in the above-described embodiment, since the heat treatment is performed before forming the TiN layer 22, there is no residual stress, and deterioration of EM resistance and SM resistance can be prevented. In particular, in this embodiment, the Al alloy layer 1
After forming No. 8, heat treatment was performed without breaking the vacuum in the clustering device to prevent the surface of the Al alloy layer 18 from being oxidized, so that rearrangement of Al grains and increase in grain size are not hindered. Therefore, there is no residual stress, and deterioration of EM resistance and SM resistance can be further prevented.

FIG. 5 shows an etching time and a short circuit (time) for patterning the wiring when the heat treatment is performed after the formation of the Ti layer 20 (invention) and when the heat treatment is performed before the formation of the Ti layer 20 (comparative example). It shows the relationship with the short circuit) avoidance rate. In the present invention and the comparative example, the processing steps are the same as those described above with reference to FIGS. 1 to 4 except for the order of heat treatment (whether the Ti layer 20 is formed or before).
In the wiring patterning step of, the wiring layers 26A and 26B
Was selectively dry-etched so that the distance between the two was 0.5 μm. The short-circuit avoidance rate shows what percentage of a predetermined number of samples avoided the short-circuit occurrence as shown in 3a of FIG. 8. Lines P and Q are the dry etching time of the short-circuit avoidance rate in the present invention and the comparative example, respectively. Show dependencies.

It can be seen from FIG. 5 that in the case of the present invention, the occurrence of short circuit can be eliminated by 100% even if the dry etching time is shortened by about 20 seconds as compared with the case of the comparative example.

In the above embodiment, a TiN layer may be used instead of the TiON layer 16. A TiON layer may be used instead of the TiN layer 22. Furthermore, the Ti layer 20
The thickness of the other layers 16 and 1 may be about 5 to 20 nm.
The thicknesses of 8 and 22 are not limited to those described above, and can be appropriately selected.

Regarding the heat treatment after forming the Ti layer 20, the temperature may be about 450 to 500 ° C., and the time is not limited to 120 seconds.

[0028]

As described above, according to the present invention, Ti
Since the generation of Si nodules is suppressed by heat treatment after forming the layer, it is possible to suppress an increase in wiring resistance and to shorten an etching time at the time of wiring patterning. Further, the effect of improving the EM resistance by the heat treatment can be obtained.

Moreover, TiN or Ti is formed under the Al alloy layer.
If a barrier layer made of ON is provided and heat treatment is performed before the formation of the antireflection layer, the effect of preventing deterioration of EM resistance and SM resistance can also be obtained.

[Brief description of drawings]

FIG. 1 is a substrate cross-sectional view showing a wiring material applying step in a wiring forming method according to an embodiment of the present invention.

FIG. 2 is a substrate cross-sectional view showing a heat treatment step that follows the step of FIG.

FIG. 3 is a substrate cross-sectional view showing a TiN deposition and resist layer forming step that follows the step of FIG.

FIG. 4 is a substrate cross-sectional view showing a wiring patterning process that follows the process of FIG.

FIG. 5 shows the dry etching time and the short-circuit avoidance rate at the time of wiring patterning when the heat treatment is performed after forming the Ti layer 20 (the present invention) and when the heat treatment is performed before forming the Ti layer 20 (comparative example). It is a graph which shows the relationship of.

FIG. 6 is a substrate cross-sectional view showing a wiring material applying step in a conventional wiring forming method.

FIG. 7 is a substrate cross-sectional view showing a resist layer forming step following the step of FIG.

FIG. 8 is a substrate cross-sectional view showing a wiring patterning process that follows the process of FIG.

[Explanation of symbols]

10: semiconductor substrate, 12: insulating film, 14: Ti layer, 1
6: TiON layer, 18: Al alloy layer, 20: Ti layer, 2
2: TiN layer, 24A, 24B: resist layer, 26A,
26B: wiring layer.

Claims (2)

[Claims] 1. A step of forming a Si-containing Al alloy layer to cover a wiring underlying film, a step of forming a Ti layer on the Al alloy layer, and an excess Si in the Al alloy layer to the Ti layer. A step of performing heat treatment for absorption, a step of forming an antireflection layer made of TiN or TiON on the Ti layer, and a step of forming a mask layer on the antireflection layer by photolithography according to a desired wiring pattern A wiring forming method comprising: a step of forming a wiring layer by patterning a stack of the antireflection layer, the Ti layer, and the Al alloy layer by a selective etching process using the mask layer. 2. A step of forming a barrier layer made of TiN or TiON so as to cover the wiring underlying film, a step of forming a Si-containing Al alloy layer on the barrier layer, and a Ti layer on the Al alloy layer. Forming a Ti layer, heat treating the Ti layer to absorb excess Si in the Al alloy layer, and performing TiN or T on the Ti layer after the heat treatment.
a step of forming an antireflection layer made of iON, a step of forming a mask layer on the antireflection layer in accordance with a desired wiring pattern by photolithography, and a step of selective etching using the mask layer, the antireflection layer, Forming a wiring layer by patterning a stack of the Ti layer, the Al alloy layer and the barrier layer.