JPH05152280A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05152280A JPH05152280A JP31590591A JP31590591A JPH05152280A JP H05152280 A JPH05152280 A JP H05152280A JP 31590591 A JP31590591 A JP 31590591A JP 31590591 A JP31590591 A JP 31590591A JP H05152280 A JPH05152280 A JP H05152280A
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- film
- aluminum
- insulating film
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特にプラズマCVD法による絶縁膜の形成方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an insulating film by a plasma CVD method.
【0002】[0002]
【従来の技術】従来、金属配線を有する半導体チップに
カバー絶縁膜などをプラズマCVD法で堆積する場合、
生成温度は一定にして成膜していた。2. Description of the Related Art Conventionally, when a cover insulating film or the like is deposited on a semiconductor chip having metal wiring by a plasma CVD method,
The formation temperature was kept constant and the film was formed.
【0003】[0003]
【発明が解決しようとする課題】この従来の一定温度で
成膜するプロセスでは生成温度が300℃付近と比較的
高く設定されるのが普通であるため、下地基板の半導体
チップにアルミニウム系の金属配線が既に形成されてい
る場合、アルミニウムのヒロックが発生したり甚しい場
合は断線が発生し、歩留低下や品質低下をもたらすとい
う問題点があった。In this conventional process for forming a film at a constant temperature, the production temperature is usually set to a relatively high value of around 300 ° C. Therefore, the semiconductor chip of the base substrate is made of an aluminum-based metal. When the wiring is already formed, hillocks of aluminum are generated, and if severe, disconnection occurs, resulting in a decrease in yield and quality.
【課題を解決するための手段】本発明は、金属配線を形
成した半導体チップにプラズマCVD法で絶縁膜を堆積
する工程を有する半導体装置の製造方法において、生成
温度を所定値から上昇させつつ前記絶縁膜を堆積すると
いうものである。According to the present invention, there is provided a method of manufacturing a semiconductor device including a step of depositing an insulating film on a semiconductor chip having metal wiring formed thereon by a plasma CVD method, while increasing a generation temperature from a predetermined value. This is to deposit an insulating film.
【0004】[0004]
【実施例】次に本発明の一実施例について説明する。Next, an embodiment of the present invention will be described.
【0005】まず、図1(a)に示すように、P型シリ
コン基板1に図示しないトランジスタなどの素子、酸化
シリコン膜2(フィールド酸化膜や層間絶縁膜など)お
よびアルミニウム配線3を形成した半導体チップ(実際
にはウェーハ)を準備し、150℃に加熱されている、
プラズマCVD装置の反応炉に入れる。1分〜20分そ
のままにして、ウェーハの温度が一定になってから反応
ガス(SiH4 −NH3 −N2 O)を導入すると同時
に、図2に示すように、15℃/minの割合で温度を
上昇させ、10分後に300℃に保持する。温度が15
0℃から300℃になるまでの間にSi−O−N膜を約
200nmの厚さ成長させ、300℃で約800nmの
厚さ成長させる。ただし、Si4 ガス、NH3 ガスおよ
びN2 Oガスの流量はそれぞれ1000cc/min、
300cc/minおよび250cc/min、炉内圧
力は0.35Torr、周波数50kHz、マイクロ波
電力は1.0Wとする。First, as shown in FIG. 1A, a semiconductor in which elements such as transistors (not shown), a silicon oxide film 2 (a field oxide film, an interlayer insulating film, etc.) and an aluminum wiring 3 are formed on a P-type silicon substrate 1. Prepare a chip (actually a wafer) and heat it to 150 ° C
It is placed in the reaction furnace of the plasma CVD apparatus. The reaction gas (SiH 4 —NH 3 —N 2 O) was introduced after the temperature of the wafer became constant for 1 to 20 minutes, and at the same time, as shown in FIG. 2, at a rate of 15 ° C./min. The temperature is raised and kept at 300 ° C. after 10 minutes. Temperature is 15
A Si—O—N film is grown to a thickness of about 200 nm between 0 ° C. and 300 ° C., and a thickness of about 800 nm is grown at 300 ° C. However, the flow rates of Si 4 gas, NH 3 gas, and N 2 O gas are each 1000 cc / min,
The pressure is 300 cc / min and 250 cc / min, the furnace pressure is 0.35 Torr, the frequency is 50 kHz, and the microwave power is 1.0 W.
【0006】このようにして形成されたSi−O−N膜
4は、下層でストレスが小さく上層で緻密であるので、
アルミニウムのヒロックの発生を防止すると同時に、パ
ッシベーション効果の優れたものとなる。The Si-O-N film 4 thus formed has less stress in the lower layer and is dense in the upper layer.
It prevents generation of aluminum hillocks and, at the same time, has an excellent passivation effect.
【0007】なお、絶縁膜の堆積はSi−O−Nに限ら
ず、Si−NやSi−Oを用いてもよい。また用途的に
は層間絶縁膜やカバー絶縁膜のいずれでもよい。The deposition of the insulating film is not limited to Si-O-N, but Si-N or Si-O may be used. Further, it may be either an interlayer insulating film or a cover insulating film for use.
【0008】[0008]
【発明の効果】以上説明したように半導体は、絶縁膜の
堆積を150℃程度の低温で開始し、徐々に300℃程
度まで上昇させ成膜することで、アルミニウム系配線の
表面では、低ストレス上層は、緻密な膜質とすることで
アルミニウムのヒロックや断線を防止し、かつ信頼性の
高い半導体装置を高歩留りで製造できる効果がある。As described above, in the semiconductor, the deposition of the insulating film is started at a low temperature of about 150 ° C., and the temperature is gradually raised to about 300 ° C. to form a film. The upper layer has the effect of preventing aluminum hillocks and disconnection by forming a dense film quality and capable of manufacturing a highly reliable semiconductor device with a high yield.
【図1】本発明の一実施例の説明に使用するため
(a),(b)に分図して示す工程順断面図である。1A to 1C are cross-sectional views in order of the processes, which are illustrated in FIGS.
【図2】一実施例における温度スケジュールを示すよグ
ラフである。FIG. 2 is a graph showing a temperature schedule in one example.
1 P型シリコン基板 2 酸化シリコン膜 3 アルミニウム配線 4 Si−O−N(酸窒化シリコン)膜 1 P-type silicon substrate 2 Silicon oxide film 3 Aluminum wiring 4 Si-ON (silicon oxynitride) film
Claims (1)
ズマCVD法で絶縁膜を堆積する工程を有する半導体装
置の製造方法において、生成温度を所定値から上昇させ
つつ前記絶縁膜を堆積することを特徴とする半導体装置
の製造方法。1. A method of manufacturing a semiconductor device, comprising a step of depositing an insulating film on a semiconductor chip having metal wiring formed thereon by a plasma CVD method, wherein the insulating film is deposited while increasing a generation temperature from a predetermined value. And a method for manufacturing a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31590591A JPH05152280A (en) | 1991-11-29 | 1991-11-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31590591A JPH05152280A (en) | 1991-11-29 | 1991-11-29 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05152280A true JPH05152280A (en) | 1993-06-18 |
Family
ID=18071021
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31590591A Withdrawn JPH05152280A (en) | 1991-11-29 | 1991-11-29 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05152280A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07201749A (en) * | 1993-12-28 | 1995-08-04 | Applied Materials Inc | Formation method for thin film |
KR100510464B1 (en) * | 1998-04-30 | 2005-10-24 | 삼성전자주식회사 | Deposition method of high density plasma oxide |
-
1991
- 1991-11-29 JP JP31590591A patent/JPH05152280A/en not_active Withdrawn
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07201749A (en) * | 1993-12-28 | 1995-08-04 | Applied Materials Inc | Formation method for thin film |
KR100510464B1 (en) * | 1998-04-30 | 2005-10-24 | 삼성전자주식회사 | Deposition method of high density plasma oxide |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990204 |