JPH0810692B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
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- JPH0810692B2 JPH0810692B2 JP22720290A JP22720290A JPH0810692B2 JP H0810692 B2 JPH0810692 B2 JP H0810692B2 JP 22720290 A JP22720290 A JP 22720290A JP 22720290 A JP22720290 A JP 22720290A JP H0810692 B2 JPH0810692 B2 JP H0810692B2
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- Prior art keywords
- vapor deposition
- chemical vapor
- deposition method
- semiconductor device
- film
- Prior art date
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Description
【発明の詳細な説明】 〔概 要〕 半導体装置のテトラエトキシシラン（TEOS）等のシリ
コンアルコキシドとオゾンを原料ガスとして用いる化学
気相成長法により所定厚さの層間絶縁層を形成する方法
に関し， TEOS等が特徴とする表面の平坦な層間絶縁層を形成可
能とするために，金属や半導体から成る導電層上と該導
電層の下地となる絶縁層上における成長速度差の影響が
防止された形成方法を提供することを目的とし， 絶縁層上に該絶縁層を部分的に表出するようにして金
属層もしくは半導体層が形成された基板上に,450℃以下
で行う低温化学気相成長法，とくにシラン（SiH4）と亜
酸化窒素（N2O）を原料ガスとするプラズマ化学気相成
長法またはシラン（SiH4）と酸素（O2）を原料ガスとす
る減圧もしくは常圧化学気相成長法により薄い酸化膜を
形成する工程と，シリコンアルコキシドとオゾンを原料
ガスとする化学気相成長法を用いて厚い酸化膜を該薄い
酸化膜上に形成する工程とを含むことから構成される。DETAILED DESCRIPTION OF THE INVENTION [Overview] A method for forming an interlayer insulating layer of a predetermined thickness by a chemical vapor deposition method using silicon alkoxide such as tetraethoxysilane (TEOS) and ozone as a source gas for a semiconductor device, In order to be able to form an interlayer insulating layer with a flat surface characterized by TEOS, etc., the influence of the difference in growth rate between the conductive layer made of metal or semiconductor and the insulating layer which is the base of the conductive layer was prevented. Low temperature chemical vapor deposition at a temperature of 450 ° C or lower on a substrate on which a metal layer or a semiconductor layer is formed so as to partially expose the insulating layer for the purpose of providing a forming method. Method, especially plasma chemical vapor deposition using silane (SiH 4 ) and nitrous oxide (N 2 O) as source gases, or depressurized or atmospheric pressure chemistry using silane (SiH 4 ) and oxygen (O 2 ) as source gases Thin by vapor growth method Of a step of film formation, and because they contain a step of the silicon alkoxide and ozone to form the chemical vapor deposition of a thick oxide film the thin oxide film on the use as a raw material gas.
本発明は，半導体装置のテトラエトキシシラン（TEO
S）等のシリコンアルコキシドとオゾンを原料ガスとし
て用いる化学気相成長法により所定厚さの層間絶縁層を
形成する方法に関する。The present invention is directed to a semiconductor device such as tetraethoxysilane (TEO).
The present invention relates to a method for forming an interlayer insulating layer having a predetermined thickness by a chemical vapor deposition method using a silicon alkoxide such as S) and ozone as a source gas.
半導体集積回路の高密度化およびゲート数の増大にと
もなって，配線敷設密度が増加し，また，配線パターン
が複雑になる傾向にある。このため，多層配線の導入が
一般的になっている。配線が多層化するのにともなっ
て，層間絶縁層表面における段差が大きくなる。この段
差は，一方で，層間絶縁層上に形成される配線層のカバ
レッジや微細配線のパターンニングを困難にし，配線敷
設密度や微細化に限界を生じる要因となる。As the density of semiconductor integrated circuits increases and the number of gates increases, the wiring laying density tends to increase and the wiring patterns tend to become complicated. For this reason, the introduction of multilayer wiring has become common. As the wiring becomes multi-layered, the step difference on the surface of the interlayer insulating layer becomes larger. On the other hand, this step difference makes coverage of the wiring layer formed on the interlayer insulating layer and patterning of fine wiring difficult, and causes a limit in wiring laying density and miniaturization.
このために，段差を有する層間絶縁層表面に，いわゆ
るスピンオングラス（SOG）と呼ばれる珪酸化合物溶液
を塗布し、これをエッチバックする平坦化方法がある。
しかし,SOGの塗布・ベーキングあるいはエッチバック等
に長時間を要し，また,SOGから成る絶縁層の電気的耐圧
が充分でないために,SOG絶縁層を避けてコンタクトホー
ルを形成する必要がある等，レイアウト上の制約が生じ
る問題がある。For this purpose, there is a flattening method in which a so-called spin-on-glass (SOG) solution of a silicate compound is applied to the surface of an interlayer insulating layer having a step and is etched back.
However, it takes a long time to apply, bake or etch back SOG, and the electrical breakdown voltage of the SOG insulating layer is not sufficient, so it is necessary to avoid the SOG insulating layer to form contact holes. ， There is a problem that layout restrictions occur.
これに対して，テトラエトキシシラン〔TEOS:Si（OC2
H5）４〕等のシリコンアルコキシドのようなシリコン有
機化合物のガスとオゾン（O3）とを原料ガスとする化学
気相成長（CVD）法が注目されている。これは,TEOS−O3
系のCVDによるSiO2層は，配線層による段差を緩やかに
するように成長し，あたかも，リフロー処理を行ったよ
うな表面を呈するため，この上にカバレッジが良好な配
線層等を形成できるのである。On the other hand, tetraethoxysilane [TEOS: Si (OC 2
A chemical vapor deposition (CVD) method using a gas of a silicon organic compound such as a silicon alkoxide such as H 5 ) 4 ] and ozone (O 3 ) as a source gas is drawing attention. This is TEOS-O 3
The SiO 2 layer formed by CVD of the system grows so as to moderate the step due to the wiring layer and has a surface as if it had been subjected to reflow treatment, so that a wiring layer with good coverage can be formed on it. is there.
しかしながら,TEOS−O3系ガスを用いるCVDによるSiO2
膜の成長速度には，下地依存性があることが知られてい
る。例えば，第３図には,TEOS−O3系ガスのCVDによるSi
O2膜の，シリコン（Si）表面上と酸化膜上における成長
速度の違いを示すグラフであって，成長初期の段階で，
酸化膜上での成長速度が低いことが分かる。この傾向
は，下地の前処理，とくに酸溶液中への浸漬と水洗を繰
り返す湿式処理によっても影響を受け，酸化膜上にはほ
とんど成長しない場合も生じる。その結果，層間絶縁層
表面における段差がより強調され,TEOS−O3系ガスを用
いるCVDの長所を充分発揮することができない。However, SiO 2 by CVD using TEOS-O 3 system gas
It is known that the film growth rate depends on the substrate. For example, Fig. 3 shows Si produced by CVD of TEOS-O 3 system gas.
3 is a graph showing a difference in growth rate of an O 2 film on a silicon (Si) surface and on an oxide film.
It can be seen that the growth rate on the oxide film is low. This tendency is also affected by the pretreatment of the base, especially the wet treatment in which dipping in an acid solution and washing with water are repeated, and there is a case in which almost no growth occurs on the oxide film. As a result, the step on the surface of the interlayer insulating layer is further emphasized, and the advantages of CVD using TEOS-O 3 system gas cannot be fully exerted.
本発明は上記問題点を解決し,TEOS−O3系ガスによるC
VDが特徴とする表面の平坦な層間絶縁層を形成可能とす
るために，金属や半導体から成る導電層上と該導電層の
下地となる絶縁層上における成長速度差の影響が防止さ
れた形成方法を提供することを目的とする。The present invention solves the above problems, C by TEOS-O 3 based gas
In order to be able to form an interlayer insulating layer with a flat surface characterized by VD, formation that prevents the influence of the growth rate difference between the conductive layer made of metal or semiconductor and the insulating layer that is the base of the conductive layer is prevented. The purpose is to provide a method.
上記目的は，金属もしくは半導体から成る導電層と絶
縁層とが表出する基板上に成長速度の下地選択性を示さ
ない第１の化学気相成長法を用いて薄い酸化膜を形成す
る工程と，シリコンアルコキシドとオゾンを成長原料ガ
スとする第２の化学気相成長法を用いて厚い酸化膜を該
薄い酸化膜上に形成する工程とを含むことを特徴とする
本発明に係る半導体装置の製造方法，とくに，該薄い酸
化膜の成長を450℃以下の低温化学気相成長法，例えば
シラン（SiH4）と亜酸化窒素（N2O）を原料ガスとして
用いる該プラズマ化学気相成長法またはシラン（SiH4）
と酸素（O2）を原料ガスとして用いる減圧もしくは常圧
化学気相成長法で行うことを特徴とする本発明に係る半
導体装置の製造方法によって達成される。The purpose is to form a thin oxide film on a substrate on which a conductive layer made of a metal or a semiconductor and an insulating layer are exposed, by using a first chemical vapor deposition method that does not show underlying selectivity of growth rate. A step of forming a thick oxide film on the thin oxide film by using a second chemical vapor deposition method using silicon alkoxide and ozone as a growth raw material gas, the semiconductor device according to the present invention. Manufacturing method, especially low temperature chemical vapor deposition method for growing thin oxide film at 450 ° C. or lower, for example, plasma chemical vapor deposition method using silane (SiH 4 ) and nitrous oxide (N 2 O) as source gas Or silane (SiH 4 )
And the oxygen (O 2 ) are used as the source gas, the method is a reduced pressure or atmospheric pressure chemical vapor deposition method.
SiH4とN2Oを原料ガスとするプラズマCVD法，または,S
iH4とO2を原料ガスとする減圧もしくは常圧CVD法等によ
り450℃以下の低温でSiO2膜を成長させる場合，成長速
度に下地選択性は現れない。しかし，これらの成長方法
では，高アスペクト比の凹部に対するカバレッジが充分
でないために，第４図に示すように，例えば配線層３の
側面には,SiO2膜４がオーバーハング状に成長しやす
い。したがって，上記CVD法は比較的厚い層間絶縁層を
形成する方法としては充分なものと言えあい。なお，同
図におけるその他の符号は,1は基板,2は下地の絶縁層で
ある。Plasma CVD method using SiH 4 and N 2 O as source gas, or S
When the SiO 2 film is grown at a low temperature of 450 ° C. or lower by a reduced pressure or normal pressure CVD method using iH 4 and O 2 as source gases, there is no underlying selectivity in the growth rate. However, in these growth methods, since the coverage for the recess having a high aspect ratio is not sufficient, as shown in FIG. 4, for example, the SiO 2 film 4 easily grows in an overhang shape on the side surface of the wiring layer 3. . Therefore, it can be said that the above CVD method is sufficient as a method for forming a relatively thick interlayer insulating layer. The other symbols in the figure are 1 for the substrate and 2 for the underlying insulating layer.
本発明においては，第１図に示すように，例えばアル
ミニウム（Al）から成る配線層３が形成された基板１上
に，上記低温成長が可能なCVD法によってSiO2膜41を形
成し，下地絶縁層２および配線層３表面を覆ってしまっ
たのち,TEOS−O3系のガスを用いるCVD法によってSiO2膜
５を形成する。SiO2膜５は,SiO2膜41により下地の絶縁
層２表面および配線層３表面の影響を直接受けなくな
り，その結果，配線層３による段差を緩やかにするよう
な表面を呈して成長するため,TEOS−O3系のガスを用い
るCVD法本来の特徴を発揮可能となる。In the present invention, as shown in FIG. 1, a SiO 2 film 41 is formed on a substrate 1 on which a wiring layer 3 made of, for example, aluminum (Al) is formed, by the CVD method capable of low temperature growth, and a base layer is formed. After covering the surfaces of the insulating layer 2 and the wiring layer 3, a SiO 2 film 5 is formed by a CVD method using a TEOS-O 3 system gas. Since the SiO 2 film 5 is not directly influenced by the surface of the underlying insulating layer 2 and the surface of the wiring layer 3 due to the SiO 2 film 41, as a result, it grows with a surface that makes the step due to the wiring layer 3 gentle. Therefore, the original characteristics of the CVD method using the TEOS-O 3 system gas can be exhibited.
以下本発明の実施例を第２図を参照して説明する。同
図において，既掲の図面におけるのと同じ部分には同一
符号を付してある。An embodiment of the present invention will be described below with reference to FIG. In the figure, the same parts as those in the above figures are designated by the same reference numerals.
第２図（ａ）を参照して，例えば，シリコンウエハの
ような基板１の表面には多結晶シリコンから成る電極11
が形成されており，さらに，電極11を覆うSiO2から成る
絶縁層２が形成されている。そして，電極11の一部を表
出する図示しないコンタクトホールを絶縁層２に形成し
たのち，絶縁層２上に,Alから成る導電層31を堆積す
る。そして，周知のリングラフ技術により導電層31をパ
ターンニングして同図（ｂ）に示すように配線層３を形
成する。Referring to FIG. 2 (a), for example, an electrode 11 made of polycrystalline silicon is provided on the surface of a substrate 1 such as a silicon wafer.
And an insulating layer 2 made of SiO 2 covering the electrode 11 is further formed. Then, after forming a contact hole (not shown) exposing a part of the electrode 11 in the insulating layer 2, a conductive layer 31 made of Al is deposited on the insulating layer 2. Then, the conductive layer 31 is patterned by the well-known Lingraft technique to form the wiring layer 3 as shown in FIG.
なお，上記導電層31のパターニングののち，レジスト
等の有機物残渣やAl等の金属材料残渣，あるいは，鉄
（Fe）等の重金属汚染物質等を除去するための弗酸（H
F）溶液や硝酸（HNO3）溶液への浸漬処理や，これに続
く水洗等が行われるのであるが，これらの処理によっ
て，のちのTEOS−O3系のCVDにおいて，絶縁層２表面にS
iO2膜が成長し難くなる選択性が強調される場合があ
る。After the conductive layer 31 is patterned, hydrofluoric acid (H 2) for removing organic residue such as resist, metal material residue such as Al, or heavy metal contaminant such as iron (Fe) is removed.
F) solution or nitric acid (HNO 3 ) solution is soaked in water and then washed with water. These treatments are used to remove S on the surface of the insulating layer 2 in the subsequent TEOS-O 3 system CVD.
The selectivity that makes it difficult for the iO 2 film to grow may be emphasized.
次いで，同図（ｃ）に示すように，配線層３が形成さ
れた基板１表面に，例えばSiH4−N2O系のガスを用いる
プラズマCVD法により，厚さ約0.2〜0.5μｍのSiO2膜41
を堆積する。このプラズマCVD成長の条件の例は,SiH4お
よびN2Oの流量が，それぞれ,5〜10SCCMおよび200〜400S
CCM,反応系の全圧が１〜3Torr,基板１温度が200〜350℃
だある。この条件の下での成長速度は1000Å/minないし
それ以上である。なお，プラズマの発生は電圧を印加し
て行う。Then, as shown in FIG. 3C, on the surface of the substrate 1 on which the wiring layer 3 is formed, a SiO 2 film having a thickness of about 0.2 to 0.5 μm is formed by, for example, a plasma CVD method using a SiH 4 —N 2 O based gas. 2 film 41
Is deposited. An example of this plasma CVD growth condition is that the flow rates of SiH 4 and N 2 O are 5 to 10 SCCM and 200 to 400 S, respectively.
CCM, total pressure of reaction system is 1-3 Torr, substrate 1 temperature is 200-350 ℃
There is. The growth rate under this condition is 1000Å / min or more. Plasma is generated by applying a voltage.
次いで，同図（ｄ）に示すように,SiO2膜41が形成さ
れた基板１表面に,TEOS−O3系のガスを用いるCVD法によ
り，厚さ約0.4〜0.7μｍのSiO2膜５を堆積する。このCV
Dの条件の例は,TEOS中のバブリングするN2ガスおよびオ
ゾン発生装置におけるO2の流量が，それぞれ,3.5〜5.0S
CCMおよび5.0〜10.0SCCM,反応系の全圧が500〜700Torr,
基板１温度が375〜400℃である。これによりO2の流量の
５〜８％のO3がCVD装置に流入する。Then, as shown in FIG. 3D, a SiO 2 film 5 having a thickness of about 0.4 to 0.7 μm is formed on the surface of the substrate 1 on which the SiO 2 film 41 is formed by a CVD method using a TEOS-O 3 based gas. Deposit. This CV
As an example of the condition of D, the bubbling N 2 gas in TEOS and the O 2 flow rate in the ozone generator are 3.5 to 5.0 S, respectively.
CCM and 5.0 to 10.0 SCCM, total pressure of reaction system is 500 to 700 Torr,
The substrate 1 temperature is 375 to 400 ° C. As a result, 5 to 8% of the flow rate of O 2 O 3 flows into the CVD apparatus.
次いで，配線層３上の所定領域に,SiO2膜５およびSiO
2膜41を貫通するコンタクトホールを形成したのち,SiO2
膜５上に，例えばAl層を堆積し，これをパターンニング
して，同図（ｅ）に示すように，上層配線層６を形成す
る。Then, in a predetermined area on the wiring layer 3, the SiO 2 film 5 and the SiO 2 are formed.
After forming a contact hole passing through the 2 film 41, SiO 2
For example, an Al layer is deposited on the film 5 and is patterned to form an upper wiring layer 6 as shown in FIG.
本発明の別の実施例においては,SiO2膜41の形成を,Si
H4とO2との混合ガスを用いる減圧CVD法により行う。そ
の条件例は,SiH4およびO2の流量が，それぞれ,30〜50SC
CMおよび90〜150SCCM,反応系の全圧が0.3〜1.0Torr,基
板１温度が400〜430℃である。この条件の下での成長速
度は200〜500Å/minである。SiO2膜５の形成は前記実施
例と同様である。In another embodiment of the present invention, the SiO 2 film 41 is formed by Si
It is performed by a low pressure CVD method using a mixed gas of H 4 and O 2 . An example of the conditions is that the SiH 4 and O 2 flow rates are 30 to 50 SC, respectively.
CM and 90 to 150 SCCM, total reaction system pressure is 0.3 to 1.0 Torr, and substrate 1 temperature is 400 to 430 ° C. The growth rate under this condition is 200-500Å / min. The formation of the SiO 2 film 5 is the same as in the above-mentioned embodiment.
また，本発明のさらに別の実施例においては,SiO2膜4
1の形成を,SiH4とO2との混合ガスを用いる常圧CVD法に
より行う。その条件例は,SiH4およびO2の流量が，それ
ぞれ,40SCCMおよび800SCCM,反応系の圧力が760Torr,基
板１温度が400〜430℃である。SiO2膜５の形成は前記実
施例と同様である。In another embodiment of the present invention, the SiO 2 film 4 is used.
The formation of 1 is performed by the atmospheric pressure CVD method using a mixed gas of SiH 4 and O 2 . An example of the conditions is that the flow rates of SiH 4 and O 2 are 40 SCCM and 800 SCCM, respectively, the reaction system pressure is 760 Torr, and the substrate 1 temperature is 400 to 430 ° C. The formation of the SiO 2 film 5 is the same as in the above-mentioned embodiment.
また,SiO2膜41を，周知のスパッタリング法により，
とくに加熱しない基板１上に形成してもよい。本発明に
おいて,450℃以下の低温CVD法によりSiO2膜41を形成し
た場合，成長速度の下地依存性，とくに前記のような前
処理による影響が実質的に現れない。この理由について
は現在のところ不明である。Moreover, the SiO 2 film 41 is formed by a well-known sputtering method.
It may be formed on the substrate 1 which is not particularly heated. In the present invention, when the SiO 2 film 41 is formed by the low temperature CVD method at 450 ° C. or lower, the dependency of the growth rate on the base, particularly the influence of the pretreatment as described above, does not substantially appear. The reason for this is currently unknown.
本発明によれば,TEOS−O3系の原料ガスを用いるCVD法
により成長するSiO2膜の下地依存性の影響が現れなくな
り,TEOS−O3系CVDの特徴とする平坦表面を有するSiO2膜
の形成が可能となる。その結果，この上に形成される上
層配線層のカバレッジ不良に起因する障害が防止され，
多層配線を必須とする高密度集積回路の製造歩留りおよ
び信頼性を向上可能とする効果がある。According to the present invention, the influence of the underlayer dependence of the SiO 2 film grown by the CVD method using the TEOS-O 3 -based source gas disappears, and the SiO 2 with the flat surface characteristic of TEOS-O 3 -based CVD does not appear. A film can be formed. As a result, obstacles caused by poor coverage of the upper wiring layer formed on this are prevented,
This has the effect of improving the manufacturing yield and reliability of high-density integrated circuits that require multilayer wiring.
第１図は本発明の原理説明図， 第２図は本発明の実施例の工程説明図， 第３図はTEOS−O3系ガスにより成長するSiO2膜の下地依
存性を示すグラフ， 第４図は従来の問題点説明図 である。 図において， １は基板,2は絶縁層,3は配線層， ４と５と41はSiO2膜,6は上層配線層， 11は電極,31は導電層 である。FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a diagram for explaining the steps of the embodiment of the present invention, and FIG. 3 is a graph showing the underlayer dependence of a SiO 2 film grown by TEOS-O 3 system gas, Figure 4 is an illustration of the conventional problems. In the figure, 1 is a substrate, 2 is an insulating layer, 3 is a wiring layer, 4 and 5 and 41 are SiO 2 films, 6 is an upper wiring layer, 11 is an electrode, and 31 is a conductive layer.
Claims (5)
層とが表出する基板上に成長速度の下地選択性を示さな
い第１の化学気相成長法を用いて薄い酸化膜を形成する
工程と， シリコンアルコキシドとオゾンを成長原料ガスとする第
２の化学気相成長法を用いて厚い酸化膜を該薄い酸化膜
上に形成する工程 とを含むことを特徴とする半導体装置の製造方法。1. A step of forming a thin oxide film on a substrate on which a conductive layer made of a metal or a semiconductor and an insulating layer are exposed by using a first chemical vapor deposition method showing no underlayer selectivity of a growth rate. And a step of forming a thick oxide film on the thin oxide film by using a second chemical vapor deposition method using silicon alkoxide and ozone as a growth source gas, and a method for manufacturing a semiconductor device.
う低温化学気相成長法であることを特徴とする請求項１
記載の半導体装置の製造方法。2. The first chemical vapor deposition method is a low temperature chemical vapor deposition method performed at 450 ° C. or lower.
The manufacturing method of the semiconductor device described in the above.
と亜酸化窒素（N2O）を原料ガスとして用いるプラズマ
化学気相成長法であることを特徴とする請求項２記載の
半導体装置の製造方法。3. The first chemical vapor deposition method is silane (SiH 4 ).
3. The method of manufacturing a semiconductor device according to claim 2, wherein the plasma chemical vapor deposition method uses nitrous oxide (N 2 O) as a source gas.
と酸素（O2）を原料ガスとして用いる減圧化学気相成長
法であることを特徴とする請求項２記載の半導体装置の
製造方法。4. The first chemical vapor deposition method is silane (SiH 4 ).
The method for manufacturing a semiconductor device according to claim 2, wherein the method is a low pressure chemical vapor deposition method using oxygen and oxygen (O 2 ) as source gases.
と酸素（O2）を原料ガスとして用いる常圧化学気相成長
法であることを特徴とする請求項２記載の半導体装置の
製造方法。5. The first chemical vapor deposition method is silane (SiH 4 ).
3. The method of manufacturing a semiconductor device according to claim 2, wherein the atmospheric pressure chemical vapor deposition method uses oxygen and oxygen (O 2 ) as source gases.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22720290A JPH0810692B2 (en) | 1990-08-28 | 1990-08-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22720290A JPH0810692B2 (en) | 1990-08-28 | 1990-08-28 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04107924A JPH04107924A (en) | 1992-04-09 |
| JPH0810692B2 true JPH0810692B2 (en) | 1996-01-31 |
Family
ID=16857099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22720290A Expired - Lifetime JPH0810692B2 (en) | 1990-08-28 | 1990-08-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0810692B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0582724A1 (en) * | 1992-08-04 | 1994-02-16 | Siemens Aktiengesellschaft | Method of CVD deposition of SiO2 layers with local and global planarization on structured silicon substrates |
| JP2908200B2 (en) * | 1993-11-02 | 1999-06-21 | 日本電気株式会社 | Method for manufacturing semiconductor device |
-
1990
- 1990-08-28 JP JP22720290A patent/JPH0810692B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04107924A (en) | 1992-04-09 |
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