KR0179021B1 - Method of depositing double layered interlayer insulator - Google Patents
Method of depositing double layered interlayer insulator Download PDFInfo
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- KR0179021B1 KR0179021B1 KR1019910002364A KR910002364A KR0179021B1 KR 0179021 B1 KR0179021 B1 KR 0179021B1 KR 1019910002364 A KR1019910002364 A KR 1019910002364A KR 910002364 A KR910002364 A KR 910002364A KR 0179021 B1 KR0179021 B1 KR 0179021B1
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- dielectric film
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- interlayer insulating
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- 239000011229 interlayer Substances 0.000 title claims abstract description 61
- 238000000151 deposition Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 12
- 239000012212 insulator Substances 0.000 title 1
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000007796 conventional method Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000009413 insulation Methods 0.000 description 7
- 238000002360 preparation method Methods 0.000 description 5
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 IC 제조에 있어서 다층 금속배선의 층간절연막 형성시 플라즈마 화학기상증착 반응기를 이용하여 증착시키는 방법에 관한 것으로, 특히 층간절연막 하층 금속배선의 힐록성장을 최소화함과 동시에 층간절연막의 단차 피복성이 우수하도록 한 이중 층간절연막 증착방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of depositing an interlayer dielectric film using a plasma chemical vapor deposition reactor in the fabrication of a semiconductor IC. The present invention relates to a method for depositing a double interlayer dielectric film having excellent properties.
종래 기술의 층간절연막 증착방법은 층간절연막 하층 금속배선에 힐록이 성장되어 층간절연막의 절연특성을 저하시키고 층간절연막은 단차피복성이 불량하여 단선을 유발시키는 문제점이 있다.The conventional method for depositing the interlayer dielectric film has a problem in that hillock is grown on the metal layer under the interlayer dielectric film to degrade the insulating property of the interlayer dielectric film, and the interlayer dielectric film is poor in step coverage and causes disconnection.
이에 따라 본 발명은 상기한 문제점을 해결하기 위해 2단계 플라즈마 화학기상증착 반응기를 이용한 층간절연막 증착방법으로써, 금속배선이 완성된 실리콘기판을 반응기내에 장착시켜 일정온도와 시간에 의해 800~1500Å의 두께로 1단계 층간절연막을 형성하고, 상기 1단계 층간절연막상에 반응기 최종온도(350~400℃)의 범위에서 실리콘기판을 균열시킨후 2단계 층간절연막을 증착시키는 이중 층간절연막 증착방법에 관한 것이다.Accordingly, the present invention is an interlayer dielectric film deposition method using a two-step plasma chemical vapor deposition reactor to solve the above problems, by mounting a silicon substrate with metal wiring in the reactor thickness of 800 ~ 1500Å by a constant temperature and time The present invention relates to a double interlayer dielectric film deposition method in which a first stage interlayer dielectric film is formed, and a silicon substrate is cracked on the first stage interlayer dielectric film in a range of a reactor final temperature (350 to 400 ° C.).
Description
제1도는 종래의 층간절연막 단면도.1 is a cross-sectional view of a conventional interlayer insulating film.
제2도는 제1도에 있어서 온도와 시간의 변화를 나타낸 그래프도.FIG. 2 is a graph showing changes in temperature and time in FIG.
제3도는 본 발명의 이중 층간절연막 단면도.3 is a cross-sectional view of a double interlayer insulating film of the present invention.
제4도는 제3도에 있어서 온도와 시간의 변화를 나타낸 그래프도.4 is a graph showing changes in temperature and time in FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 층간절연막 하층 금속배선DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Interlayer insulation film Underlayer metal wiring
3 : 층간절연막 4 : 열산화막3: interlayer insulating film 4: thermal oxide film
5 : 반응기의 온도 5 : 층간절연막 형성중의 웨이퍼 온도5: reactor temperature 5: wafer temperature during interlayer dielectric film formation
7,7' : 층간절연막 형성준비시간 8 : 층간절연막 형성시간7,7 ': preparation time for interlayer insulation film 8: preparation time for interlayer insulation film
9,9' : 1단계 입힘시간과 온도 10 : 힐록9,9 ': 1st coating time and temperature 10: Hillock
11 : 단차피복성 불량11: poor step coverage
본 발명은 반도체 IC 제조에 있어서 다층 금속배선의 층간절연막 형성시 플라즈마 화학기상증착(PECVD)반응기를 이용하여 증착시키는 방법에 관한 것으로, 특히 층간절연막 하층 금속배선의 힐록(hillock) 성장을 최소화함과 동시에 층간절연막의 단차 피복성(step coverage)이 우수하도록 한 이중 층간절연막 증착방법에 관한 것이다.The present invention relates to a method of deposition using a plasma chemical vapor deposition (PECVD) reactor for the formation of an interlayer insulating film of a multi-layer metal wiring in the manufacture of semiconductor ICs, and in particular, to minimize the hillock growth of the lower metal wiring of the interlayer insulating film. At the same time, the present invention relates to a method for depositing a double interlayer insulating film in which the step coverage of the interlayer insulating film is excellent.
종래의 기술구성은 제1도에 도시된 바와같이 반도체 IC 제조의 다층금속배선을 채용하고, 플라즈마 화학기상증착방법을 이용하여 금속배선의 층간절연막(3)을 실리콘 질화물 또는 실리콘 산화물로써 증착시키는 경우 층간절연막 하층금속배선(2)이 완성된 실리콘기판(1)을 플라즈마 화학기상증착 반응기내에 장착시킨후, 상기 실리콘기판(1)에는 일정의 온도로 균열을 일으킨 뒤에 층간절연막(3)을 증착하도록 구성하고 있다.The prior art configuration employs a multilayer metal wiring of semiconductor IC fabrication as shown in FIG. 1, and when the interlayer insulating film 3 of the metal wiring is deposited with silicon nitride or silicon oxide using a plasma chemical vapor deposition method. After mounting the silicon substrate 1 on which the interlayer insulating layer lower metal wiring 2 was completed in a plasma chemical vapor deposition reactor, the silicon substrate 1 was cracked at a predetermined temperature and then the interlayer insulating film 3 was deposited. It consists.
상기한 종래 기술의 층간절연막 방법은 제1도에 도시된 바와 같이 층간절연막 하층금속배선(2)을 일반적인 알루미늄 또는 알루미늄 합금을 사용하여 형성시킨 실리콘기판(1)을 플라즈마 화학기상증착(PECVD)반응기 내로 장착한후 다음과 같은 처리조건에 의해 층간절연막(3)을 증착시킨다.In the above-described conventional interlayer insulating film method, as shown in FIG. 1, a plasma chemical vapor deposition (PECVD) reactor is used to form a silicon substrate (1) on which an interlayer insulating film lower layer metal wiring (2) is formed using a general aluminum or aluminum alloy. After mounting therein, the interlayer insulating film 3 is deposited by the following processing conditions.
우선 제2도에서 시간과 온도의 변화를 나타낸 바와같이 층간절연막(3) 성형시간(8)(약 30~60분)과 플라즈마 화학기상증착 반응기의 온도(5)250~400℃의 일정온도 범위에서 플라즈마 화학기상 증착반응기 내의 층간절연막(3)은 실리콘기판의 균열 및 개스 압력 등의 제어에 의해 증착되도록 조건을 확보하여, 제1도의 층간절연막(3)을 증착시킨후 개스공급중단 및 대기압으로 환원하여 플라즈마 화학기상증착 반응기를 개방하고 실리콘기판(1)을 탈착한다.First, as shown in FIG. 2, the time and temperature change are shown, the forming time of the interlayer insulating film 3 (8) (about 30 to 60 minutes) and the temperature of the plasma chemical vapor deposition reactor (5) are a constant temperature range of 250 to 400 ° C. In the plasma chemical vapor deposition reactor, the interlayer insulating film 3 in the plasma chemical vapor deposition reactor is ensured to be deposited by control of the crack and gas pressure of the silicon substrate, and the interlayer insulating film 3 of FIG. By reducing, the plasma chemical vapor deposition reactor is opened and the silicon substrate 1 is desorbed.
그리고 제2도에서는 플라즈마 화학기상증착 반응기의 온도(5)와 층간절연막 형성중의 웨이퍼온도(6) 및 준비시간(7), 형성시간(4)을 그래프로 나타내었고, 플라즈마 화학기상증착 반응기의 온도(5)를 250~300[℃]의 범위로 하는 경우 제1도(a)에 나타낸 바와같이 비교적 높은 온도에서 장시간 노출되어짐에 따른 층간절연막 하층금속배선(2)은 힐록(10)이 성장되어 층간절연막(3)의 절연특성을 저하시키고, 층간절연막(3)은 단차피복성이 불량(11)하여 단선을 유발시킨다.In FIG. 2, the temperature (5) of the plasma chemical vapor deposition reactor, the wafer temperature (6), the preparation time (7), and the formation time (4) during the formation of the interlayer dielectric film are shown graphically. When the temperature (5) is in the range of 250 to 300 [deg.] C., as shown in FIG. 1A, the heellock 10 grows as the interlayer insulating film lower layer metal wiring 2 is exposed for a long time at a relatively high temperature. As a result, the insulating properties of the interlayer insulating film 3 are lowered, and the interlayer insulating film 3 is poor in step coverage and causes breakage.
또한 플라즈마 화학기상증착 반응기의 온도(5)를 350°~400[℃]의 범위로 하는 경우 제1도(b)에 나타낸 바와같이 단차피복성은 우수하지만 고온에서 장시간 노출됨에 따른 층간절연막 하층 금속배선(2)의 힐록(10)성장에 의해 층간절연막(3)의 절연특성이 저하되는 문제점이 있었다.In addition, when the temperature (5) of the plasma chemical vapor deposition reactor is in the range of 350 ° to 400 [° C.], as shown in FIG. 1 (b), the step coverage is excellent, but the interlayer insulating film lower layer metal wiring due to long exposure at high temperature There was a problem that the insulating properties of the interlayer insulating film 3 were lowered due to the growth of the hillock 10 in (2).
이에 따른 본 발명은 상기한 문제점을 해결하기 위해 2단계 플라즈마 화학기상증착 반응기를 이용한 층간절연막 증착방법으로써, 우선 제3도에 도시된 바와같이 반도체 IC제조의 다층 금속배선을 채용하고, 금속배선의 층간절연막(3)을 플라즈마 화학기상증착방법을 이용한 실리콘 질화물이나 실리콘 산화물로써 증착시키는 경우 층간절연막 하층금속배선(2)을 알루미늄 또는 알루미늄합금으로 사용하여 완성된 실리콘기판(1)을 플라즈마 화학기상증착 반응기내에 장착한 후, 상기 실리콘기판(1)의 온도가 낮은 상태(150~200℃)에 있을 동안 1단계의 두께 800~1500Å(옴스트롱)의 층간절연막을 증착시키고, 2단계는 온도 350~400℃의 범위로 실리콘기판(1)을 균열시킨 다음 최소층간 절연막 두께만큼 증착시킨다.Accordingly, the present invention is an interlayer insulating film deposition method using a two-step plasma chemical vapor deposition reactor in order to solve the above problems, first, as shown in Figure 3 employs a multi-layer metal wiring of semiconductor IC manufacturing, In the case of depositing the interlayer insulating film 3 with silicon nitride or silicon oxide using the plasma chemical vapor deposition method, the silicon substrate 1, which is formed by using the interlayer insulating film lower layer metal wiring 2 as aluminum or an aluminum alloy, is deposited by plasma chemical vapor deposition. After mounting in the reactor, while the temperature of the silicon substrate 1 is in a low state (150-200 ° C.), an interlayer insulating film having a thickness of 800 to 1500 kW (Om Strong) is deposited in one step, and the temperature is 350 to The silicon substrate 1 is cracked in the range of 400 ° C. and then deposited by the minimum interlayer insulating film thickness.
이하, 상기한 본 발명의 층간절연막 증착방법 및 작용효과를 첨부된 도면에 따라 상세히 설명하면 다음과 같다.Hereinafter, the above-described interlayer insulating film deposition method and effect of the present invention will be described in detail with reference to the accompanying drawings.
우선 제3도에 도시된 바와같이 금속배선의 층간절연막(3)을 플라즈마 화학기상증착방법을 이용한 실리콘 질화물이나 실리콘 산화물로써 증착시키는 경우 층간절연막 하층금속배선(2)을 알루미늄 또는 알루미늄 합금으로 사용하여 완성된 실리콘기판(1)을 플라즈마 화학기상증착 반응기내에 장착시킨 후, 다음과 같은 2단계 처리조건에 의해 층간절연막을 증착시킨다. 우선 제4도에 층간절연막(3)을 입히는 시간과 온도를 나타낸 바와 같이 증착 절연막 형성전의 준비시간(7)(7')은 플라즈마 화학기상증착 반응기의 최종온도(5) 350~400℃사이의 일정온도로 실리콘기판(1)의 온도가 상승하기전이며, 1단계 층간절연막 증착온도(9') 150℃에 도달하는 시간(9) 5~10분 동안 개스 압력 등의 제어에 의해 층간절연막(3)을 증착하도록 조건을 확보하여 두께 800~1500Å(옴스트롱)의 1단계 층간절연막(3)을 증착시킨다.First, as shown in FIG. 3, when the interlayer insulating film 3 of the metal wiring is deposited with silicon nitride or silicon oxide using a plasma chemical vapor deposition method, the interlayer insulating film underlayer metal wiring 2 is used as aluminum or an aluminum alloy. After the completed silicon substrate 1 is mounted in a plasma chemical vapor deposition reactor, an interlayer insulating film is deposited by the following two-step processing conditions. First, as shown in FIG. 4, the time and temperature at which the interlayer insulating film 3 is applied, the preparation time (7) (7 ') before the deposition insulating film formation is performed between 350 and 400 ° C in the final temperature (5) of the plasma chemical vapor deposition reactor. Before the temperature of the silicon substrate 1 rises to a predetermined temperature, the first stage interlayer dielectric film deposition temperature (9 ') reaches a temperature of 150 DEG C. (9) for 5 to 10 minutes. 3) The conditions are ensured to deposit, and the first-level interlayer insulating film 3 having a thickness of 800 to 1500 kW (Om Strong) is deposited.
또한 2단계 층간절연막 형성전의 준비시간(7') 20~30분을 갖는후 플라즈마 화학기상증착 반응기의 최종온도(5) 350~400℃의 범위로 실리콘기판(1)을 균열시킨 뒤에 1단계 층간절연막 두께를 감안하여 최종 층간절연막(3) 두께만큼 층간절연막 형성시간(8) 동안 증착시키며, 상기 층간절연막(3) 증착후 개스공급중단 및 대기압으로 환원하여 플라즈마 화학기상증착 반응기를 개방하고 실리콘기판(1)을 탈착한다.In addition, after the preparation time (7 ') 20 to 30 minutes before the formation of the two-stage interlayer insulating film, the silicon substrate (1) is cracked in the range of 350 to 400 ° C. in the final temperature (5) of the plasma chemical vapor deposition reactor. In consideration of the thickness of the insulating film, the thickness of the final insulating film 3 is deposited for the formation time of the insulating film 8, and after the deposition of the insulating film 3, the gas supply is stopped and reduced to atmospheric pressure to open the plasma chemical vapor deposition reactor and the silicon substrate. Remove (1).
이와같은 본 발명인 2단계 층간절연막 증착방법에 있어서 먼저 1단계 증착을 실시하도록 하여 층간절연막 하층 금속배선 상의 힐록 성장을 억제시킬 수 있으므로 층간절연막의 절연특성을 우수하게 유지할 수 있고, 2단계 증착은 최종 층간절연막 두께만큼 증착함에 따라 단차 피복성을 우수하게 할 수 있다.In the two-step interlayer dielectric film deposition method of the present invention, first step deposition is performed to suppress hillock growth on the metal layer under the interlayer dielectric film, thereby maintaining excellent insulation characteristics of the interlayer dielectric film, and the second stage deposition By depositing the thickness of the interlayer insulating film, it is possible to improve the step coverage.
즉, 1단계 저온증착과 제2단계 고온증착을 연속적으로 함에 의해 저온증착의 문제점인 단차피복성 악화를 극복하고 고온 증착만을 실시할 경우에 생기는 층간절연막 하층금속선의 힐록성장에 기인한 층간절연막의 절연특성저하가 일어나지 않도록 하는 효과가 있다.That is, the interlayer insulation film resulting from the hillock growth of the metal layer under the interlayer insulation film produced when only the high temperature deposition is performed by overcoming the deterioration of the step coverage, which is a problem of the low temperature deposition, by continuously performing the first and second high temperature depositions. There is an effect that the insulation characteristic degradation does not occur.
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| KR1019910002364A KR0179021B1 (en) | 1991-02-12 | 1991-02-12 | Method of depositing double layered interlayer insulator |
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| KR1019910002364A KR0179021B1 (en) | 1991-02-12 | 1991-02-12 | Method of depositing double layered interlayer insulator |
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| KR0179021B1 true KR0179021B1 (en) | 1999-04-15 |
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