JP3172307B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3172307B2
JP3172307B2 JP00554693A JP554693A JP3172307B2 JP 3172307 B2 JP3172307 B2 JP 3172307B2 JP 00554693 A JP00554693 A JP 00554693A JP 554693 A JP554693 A JP 554693A JP 3172307 B2 JP3172307 B2 JP 3172307B2
Authority
JP
Japan
Prior art keywords
oxide film
plasma oxide
semiconductor device
forming
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP00554693A
Other languages
Japanese (ja)
Other versions
JPH06216118A (en
Inventor
章二 奥田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP00554693A priority Critical patent/JP3172307B2/en
Publication of JPH06216118A publication Critical patent/JPH06216118A/en
Application granted granted Critical
Publication of JP3172307B2 publication Critical patent/JP3172307B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に係り、特にプラズマ酸化膜の膜質の改善に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in the quality of a plasma oxide film.

【0002】近年のサブミクロンプロセスにより製造す
る微細化した半導体装置では、半導体装置の製造工程に
おいて形成する絶縁膜の膜厚を薄くしなければならない
ので膜質に対する要求が厳しくなっており、膜質が悪い
場合には特にトランジスタ特性の変動などに悪影響を及
ぼしている。
In a recent miniaturized semiconductor device manufactured by a submicron process, the thickness of an insulating film formed in a manufacturing process of the semiconductor device must be reduced, so that requirements for film quality are strict, and the film quality is poor. In such a case, the variation in transistor characteristics is adversely affected.

【0003】以上のような状況から、半導体装置の微細
化に対応することが可能な絶縁膜を形成することが可能
な半導体装置の製造方法が要望されている。
[0005] Under the circumstances described above, there is a demand for a method of manufacturing a semiconductor device capable of forming an insulating film capable of coping with miniaturization of the semiconductor device.

【0004】[0004]

【従来の技術】従来の半導体装置の製造方法について図
3により詳細に説明する。図3は従来の半導体装置の製
造方法を工程順に示す側断面図である。
2. Description of the Related Art A conventional method for manufacturing a semiconductor device will be described in detail with reference to FIG. FIG. 3 is a side sectional view showing a conventional method of manufacturing a semiconductor device in the order of steps.

【0005】まず図3(a) に示すように半導体基板11の
表面にアルミ配線層12を形成し、この半導体基板11とア
ルミ配線層12とを被覆する膜厚 3,000Å程度のプラズマ
酸化膜13をプラズマ法により形成し、このプラズマ酸化
膜13の表面にSOG膜14を塗布して形成する。
First, as shown in FIG. 3A, an aluminum wiring layer 12 is formed on the surface of a semiconductor substrate 11, and a plasma oxide film 13 having a thickness of about 3,000 mm covering the semiconductor substrate 11 and the aluminum wiring layer 12. Is formed by a plasma method, and an SOG film 14 is applied on the surface of the plasma oxide film 13 to form the same.

【0006】つぎに図3(b) に示すようにアルミ配線層
12の表面に形成したプラズマ酸化膜13が露出するまでS
OG膜14を除去するエッチバックを行う。ついで図3
(c) に示すように全表面にPSG膜15を形成する。
[0006] Next, as shown in FIG.
12 until the plasma oxide film 13 formed on the surface of
Etchback for removing the OG film 14 is performed. Then Figure 3
A PSG film 15 is formed on the entire surface as shown in FIG.

【0007】その後、これらのプラズマ酸化膜13、SO
G膜14、PSG膜15からなる絶縁膜を、流量7,500 sccm
の窒素ガスと流量7,500 sccmの水素ガスの混合ガス雰囲
気中にて摂氏 450度で30分間アニール処理を行ってい
る。
Thereafter, these plasma oxide films 13 and SO
The insulating film composed of the G film 14 and the PSG film 15 is coated at a flow rate of 7,500 sccm.
Annealing is performed at 450 degrees Celsius for 30 minutes in a mixed gas atmosphere of nitrogen gas and hydrogen gas at a flow rate of 7,500 sccm.

【0008】[0008]

【発明が解決しようとする課題】以上説明した従来の半
導体装置の製造方法においては、プラズマ酸化膜の表面
にSOG膜やPSG膜を被着形成した後に、窒素ガスと
水素ガスの混合ガス雰囲気中にてアニールを行っている
ので、プラズマ酸化膜やSOG膜に含有している水分を
完全に除去することができないため、完成した半導体装
置のトランジスタ特性に悪影響を及ぼしているという問
題点があった。
In the above-described conventional method of manufacturing a semiconductor device, after an SOG film or a PSG film is formed on the surface of a plasma oxide film, it is placed in a mixed gas atmosphere of nitrogen gas and hydrogen gas. , The moisture contained in the plasma oxide film or the SOG film cannot be completely removed, which has a problem that the transistor characteristics of the completed semiconductor device are adversely affected. .

【0009】本発明は以上のような状況から、簡単且つ
容易に行える工程の改良により、微細化した半導体装置
において水分を透過しない絶縁膜を形成することが可能
となる半導体装置の製造方法の提供を目的としたもので
ある。
In view of the above, the present invention provides a method of manufacturing a semiconductor device capable of forming an insulating film that does not transmit moisture in a miniaturized semiconductor device by improving a process that can be performed easily and easily. It is intended for.

【0010】[0010]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板上に配線層を形成し、この配線層
及びこの半導体基板の表面にプラズマ酸化膜を被着して
形成する第1の工程と、水素ガスと酸素ガスの混合ガス
雰囲気中においてアニールする第2の工程と、このプラ
ズマ酸化膜の表面にテトラ・エチル・オルソ・シリケー
トからなるプラズマ酸化膜を被着して形成する第3の工
程と、このテトラ・エチル・オルソ・シリケートからな
るプラズマ酸化膜の表面を平坦にする絶縁膜を被着して
形成する第4の工程とを含むように構成する。
According to a method of manufacturing a semiconductor device of the present invention, a wiring layer is formed on a semiconductor substrate, and a plasma oxide film is formed on the wiring layer and the surface of the semiconductor substrate. Step 1, annealing in a mixed gas atmosphere of hydrogen gas and oxygen gas, and forming a plasma oxide film made of tetra-ethyl-ortho-silicate on the surface of the plasma oxide film It is configured to include a third step and a fourth step of applying and forming an insulating film for flattening the surface of the plasma oxide film made of tetra-ethyl-ortho-silicate.

【0011】この第2の工程は、水素ガスと酸素ガスの
混合ガス雰囲気に代替して、酸素ガス雰囲気中或いは窒
素ガスと水素ガスとの混合ガス雰囲気中においても行う
ことが可能である。
In the second step, hydrogen gas and oxygen gas are mixed.
Instead of the mixed gas atmosphere, it is also possible to perform the treatment in an oxygen gas atmosphere or a mixed gas atmosphere of nitrogen gas and hydrogen gas.

【0012】[0012]

【作用】即ち本発明においては、半導体基板上に形成し
た配線層及びこの半導体基板の表面にプラズマ酸化膜を
被着した後、水素ガスと酸素ガスの混合ガス雰囲気中或
いは酸素ガス雰囲気中或いは窒素ガスと水素ガスの混合
ガス雰囲気中においてアニールした後、テトラ・エチル
・オルソ・シリケートからなるプラズマ酸化膜を被着し
て形成し、このテトラ・エチル・オルソ・シリケートか
らなるプラズマ酸化膜の表面を平坦にする絶縁膜を被着
して形成するので、プラズマ酸化膜のアニールを直接か
つ確実に行うことが可能であり、完成した半導体装置の
トランジスタ特性の劣化を防止することが可能となる。
According to the present invention, a plasma oxide film is deposited on a wiring layer formed on a semiconductor substrate and a surface of the semiconductor substrate, and then a mixed gas atmosphere of hydrogen gas and oxygen gas, an oxygen gas atmosphere, or After annealing in a mixed gas atmosphere of gas and hydrogen gas, a plasma oxide film made of tetra-ethyl-ortho-silicate is deposited and formed, and the surface of the plasma oxide film made of tetra-ethyl-ortho-silicate is formed. Since the insulating film to be flattened is formed, the plasma oxide film can be directly and reliably annealed, and deterioration of transistor characteristics of the completed semiconductor device can be prevented.

【0013】[0013]

【実施例】以下図1により本発明の一実施例を工程順
に、図2により本発明による一実施例の効果について詳
細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG.

【0014】図1は本発明による一実施例を工程順に示
す側断面図、図2は本発明による一実施例の処理方法に
より処理したRFプラズマ酸化膜の耐湿性劣化度を示す
図である。
FIG. 1 is a side sectional view showing an embodiment according to the present invention in the order of steps, and FIG. 2 is a view showing the degree of deterioration of the moisture resistance of an RF plasma oxide film processed by the processing method of the embodiment according to the present invention.

【0015】本発明による一実施例においてはまず図1
(a) に示すように、半導体基板1の表面に膜厚1μm 程
度のアルミ配線層2を形成し、このアルミ配線層2と半
導体基板1の全面に平行平板型プラズマ装置を用いて膜
厚 3,000Åのプラズマ酸化膜3を形成する。
In one embodiment of the present invention, FIG.
1A, an aluminum wiring layer 2 having a thickness of about 1 μm is formed on the surface of a semiconductor substrate 1, and the aluminum wiring layer 2 and the entire surface of the semiconductor substrate 1 are subjected to a film thickness of 3,000 using a parallel plate type plasma apparatus. The plasma oxide film 3 of Å is formed.

【0016】つぎにこの状態の半導体基板1をアニール
炉内に載置し、流量7,500 sccmの水素ガスと流量5,000
sccmの酸素ガスの混合ガス雰囲気中にて摂氏 450度で30
分間アニール処理を行っている。
Next, the semiconductor substrate 1 in this state is placed in an annealing furnace, and hydrogen gas at a flow rate of 7,500 sccm and flow rate of 5,000 sc
30 at 450 degrees Celsius in a mixed gas atmosphere of oxygen gas of sccm
Minute annealing process.

【0017】ついで図1(b) に示すように、この処理を
行ったプラズマ酸化膜3の表面にテトラ・エチル・オル
ソ・シリケートからなるプラズマ酸化膜4(以下、TE
OSプラズマ酸化膜4と略称する)を形成する。
Then, as shown in FIG. 1B, a plasma oxide film 4 (hereinafter referred to as TE) made of tetra-ethyl-ortho-silicate is formed on the surface of the plasma oxide film 3 which has been subjected to this treatment.
OS plasma oxide film 4).

【0018】その後図1(c) に示すように、このTEO
Sプラズマ酸化膜4の表面を平坦にする絶縁膜、例えば
SOG膜5をスピナーを用いて塗布して形成する。本実
施例においては、アニール処理を水素ガスと酸素ガスの
混合ガス雰囲気中にて行ったが、流量5,000 sccmの酸素
ガスのみ或いは流量7,500 sccmの窒素ガスと流量7,500
sccmの水素ガスの混合ガス雰囲気中において同じ温度、
同じ時間のアニール処理を行うことも可能である。
Thereafter, as shown in FIG.
An insulating film for flattening the surface of the S plasma oxide film 4, for example, an SOG film 5 is formed by applying using a spinner. In the present embodiment, the annealing was performed in a mixed gas atmosphere of hydrogen gas and oxygen gas, but only oxygen gas at a flow rate of 5,000 sccm or nitrogen gas at a flow rate of 7,500 sccm and a flow rate of 7,500 sccm were used.
The same temperature in a mixed gas atmosphere of hydrogen gas of sccm,
It is also possible to perform annealing for the same time.

【0019】このようにして絶縁膜を形成した半導体装
置を気圧2気圧、温度摂氏 121度の容器内でプレッシャ
ー・クッカーテストを行うと、それぞれの半導体装置の
プレッシャー・クッカーテスト時間に対する劣化度は図
2に示すようになる。
When the pressure-cooker test is performed on the semiconductor device on which the insulating film is formed in a container at a pressure of 2 atm and a temperature of 121 ° C., the degree of deterioration of each semiconductor device with respect to the pressure-cooker test time is shown in FIG. As shown in FIG.

【0020】図2の縦軸は赤外線吸収ピーク面積を比較
した劣化度を示している。アニール処理を行わないもの
は図に「処理なし」と示すように70時間程度で完全に劣
化するが、窒素ガスと水素ガスの混合ガス雰囲気中にお
いてアニール処理したものは「N2 +H2 」と示すよう
に 200時間程度で完全に劣化する。酸素ガスのみの雰囲
気中においてアニール処理したものは「O2 」と示すよ
うに 250時間程度で完全に劣化する。水素ガスと酸素ガ
スの混合ガス雰囲気中においてアニール処理したものは
「H2 +O2 」と示すように 250時間経過しても、なお
劣化度0.8 程度を維持している。
The vertical axis in FIG. 2 shows the degree of deterioration in comparison of the infrared absorption peak areas. In the case where no annealing treatment is performed, as shown in the figure, "no treatment" is shown, the deterioration completely occurs in about 70 hours, but in the case of annealing treatment in a mixed gas atmosphere of nitrogen gas and hydrogen gas, "N 2 + H 2 " As shown, it deteriorates completely in about 200 hours. Those annealed in an oxygen gas only atmosphere of completely deteriorated in about 250 hours as shown as "O 2". Those annealed in a mixed gas atmosphere of hydrogen gas and oxygen gas are maintained even after the lapse of 250 hours as shown as "H 2 + O 2", it noted a degree deterioration degree 0.8.

【0021】このように、まずプラズマ酸化膜3を形成
した直後にこのプラズマ酸化膜3のアニール処理を行う
ので、この処理によって外部からの水分の侵入を遮断す
ることが可能な耐湿性の良い絶縁膜を形成することがで
きる。
As described above, since the plasma oxide film 3 is annealed immediately after the plasma oxide film 3 is first formed, the insulating film having good moisture resistance can block the invasion of moisture from the outside by this process. A film can be formed.

【0022】[0022]

【発明の効果】以上の説明から明らかなように、本発明
によれば極めて簡単な工程の変更により、半導体装置の
絶縁膜の膜質を改善することが可能となる利点があり、
著しい経済的及び、信頼性向上の効果が期待できる半導
体装置の製造方法の提供が可能である。
As is apparent from the above description, according to the present invention, there is an advantage that the film quality of the insulating film of the semiconductor device can be improved by a very simple process change.
It is possible to provide a method of manufacturing a semiconductor device which can be expected to be significantly economical and to have an effect of improving reliability.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明による一実施例を工程順に示す側断面
図、
FIG. 1 is a side sectional view showing an embodiment according to the present invention in the order of steps;

【図2】 本発明による一実施例の処理方法により処理
したRFプラズマ酸化膜の耐湿性劣化度を示す図、
FIG. 2 is a diagram showing the degree of deterioration of moisture resistance of an RF plasma oxide film processed by the processing method according to one embodiment of the present invention;

【図3】 従来の半導体装置の製造方法を工程順に示す
側断面図、
FIG. 3 is a side sectional view showing a conventional method of manufacturing a semiconductor device in the order of steps;

【符号の説明】[Explanation of symbols]

1は半導体基板、2はアルミ配線層、3はプラズマ酸化
膜、4はTEOSプラズマ酸化膜、5はSOG膜、
1 is a semiconductor substrate, 2 is an aluminum wiring layer, 3 is a plasma oxide film, 4 is a TEOS plasma oxide film, 5 is an SOG film,

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平4−118927(JP,A) 特開 平5−343542(JP,A) 特開 平6−163521(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/316 H01L 21/768 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-118927 (JP, A) JP-A-5-343542 (JP, A) JP-A-6-163521 (JP, A) (58) Field (Int.Cl. 7 , DB name) H01L 21/316 H01L 21/768

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体基板上に配線層を形成し、該配線
層及び前記半導体基板の表面にプラズマ酸化膜を被着し
て形成する第1の工程と、 水素ガスと酸素ガスの混合ガス雰囲気中においてアニー
ルする第2の工程と、 前記プラズマ酸化膜の表面にテトラ・エチル・オルソ・
シリケートからなるプラズマ酸化膜を被着して形成する
第3の工程と、 前記テトラ・エチル・オルソ・シリケートからなるプラ
ズマ酸化膜の表面を平坦にする絶縁膜を被着して形成す
る第4の工程と、 を含むことを特徴とする半導体装置の製造方法。
A first step of forming a wiring layer on a semiconductor substrate and applying a plasma oxide film on the wiring layer and the surface of the semiconductor substrate to form a mixed gas atmosphere of hydrogen gas and oxygen gas; A second step of annealing in the inside, and tetra-ethyl-ortho.
A third step of depositing and forming a plasma oxide film of silicate; and a fourth step of depositing and forming an insulating film for flattening the surface of the plasma oxide film of tetra-ethyl-ortho-silicate. A method for manufacturing a semiconductor device, comprising:
【請求項2】 半導体基板上に配線層を形成し、該配線
層及び前記半導体基板の表面にプラズマ酸化膜を被着し
て形成する第1の工程と、 酸素ガス雰囲気中においてアニールする第2の工程と、 前記プラズマ酸化膜の表面にテトラ・エチル・オルソ・
シリケートからなるプラズマ酸化膜を被着して形成する
第3の工程と、 前記テトラ・エチル・オルソ・シリケートからなるプラ
ズマ酸化膜の表面を平坦にする絶縁膜を被着して形成す
る第4の工程と、 を含む ことを特徴とする半導体装置の製造方法。
2. A wiring layer is formed on a semiconductor substrate.
Depositing a plasma oxide film on the surface of the layer and the semiconductor substrate
A first step of forming by plasma etching , a second step of annealing in an oxygen gas atmosphere, and a step of forming a tetra-ethyl-ortho-
Deposition by forming a plasma oxide film made of silicate
A third step, and a step of preparing the tetra-ethyl-ortho-silicate
Deposits an insulating film to flatten the surface of the zuma oxide film.
The method of manufacturing a semiconductor device comprising: the fourth step, characterized in that it comprises that.
【請求項3】 半導体基板上に配線層を形成し、該配線
層及び前記半導体基板の表面にプラズマ酸化膜を被着し
て形成する第1の工程と、 窒素ガスと水素ガスの混合ガス雰囲気中においてアニー
ルする第2の工程と、 前記プラズマ酸化膜の表面にテトラ・エチル・オルソ・
シリケートからなるプラズマ酸化膜を被着して形成する
第3の工程と、 前記テトラ・エチル・オルソ・シリケートからなるプラ
ズマ酸化膜の表面を平坦にする絶縁膜を被着して形成す
る第4の工程と、 を含む ことを特徴とする半導体装置の製造方法。
3. A wiring layer is formed on a semiconductor substrate.
Depositing a plasma oxide film on the surface of the layer and the semiconductor substrate
A second step of annealing in a mixed gas atmosphere of nitrogen gas and hydrogen gas, and a step of forming a tetra-ethyl-ortho-
Deposition by forming a plasma oxide film made of silicate
A third step, and a step of preparing the tetra-ethyl-ortho-silicate
Deposits an insulating film to flatten the surface of the zuma oxide film.
The method of manufacturing a semiconductor device comprising: the fourth step, characterized in that it comprises that.
JP00554693A 1993-01-18 1993-01-18 Method for manufacturing semiconductor device Expired - Lifetime JP3172307B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP00554693A JP3172307B2 (en) 1993-01-18 1993-01-18 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP00554693A JP3172307B2 (en) 1993-01-18 1993-01-18 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH06216118A JPH06216118A (en) 1994-08-05
JP3172307B2 true JP3172307B2 (en) 2001-06-04

Family

ID=11614194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP00554693A Expired - Lifetime JP3172307B2 (en) 1993-01-18 1993-01-18 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3172307B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3211950B2 (en) 1998-01-19 2001-09-25 日本電気株式会社 Semiconductor device and method of manufacturing the same
KR100583619B1 (en) * 1999-10-01 2006-05-26 삼성전자주식회사 Manufacturing method for semiconductor device
JP4285184B2 (en) * 2003-10-14 2009-06-24 東京エレクトロン株式会社 Film forming method and film forming apparatus
JP5813303B2 (en) * 2009-11-20 2015-11-17 株式会社日立国際電気 Semiconductor device manufacturing method, substrate processing method, and substrate processing apparatus

Also Published As

Publication number Publication date
JPH06216118A (en) 1994-08-05

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