JPH0713872B2 - 半導体記憶装置 - Google Patents

半導体記憶装置

Info

Publication number
JPH0713872B2
JPH0713872B2 JP62295517A JP29551787A JPH0713872B2 JP H0713872 B2 JPH0713872 B2 JP H0713872B2 JP 62295517 A JP62295517 A JP 62295517A JP 29551787 A JP29551787 A JP 29551787A JP H0713872 B2 JPH0713872 B2 JP H0713872B2
Authority
JP
Japan
Prior art keywords
transistor
selection
write
bit line
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62295517A
Other languages
English (en)
Japanese (ja)
Other versions
JPH01137491A (ja
Inventor
哲哉 松村
雅彦 吉本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62295517A priority Critical patent/JPH0713872B2/ja
Priority to DE3827287A priority patent/DE3827287A1/de
Priority to US07/266,057 priority patent/US4935896A/en
Publication of JPH01137491A publication Critical patent/JPH01137491A/ja
Publication of JPH0713872B2 publication Critical patent/JPH0713872B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/067—Single-ended amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
JP62295517A 1987-11-24 1987-11-24 半導体記憶装置 Expired - Fee Related JPH0713872B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP62295517A JPH0713872B2 (ja) 1987-11-24 1987-11-24 半導体記憶装置
DE3827287A DE3827287A1 (de) 1987-11-24 1988-08-11 Halbleiterspeichereinrichtung
US07/266,057 US4935896A (en) 1987-11-24 1988-11-02 Semiconductor memory device having three-transistor type memory cells structure without additional gates

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62295517A JPH0713872B2 (ja) 1987-11-24 1987-11-24 半導体記憶装置

Publications (2)

Publication Number Publication Date
JPH01137491A JPH01137491A (ja) 1989-05-30
JPH0713872B2 true JPH0713872B2 (ja) 1995-02-15

Family

ID=17821645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62295517A Expired - Fee Related JPH0713872B2 (ja) 1987-11-24 1987-11-24 半導体記憶装置

Country Status (3)

Country Link
US (1) US4935896A (enrdf_load_stackoverflow)
JP (1) JPH0713872B2 (enrdf_load_stackoverflow)
DE (1) DE3827287A1 (enrdf_load_stackoverflow)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2600304B2 (ja) * 1988-06-30 1997-04-16 三菱電機株式会社 半導体記憶装置とこれを用いたデータパス
JP2683919B2 (ja) * 1988-07-29 1997-12-03 三菱電機株式会社 半導体記憶装置
US5293563A (en) * 1988-12-29 1994-03-08 Sharp Kabushiki Kaisha Multi-level memory cell with increased read-out margin
US5121353A (en) * 1989-07-06 1992-06-09 Kabushiki Kaisha Toshiba Ferroelectric capacitor memory circuit MOS setting and transmission transistor
US5206834A (en) * 1989-10-14 1993-04-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device performing last in-first out operation and the method for controlling the same
US5325325A (en) * 1990-03-30 1994-06-28 Sharp Kabushiki Kaisha Semiconductor memory device capable of initializing storage data
JPH04305889A (ja) * 1991-04-02 1992-10-28 Mitsubishi Electric Corp シーケンシャルアクセスメモリ
JPH0520865A (ja) * 1991-07-16 1993-01-29 Mitsubishi Electric Corp メモリセル回路，非同期式シリアルアクセスメモリ装置および非同期式ランダムアクセスメモリ装置
JP3481263B2 (ja) * 1992-02-19 2003-12-22 株式会社リコー シリアル記憶装置
JP2676177B2 (ja) * 1992-08-12 1997-11-12 三菱電機株式会社 半導体メモリ
JP2921812B2 (ja) * 1992-12-24 1999-07-19 シャープ株式会社 不揮発性半導体記憶装置
US5414656A (en) * 1994-03-23 1995-05-09 Kenney; Donald M. Low charge consumption memory
JPH08147968A (ja) * 1994-09-19 1996-06-07 Mitsubishi Electric Corp ダイナミックメモリ
US5847577A (en) * 1995-02-24 1998-12-08 Xilinx, Inc. DRAM memory cell for programmable logic devices
US5581198A (en) * 1995-02-24 1996-12-03 Xilinx, Inc. Shadow DRAM for programmable logic devices
JPH097373A (ja) * 1995-06-20 1997-01-10 Oki Electric Ind Co Ltd 半導体記憶装置
JPH09162304A (ja) * 1995-12-12 1997-06-20 Mitsubishi Electric Corp 半導体記憶装置
US5646903A (en) * 1996-03-06 1997-07-08 Xilinx, Inc. Memory cell having a shared read/write line
JPH1050058A (ja) * 1996-07-30 1998-02-20 Kawasaki Steel Corp 半導体記憶装置
EP0844617A3 (en) * 1996-11-25 1999-06-16 Texas Instruments Incorporated Improvements in or relating to electronic circuits
US5784328A (en) * 1996-12-23 1998-07-21 Lsi Logic Corporation Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array
US5982659A (en) * 1996-12-23 1999-11-09 Lsi Logic Corporation Memory cell capable of storing more than two logic states by using different via resistances
US5761110A (en) * 1996-12-23 1998-06-02 Lsi Logic Corporation Memory cell capable of storing more than two logic states by using programmable resistances
US5847990A (en) * 1996-12-23 1998-12-08 Lsi Logic Corporation Ram cell capable of storing 3 logic states
US5771187A (en) * 1996-12-23 1998-06-23 Lsi Logic Corporation Multiple level storage DRAM cell
US5808932A (en) * 1996-12-23 1998-09-15 Lsi Logic Corporation Memory system which enables storage and retrieval of more than two states in a memory cell
US6016268A (en) * 1997-02-18 2000-01-18 Richard Mann Three transistor multi-state dynamic memory cell for embedded CMOS logic applications
JPH11126491A (ja) * 1997-08-20 1999-05-11 Fujitsu Ltd 半導体記憶装置
JP3099789B2 (ja) 1997-10-20 2000-10-16 日本電気株式会社 移動通信システムにおけるハンドオフ制御方法
US5956350A (en) * 1997-10-27 1999-09-21 Lsi Logic Corporation Built in self repair for DRAMs using on-chip temperature sensing and heating
US5909404A (en) * 1998-03-27 1999-06-01 Lsi Logic Corporation Refresh sampling built-in self test and repair circuit
US5995433A (en) * 1998-05-22 1999-11-30 Taiwan Semiconductor Manufacturing Co., Ltd. Three-transistor type DRAM with a refresh circuit
US6317365B1 (en) * 1998-06-24 2001-11-13 Yamaha Corporation Semiconductor memory cell
US6420746B1 (en) 1998-10-29 2002-07-16 International Business Machines Corporation Three device DRAM cell with integrated capacitor and local interconnect
US6078513A (en) * 1999-06-09 2000-06-20 Neomagic Corp. NMOS dynamic content-addressable-memory CAM cell with self-booting pass transistors and local row and column select
JP2002140890A (ja) * 2000-10-31 2002-05-17 Hitachi Ltd 半導体装置
US6353558B1 (en) * 2000-12-28 2002-03-05 International Business Machines Corporation Method and apparatus for writing to memory cells
US7221580B1 (en) * 2003-08-27 2007-05-22 Analog Devices, Inc. Memory gain cell
DE10344604B4 (de) * 2003-09-25 2011-08-11 Infineon Technologies AG, 81669 Speichereinheit mit Sammelelektroden
JP4832004B2 (ja) * 2005-06-09 2011-12-07 パナソニック株式会社 半導体記憶装置
US7295474B2 (en) * 2005-06-30 2007-11-13 Intel Corporation Operating an information storage cell array
US7898894B2 (en) * 2006-04-12 2011-03-01 International Business Machines Corporation Static random access memory (SRAM) cells
US8009459B2 (en) * 2008-12-30 2011-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit for high speed dynamic memory
KR101842413B1 (ko) 2009-12-28 2018-03-26 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
CN102714184B (zh) 2009-12-28 2016-05-18 株式会社半导体能源研究所 半导体器件
CN102742003B (zh) * 2010-01-15 2015-01-28 株式会社半导体能源研究所 半导体器件
KR101798367B1 (ko) 2010-01-15 2017-11-16 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP2012133841A (ja) * 2010-12-21 2012-07-12 Toshiba Corp 半導体記憶装置
US9087565B2 (en) * 2012-11-20 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pre-charging a data line

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3618053A (en) * 1969-12-31 1971-11-02 Westinghouse Electric Corp Trapped charge memory cell
US3699544A (en) * 1971-05-26 1972-10-17 Gen Electric Three transistor memory cell
BE788583A (fr) * 1971-09-16 1973-01-02 Intel Corp Cellule a trois lignes pour memoire a circuit integre a acces aleatoir
US4025007A (en) * 1974-08-16 1977-05-24 Herbert Kaniut Shifting horizontal tail with helical motions
JPS5539073B2 (enrdf_load_stackoverflow) * 1974-12-25 1980-10-08
US4025907A (en) * 1975-07-10 1977-05-24 Burroughs Corporation Interlaced memory matrix array having single transistor cells
US4247919A (en) * 1979-06-15 1981-01-27 Texas Instruments Incorporated Low power quasi-static storage cell
US4308594A (en) * 1980-01-31 1981-12-29 Mostek Corporation MOS Memory cell
JPS6020388A (ja) * 1983-07-14 1985-02-01 Nec Corp 半導体メモリ

Also Published As

Publication number Publication date
US4935896A (en) 1990-06-19
JPH01137491A (ja) 1989-05-30
DE3827287C2 (enrdf_load_stackoverflow) 1993-04-08
DE3827287A1 (de) 1989-06-08

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