JPH06314785A - Thin film semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce leak current between a gate electrode and a drain area and prevent conduction when a semiconductor area is charged by permitting the conductivity type of a part under the gate electrode at the external periphery of the semiconductor area to be the opposite to that of the source/drain areas of a semiconductor area. CONSTITUTION:A thin film transistor is formed on a substrate 11, a thin film semiconductor area is actually separated into source/drain areas 13 and an intrinsic channel forming area 12 which is formed under a gate electrode 17, and a gate insulating film 15 is provided by covering the semiconductor area. Impurity areas 13 are provided with contact holes through an layer insulator 19 and electrodes/wiring 18 are formed. Areas 14 of the conductivity type opposite to that of the source/drain areas 13 of the island-shaped semiconductor area 10 at the bottom of the gate electrode 17 are provided. When the impurity area 13 is N-type, an impurity of P-type conductivity is introduced. When the impurity area is of p-type, an impurity of N-type conductivity is introduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and manufacturing method of a circuit element used in a thin film integrated circuit, for example, a thin film transistor (TFT). The thin film transistor manufactured by the present invention is on an insulating substrate such as glass,
It is formed on any insulator formed on a semiconductor substrate such as single crystal silicon.

[0002]

2. Description of the Related Art Conventionally, a thin film transistor is formed by patterning a thin film semiconductor region (active layer) in an island shape, and then forming an insulating film as a gate insulating film by a CVD method or a sputtering method, and then forming a gate film thereon. The electrode was formed.

[0003]

The insulating coating formed by the CVD method or the sputtering method has a poor step coverage (step coverage), which adversely affects reliability, yield, and characteristics. FIG. 5 is a top view of a typical conventional TFT,
And a cross-sectional view taken along line AA ′ and BB ′ of the drawing. The TFT is formed on the substrate 51, the thin film semiconductor region is located below the impurity region (source / drain region, which shows N type conductivity here) 53 and the gate electrode 57, and is a substantially intrinsic channel forming region. A gate insulating film 55 is provided so as to cover the semiconductor region. A contact hole is opened in the impurity region 53 through an interlayer insulator 59, and an electrode / wiring 58 is provided.

As can be seen from the figure, the coverage of the end portion of the semiconductor region of the gate insulating film 55 is extremely poor, and typically only half the thickness of the flat portion is present. Generally, when the island-shaped semiconductor region is thick, it is extremely large. Particularly, from the AA 'cross section along the gate electrode, it can be seen that such deterioration of the covering property adversely affects the characteristics, reliability and yield of the TFT. That is, paying attention to the region 56 indicated by the dotted circle in the AA ′ sectional view of FIG. 5, the electric field of the gate electrode 57 is intensively applied to the end portion of the thin film semiconductor region. That is, since the thickness of the gate insulating film in this portion is half that of the flat portion, the electric field strength thereof is doubled.

As a result, the gate insulating film in the region 56 is easily destroyed by applying a high voltage for a long time. If the signal applied to the gate electrode is positive, the semiconductor in this region 56 is also N-type, so that the gate electrode 57 and the impurity region 58 (particularly, the drain region) become conductive, which causes deterioration in reliability. Becomes Further, when a voltage opposite to the normal voltage (a positive voltage to the drain and a negative voltage to the gate in the N-channel transistor) is applied to the gate electrode, the current (off current) flowing between the source and the drain increases. Oops. Typically, this off-current cannot be reduced, preferably below 1 × 10 ⁻¹² A.

When the gate insulating film is destroyed,
It happens that some charge is trapped, for example
If the negative charges are trapped, the semiconductor in the region 56 exhibits N-type and a path (passage) of the same conductivity type as the source / drain is formed irrespective of the voltage applied to the gate electrode. Therefore, the two impurity regions 58 become electrically conductive in the peripheral portion on the side of the island-shaped semiconductor region, which deteriorates the characteristics. Further, in order to use the TFT without causing the above deterioration, it is necessary to apply only half the voltage. However, this cannot fully utilize the performance of the TFT.

The presence of such a weak portion in a part of the TFT means that the TFT is easily destroyed due to charging or the like in the manufacturing process, which is a major factor for lowering the yield. An object of the present invention is to solve such a problem.

[0008]

The present invention is characterized in that the semiconductor in such an electrically weak region is complemented by reversing the conductivity type of the impurity regions forming the source and drain. Then, the area is 0.05 to 5 μm,
It is preferable to suppress the current leakage by making the width of 0.1 to 1 μm (width in the flat portion viewed from above). A typical structure of the present invention is shown in FIG. FIG. 1 is a drawing of the TFT as seen from above, and its AA ′ and B− are similar to FIG.
The sectional view of B'section is shown. The TFT is formed on the substrate 11, the thin film semiconductor region is an impurity region (source / drain region, which is an N-channel type TFT in this case, and thus exhibits an N-type conductivity type, and the outer peripheral portion is a P-type impurity region. Boron was added at a concentration of 1 × 10 ^{15 to} 3 × 10 ¹⁸ cm ⁻³ . On the other hand, in a P-channel TFT, a P-type source and drain are formed, and an N-type impurity is added to the region. A gate insulating film 15 is provided below the gate electrode 17 and divided into the substantially intrinsic channel forming region 12 and covers this semiconductor region. Impurity region 1
3, a contact hole is opened through an interlayer insulator 19 and an electrode / wiring 18 is provided.

The difference from the conventional TFT shown in FIG. 5 is that
By providing the region 14 having a conductivity type opposite to the conductivity type of the impurity region (source / drain region) 13 at least at the peripheral portion of the island-shaped semiconductor region 10 below the gate electrode, that is, at the outer end portion of the region. is there. For example, if the impurity region is N-type, an impurity exhibiting a P-type conductivity type is introduced into the region 14, and if the impurity region is a P-type impurity, an impurity exhibiting an N-type conductivity type is introduced into the region 14. To do. In particular, the impurity concentration of the region 14 is sufficiently doped so that it is not inverted by the voltage applied to the gate electrode (specifically, 1 × 10 ^{15 to} 3 × 10 5).
¹⁸ cm ⁻³ , preferably 1 × 10 ¹⁶ to 1 × 10 ¹⁷ c
m ^-3 ) is desired. This impurity concentration is 1 × 10 ¹⁹ cm
^{At -3} or higher, the breakdown voltage with the drain becomes weak and avalanche hot carriers are generated. In addition, except for the portion below the gate electrode, the conductivity type of the region 14 may be inverted when the impurity region 13 is doped, but there is practically no problem.

The effect of the region 14 will be described by focusing on the region 16 of the AA 'cross section. As in the case of the conventional TFT, the coverage of the gate insulating film at the end of such a semiconductor region is not good. Therefore, in this portion, the gate insulating film is destroyed, pinholes are generated, and charges are trapped. Consider the case where a pinhole occurs. Conventionally, the region 16 of the channel forming region 12 has been changed to the same conductivity type as the impurity region 13 by the voltage applied to the gate electrode, but in the present invention, this region 14 is Since it is doped to have a conductivity type opposite to that of the impurity region, the conductivity type does not reverse even if a voltage is applied to the gate electrode, or at least good conductivity is not exhibited.

Therefore, the leak current between the gate electrode and the drain region can be remarkably reduced. Further, even when undesired charges are trapped due to the breakdown of the gate insulating film, the conductivity type of the semiconductor region in the region 16 is not the same as that of the impurity region, so that conduction between the source region and the drain region can be prevented. . If there is no problem in characteristics and reliability even if the gate insulating film is destroyed in this way, the voltage limit during use will be less, and the probability of occurrence of defective products due to electrostatic breakdown during manufacturing. Also decreases and the yield improves.

Although FIG. 1 shows a state in which a region 14 having a conductivity type opposite to that of the impurity region 13 is provided at all the ends of the thin film semiconductor region on the side crossing the gate electrode, at least such a region is provided. It will be apparent from the above description that it is sufficient to provide it in the region below the electrodes. When carbon, nitrogen, oxygen, or the like is added to the region 14 in addition to the P-type (or N-type) impurities, the resistance of the region 14 increases, so that the breakdown voltage is further improved and the TFT having high reliability is obtained. was gotten. Hereinafter, the present invention will be described with reference to examples.

[0013]

【Example】

Example 1 FIG. 2 shows a cross-sectional view of a manufacturing process of this example. In the drawings of the following embodiments including this embodiment, TF
Only the cross-sectional view of T is shown, and in each case, a TFT having a surface perpendicular to the gate electrode (corresponding to the cross section BB ′ in FIGS. 1 and 5) is formed on the left side, and the TFT is parallel to the gate electrode on the right side An example of forming a TFT having a flat surface (corresponding to the cross section AA ′ in FIGS. 1 and 5) is shown.

First, a base film 21 of silicon oxide or silicon nitride having a thickness of 2000 liters or a multilayer film thereof was formed on a substrate (Corning 7059) 20 by a plasma CVD method or a sputtering method. Further, by the plasma CVD method, the thickness is 300 to 1500Å, for example, 1
A 000Å amorphous silicon film was deposited. Subsequently, a 200 Å-thick silicon oxide film was deposited as a protective film by a sputtering method. Then, this was annealed at 600 ° C. for 48 hours in a reducing atmosphere to be crystallized.
The crystallization step may be a method using strong light such as a laser.
Then, by patterning the obtained crystalline silicon film,
The island-shaped silicon regions 22a and 22b are formed. Protective films 23a and 23b are respectively placed on the island-shaped silicon film. This protective film has a function of preventing the island-shaped silicon region from being contaminated in the subsequent photolithography process.

Next, a photoresist is applied on the entire surface and the resist 24 is formed by a known photolithography method.
Patterning is carried out leaving a and 24b, and the width is 0.05.
The width is -5 μm, preferably 0.1-1 μm.
Then, using this resist as a mask, 1 × 10 1 of boron is used.
^{15 to} 3 × 10 ¹⁸ cm ⁻³ , preferably 1 × 10 ¹⁶ to 1 × 1
It was introduced at a concentration of 0 ¹⁷ cm ^-3 . A plasma doping method was used to introduce boron. Diborane (B ₂ H ₆ ) is used as a doping gas, plasma is generated by discharging at an rf power of 10 to 30 W, for example, 10 W, and is accelerated at an accelerating voltage of 20 to 60 kV, for example, 20 kV, and then introduced into a silicon region. did. The dose amount is 1 × 10 ^{13 to} 5 ×
10 ¹⁵ cm ^-2 , for example, 3 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ^-2
And As a result, the P-type regions 25a, 25b, 25
c, 25d were formed. (Fig. 2 (A))

Next, the sputtering method or plasma C
According to the VD method, the thickness is 500 to 1500Å, for example, 100
A 0Å silicon oxide film 26 is deposited as a gate insulating film, and subsequently, a thickness of 6000 to 80 is formed by a low pressure CVD method.
00Å, for example 6000Å silicon film (0.1-2%
Containing phosphorus). It is desirable that the steps of forming the silicon oxide and the silicon film are continuously performed. Then, the silicon film is patterned to form the wirings 27a, 2
7b was formed. Each of these wirings functions as a gate electrode. (Fig. 2 (B))

Next, impurities (phosphorus) were implanted into the silicon region by plasma doping using the wiring 27a as a mask. As doping gas, phosphine (PH
₃ ) is used and the acceleration voltage is 60 to 90 kV, for example 80 kV.
It was set to V. The dose is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 ,
For example, 5 × 10 ^{15 which} is larger than the previous dose of boron.
It was cm ^-2 . Then, in a reducing atmosphere, at 48 ° C at 48
The impurities were activated by annealing for a period of time. Thus, the impurity regions 28a and 28b were formed. In this case, of the boron regions previously formed,
The regions 25c and 25d where phosphorus is not introduced afterwards show P-type, while the regions 25a and 25b where phosphorus is introduced become N-type due to a large amount of phosphorus doping. There is no problem from. (Fig. 2 (C))

Subsequently, a silicon oxide film having a thickness of 3000 Å is formed as an interlayer insulating film by a plasma CVD method, a contact hole is formed in this film, and a wiring 29a is formed by a metal material, for example, a multilayer film of titanium nitride and aluminum.
29b was formed. The wiring 29a connects the wiring 27b and one of the impurity regions 28b of the TFT. The semiconductor circuit is completed through the above steps. (Fig. 2 (D))

[Embodiment 2] FIG. 3 is a sectional view of a manufacturing process of this embodiment. A base film 302 of silicon oxide having a thickness of 2000 Å was formed on the insulating surface of the substrate (Corning 7059) 301 by sputtering. Further, the thickness is 500 to 1500Å, for example, 1 by plasma CVD method.
A 000Å amorphous silicon film was deposited. Subsequently, a 200 Å-thick silicon oxide film was deposited as a protective film by a sputtering method. Then, this was annealed at 600 ° C. for 48 hours in a reducing atmosphere to be crystallized.
The crystallization step may be a method using strong light such as a laser.
Then, the obtained crystalline silicon film was patterned by a known photolithography method to form island-shaped silicon regions 303a and 303b. A protective film is left on the island-shaped silicon film. Further, the photoresist masks 304a and 304b used for etching are also left. In this etching process, an isotropic etching method (for example, wet etching using buffered hydrofluoric acid) was used, and the side end portions of the semiconductor region were tapered as shown in the figure. This angle is 30 to 6 for the substrate surface.
The angle was 0 °. In this drawing, the semiconductor region 303a is a TFT, and the semiconductor region 303b is a capacitor which is another circuit.

Next, boron was introduced using this resist as a mask. A plasma doping method was used to introduce boron. Diborane (B ₂ H ₆ ) as doping gas
Was used for accelerating at an accelerating voltage of 20 to 60 kV, for example, 20 kV, and was introduced into the silicon region. Dose amount is 1 × 1
It was set to 0 ^{13 to} 5 × 10 ¹⁴ cm ⁻² , for example, 1 × 10 ¹⁴ cm ⁻² . As a result, the P-type regions 305a, 305b, 30
5c and 305d were formed. (Fig. 3 (A))

Next, a thickness of 10 is obtained by the sputtering method.
A silicon oxide film 306 of 00Å is deposited as a gate insulating film, and subsequently, a thickness of 4000 to
8000Å, for example, 6000Å aluminum film (0.
2% by weight scandium) was deposited. In addition, it is desirable that the steps of forming the silicon oxide film and the aluminum film are continuously performed. Then, the aluminum film was patterned to form wirings 307a and 307b. Each of these wirings functions as a gate electrode. Further, the surface of this aluminum wiring was anodized to form oxide layers 309a and 309b on the surface. Before the anodization, a mask 308 was selectively formed by using a photosensitive polyimide (photonice) at a portion where a contact was to be formed later. During anodic oxidation, no anodic oxide was formed in this part due to this mask.

The anodic oxidation was performed in a 1-5% ethylene glycol solution of tartaric acid. The thickness of the obtained oxide layer was 2000Å. Next, the wiring 307a and the oxide 30 are formed in the silicon region by plasma doping.
Impurities (phosphorus) were implanted using 9a as a mask. Phosphine (PH ₃ ) was used as a doping gas, and the acceleration voltage was set to 60 to 90 kV, for example, 80 kV. The dose amount was set to 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 5 × 10 ¹⁵ cm ^−2, which is larger than the previous dose amount of boron. Thus, the N type impurity regions 310a and 310b were formed. At this time, as in the case of Example 1, the boron-doped regions 305a and 305b formed previously are formed.
Has been converted to N type. (Fig. 3 (B))

After that, the impurities were activated by the laser annealing method. As a laser, a KrF excimer laser (wavelength 248 nm, pulse width 20 nse
Although c) is used, other lasers such as XeF excimer laser (wavelength 353 nm), XeCl excimer laser (wavelength 308 nm), ArF excimer laser (wavelength 193 nm) and the like may be used. The energy density of the laser was 200 to 350 mJ / cm ² , for example, 250 mJ / cm ^2, and the irradiation was performed for 2 to 10 shots, for example, 2 shots per location. The substrate may be heated to about 200 to 450 ° C. during laser irradiation. It should be noted that the optimum laser energy density changes when the substrate is heated. Note that the polyimide mask 308 was left at the time of laser irradiation.
This is because the exposed aluminum is damaged by laser irradiation. After laser irradiation, this polyimide mask can be easily removed by exposure to oxygen plasma.

In the present embodiment, unlike the case of the first embodiment, the region 305 under the gate electrode, in which boron is implanted, is formed.
Since c and 305d do not receive the laser light, the activation rate is low, but since the crystallinity is destroyed during the ion implantation, it functions as an extremely large resistance and is effective for the purpose of reducing the leak current. It was (FIG. 3 (C)) On the other hand, on the other hand, an island region having a tapered side end in FIG. 3 (A) was formed, and thereafter, boroso was ion-implanted. Furthermore, the laser light is 50 to 350 mJ / c.
Irradiation was carried out at m ² to crystallize all of the island regions. Then, the side single part is made P-type, and the inside is made to have an I-type intrinsic or substantially intrinsic conductivity type, and further, as described above, the gate insulating film, the gate electrode, and the source / drain may be formed. By doing so, the end portion of the island-shaped region under the gate electrode can also be a fully crystallized P or P ⁻ -type region, and leakage between the N-type source / drain can be prevented.

Then, a silicon oxide film 31 having a thickness of 3000 Å is formed.
1 was formed as an interlayer insulator by a plasma CVD method, a contact hole was formed in this, and wirings 312a and 312b were formed by a metal material, for example, a multilayer film of titanium nitride and aluminum. The wiring 312a is the wiring 3
07b is connected to one of the impurity regions 310b of the TFT. Through the above steps, the TFTs 313a (cross section perpendicular to the gate electrode in the figure) and 313b (cross section parallel to the gate electrode in the figure) are completed. (FIG. 3 (D)) In this embodiment, it is apparent that a capacitor is formed between the gate electrode and the remaining impurity region unless either the source electrode or the drain electrode of the TFT is provided. Therefore, even if the same means as this embodiment is used, it is possible to obtain a capacitor having excellent characteristics such as a high breakdown voltage and a small leak, and reliability. Then, a pixel circuit of an active matrix type liquid crystal display may be configured using the TFT and the capacitor thus formed. With the TFT of the present invention, the off current can be set to 1 pA or less, and a sufficient function can be provided.

[Embodiment 3] FIG. 4 is a cross-sectional view of a manufacturing process of this embodiment. An underlayer film 41 of silicon oxide having a thickness of 2000 Å was formed on a substrate (Corning 7059) 40 by sputtering. Further, an amorphous silicon film having a thickness of 500 to 1500 Å, for example 1500 Å, was deposited by the plasma CVD method. Then, the obtained amorphous silicon film was patterned to form island-shaped silicon regions 42a and 42b.

Next, a photoresist is applied on the entire surface, and the resist 43 is formed by a known photolithography method.
Patterning was carried out leaving a and 43b. Then, boron was introduced using this resist as a mask. A plasma doping method was used to introduce boron. As a result, P-type regions 44a, 44b, 44c and 44d were formed. (Fig. 4 (A))

Next, with the photoresist remaining, a silicon oxide film 45a having a thickness of 1000 Å was deposited by the sputtering method. (FIG. 4B) Then, the photoresist was peeled off to remove the silicon oxide film formed thereon. The silicon oxide film remains as it is in the portion where the photoresist was not present. This was crystallized by annealing at 600 ° C. for 48 hours in a reducing atmosphere. The crystallization step may be a method using strong light such as a laser.

Next, a thickness of 10 is obtained by the sputtering method.
A silicon oxide film 45b of 00Å is deposited as a gate insulating film, and subsequently, a thickness of 6000 is obtained by a low pressure CVD method.
~ 8000Å, eg 6000Å silicon film (0.1
˜2% phosphorus) was deposited. It is desirable that the steps of forming the silicon oxide and the silicon film are continuously performed. Then, the silicon film is patterned to form the wiring 46.
a and 46b were formed. Each of these wirings functions as a gate electrode. Also, paying attention to the peripheral portion of the silicon-on-island region (the region where boron was previously implanted), the thickness of the insulating film is approximately doubled here by the silicon oxides 45a and 45b. Therefore, it is effective for preventing the breakdown of the gate insulating film. (Fig. 4 (C))

Next, impurities (phosphorus) were implanted into the silicon region by plasma doping using the wiring 46a as a mask. As doping gas, phosphine (PH
₃ ) was used. Then, in a reducing atmosphere, at 48 ° C at 48
The impurities were activated by annealing for a period of time. Thus, the impurity regions 47a and 47b were formed. Then, a silicon oxide film 48 having a thickness of 3000 Å is formed as an interlayer insulator by a plasma CVD method, a contact hole is formed in the film, and wirings 49a and 49 are made of a metal material, for example, a multilayer film of titanium nitride and aluminum.
b was formed. The wiring 49a connects the wiring 46b and one of the impurity regions 47b of the TFT. The semiconductor circuit is completed through the above steps. (FIG. 4 (D)) The present embodiment improved the yield more than double that of the conventional one. Further, the deterioration of the TFT characteristics was not particularly recognized. On the contrary, since the maximum voltage that can be used has increased 1.5 to 2 times that of the conventional one, the maximum operating speed has increased 2 to 4 times.

[Embodiment 4] FIG. 6 shows the present embodiment. First, a base film 61 of silicon oxide having a thickness of 1000 to 3000 Å was formed on a substrate 60. Furthermore, an amorphous silicon film is formed by plasma CVD or LPCVD.
~ 5000Å, preferably 300-1000Å. A silicon oxide film was deposited on the amorphous silicon film as a protective film in an amount of 100 to 500 liters. Then, the resist mask 63 is formed by a known photolithography method.
A and 63b were formed, and the amorphous silicon was etched by the dry etching method. The etching conditions at this time were as follows. RF power: 500 W Pressure: 100 mTorr Gas flow rate CF ₄ : 50 sccm O ₂ ; 45 sccm

As a result, as shown in FIG. 6A, island-shaped silicon regions 62a and 62b were obtained, but the edge portions thereof were tapered as shown in the figure. The angle of this taper was 20 to 60 °. In etching, if the ratio CF ₄ / O ₂ becomes large, such a tapered edge could not be obtained. Next, boron was introduced using this resist as a mask. A plasma doping method was used to introduce nitrogen. Diborane (B ₂ H ₆ ) was used as the doping gas, and the acceleration voltage was 20 to ₆
It was accelerated at 0 kV, for example 20 kV, and introduced into the silicon region. The dose amount is 1 × 10 ^{14 to} 5 × 10 ¹⁶ cm ^-2 ,
For example, it is set to 1 × 10 ¹⁵ cm ⁻² . As a result, boron was selectively doped into the edge portions 64a, 64b, 64c, and 64d in the silicon region which had no resist or was thin. (FIG. 6A) Further, nitrogen was continuously doped by the plasma doping method. Nitrogen (N ₂ ) is used as the doping gas, and the acceleration voltage is 20 to 60 kV, for example, 20.
It was accelerated in kV and introduced into the silicon region. The dose amount is 1 × 10 ^{14 to} 5 × 10 ¹⁶ cm ^-2 , for example, 1 × 10
^{It was 14} cm ^-2 . As a result, the edge portion 6 of the silicon region is
4a, 64b, 64c and 64d were doped with nitrogen.

After that, a photoresist mask material 63
The amorphous silicon was crystallized by irradiating a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) with the island-shaped silicon film exposed by removing the protective films a and 63b. . As the laser, XeCl excimer laser (wavelength 30
8 nm, pulse width 50 nsec) may be used.
Then, a silicon oxide film 65 having a thickness of 1000 to 1500Å is formed by a sputtering method or a plasma CVD method, and subsequently, aluminum having a thickness of 1000Å to 3 μm (1 wt% Si or 0.1 to 0.3 wt% S is formed).
A film containing c (scandium) was formed by an electron beam evaporation method or a sputtering method.

Then, a photoresist was applied on the surface by a known spin coating method, and patterning was performed by a known photolithography method. Then, the aluminum film was etched with phosphoric acid. In this way, the gate electrodes / wirings 66a, 6a
6b was formed. The photoresist masks 67a and 67b were left on the gate electrode / wiring. Also, due to overetching,
The side surface of the wiring is inside the side surface of the photoresist.
(Fig. 6 (B))

In this state, impurities (phosphorus) were implanted into the active semiconductor layers 62a and 62b of the TFT by the plasma doping method using the photoresists 67a and 67b as masks to form N-type sources 68a and drains 68b. Here, since the gate electrode 66a is located inside the photoresist 67a by the distance x, the gate electrode and the source / drain are in an offset state as shown in the figure. The distance x can be increased or decreased by adjusting the etching time for aluminum wiring. As x, 0.3 to 5 μm was preferable. (Fig. 6 (C))

Then, the photoresists 67a and 67b are peeled off, and a KrF excimer laser (wavelength 248 nm,
A pulse width of 20 nsec) was applied to activate the impurity ions introduced into the active layer. (Fig. 6
(D)) Finally, plasma CVD is performed on the entire surface as an interlayer insulator 69.
A silicon oxide film having a thickness of 2000 Å to 1 μm was formed by the method. Further, contact holes are formed in the source 68a and the drain 68b of the TFT, and the aluminum wiring 70a,
70b was formed to a thickness of 2000Å to 1 μm, for example 5000Å. If, for example, titanium nitride is formed under the aluminum wiring as a barrier metal, the reliability can be further improved (FIG. 6 (E)).

[0037]

According to the present invention, it is possible to improve the yield of thin film semiconductor devices, enhance their reliability, and maximize the characteristics. The thin film semiconductor device of the present invention is particularly preferable as a transistor for controlling pixels in an active matrix circuit of a liquid crystal display because it has a low leak current between the gate and the drain and between the gate and the source and can withstand a high gate voltage. .

Although the present invention has been described by taking the N-channel type TFT as an example, the P-channel type TFT or the N-channel type TFT on the same substrate.
It goes without saying that the same can be applied to the case of the phase trapping type circuit in which the channel type and the P channel type are mixed. Also, not only the simple structure shown in the embodiment,
For example, a TFT having a structure having silicide in the source / drain as shown in Japanese Patent Application No. 5-256567.
May be used for. Further, this embodiment mainly shows the TFT. However, other circuit elements, such as a thin film integrated circuit having a plurality of gate electrodes in one island region, a stacked gate type TFT, a diode, a resistor, a capacitor,
Needless to say, it can be applied to a thin film semiconductor circuit in which this is integrated. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

FIG. 1 shows a configuration example of a thin film semiconductor device (TFT) of the present invention.

2A to 2C show cross-sectional views of a manufacturing process of the TFT of Example 1.

3A to 3C show cross-sectional views of a manufacturing process of a TFT of Example 2.

4A to 4C show cross-sectional views of a manufacturing process of a TFT of Example 3.

FIG. 5 shows a configuration example of a conventional thin film semiconductor device (TFT).

6A to 6C show cross-sectional views of a manufacturing process of a TFT of Example 4.

[Explanation of symbols]

10 ... Island semiconductor region 11 ... Substrate 12 ... Channel formation region (substantially intrinsic) 13 ... Impurity region (source, drain) 14 ... Doping region (opposite impurity region) Conductive impurities are included) 15 ... Gate insulating film 16 ... Island semiconductor region end 17 ... Gate electrode 18 ... Source / drain electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location 8617-4M H01L 21/265 S 9056-4M 29/78 311 S

Claims (9)

[Claims] 1. A thin film semiconductor device having an island-shaped thin film semiconductor region formed on a substrate having an insulating surface, and a gate electrode traversing the semiconductor region, wherein: The thin-film semiconductor device is characterized in that the conductivity type of the portion below the gate electrode is opposite to the conductivity type of the source and drain regions of the semiconductor region. 2. The thin film semiconductor device according to claim 1, wherein the island-shaped thin film semiconductor region has a tapered edge. 3. The width of the region having a conductivity type opposite to that of the source and drain regions is 0.05 to 5.
The thin film semiconductor device has a thickness of 5 μm, preferably 0.1 to 1 μm. 4. The island-shaped semiconductor thin film according to claim 1, wherein at least one element of oxygen, carbon, and nitrogen is present in a portion substantially the same as a portion showing a conductivity type opposite to that of the source / drain region. A thin-film semiconductor device having: 5. A step of forming an island-shaped thin film semiconductor region, and an impurity having a conductivity type opposite to those of the source and drain regions is selected in at least a portion of the peripheral portion of the thin film semiconductor region where the gate electrode crosses. Step, a step of forming a gate electrode across the thin film semiconductor region, and a step of forming impurities into the thin film semiconductor region in a self-aligned manner using the gate electrode as a mask to form source and drain regions. A method of manufacturing a thin film semiconductor device, comprising: 6. A step of forming an island-shaped thin film semiconductor region using a semiconductor material in a substantially amorphous state, and an impurity having a conductivity type opposite to that of a source / drain region in a peripheral portion of the thin film semiconductor region. A thin film comprising: a step of introducing, a step of irradiating the thin film semiconductor region with a laser or strong light equivalent thereto to crystallize, and a step of forming a gate electrode across the thin film semiconductor region. Manufacturing method of semiconductor device. 7. A step of directly or indirectly forming a mask material on a non-single-crystal semiconductor thin film and performing island-shaped patterning by a photolithography method, and a step of forming the mask material by a dry etching method or a wet etching method. Etching the semiconductor thin film into islands according to a pattern, and accelerating and irradiating ions of N-type or P-type impurities with the mask material left on the island-shaped semiconductor thin film. A step of forming a gate electrode across the semiconductor thin film, the method for manufacturing a thin film semiconductor device. 8. The method for manufacturing a thin film semiconductor device according to claim 7, wherein the island-shaped semiconductor thin film has a tapered edge. 9. The irradiation of N-type or P-type impurity ions to an island-shaped semiconductor thin film is performed before or after the step of accelerating and irradiating ions of N-type or P-type impurities according to claim 8. And a step of introducing at least one element of oxygen, carbon, and nitrogen into a region substantially the same as the above region.