JPH07176753A - Thin-film semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To increase the resistance between a semiconductor region and a source-drain and to enhance the breakdown strength of this part by a method wherein an element which is different from that of a main component for the semiconductor region is introduced into a tapered edge in the semiconductor region. CONSTITUTION:A TFT is formed on a substrate 11. A thin-film semiconductor region is situated under an impurity region 13 and a gate electrode 17. It is divided substantially into intrinsic channel formation regions 12. A gate insulating film 15 is formed so as to cover the semiconductor region. In the impurity region, a contact hole is opened through a layer insulator 19, and electrode interconnections 18 are formed. An insular semiconductor region 10 is provided with a tapered edge, and a high-resistance region 14 is formed near the tapered edge. Since the edge is tapered, the coverage of the gate insulating film 15 is enhanced, its film thickness becomes uniform, and a locally thin region is not formed. Thereby, the breakdown strength of this part is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and manufacturing method of a circuit element used in a thin film integrated circuit, for example, a thin film transistor (TFT). The thin film transistor manufactured by the present invention is on an insulating substrate such as glass,
It is formed on any insulator formed on a semiconductor substrate such as single crystal silicon.

[0002]

2. Description of the Related Art Conventionally, in a thin film transistor, a formed non-single-crystal semiconductor film is patterned into an island shape to form an island-shaped semiconductor region (active layer), and then a gate insulating film is formed by a CVD method or a sputtering method. An insulating film was formed, and a gate electrode was formed on it.

[0003]

The insulating coating formed by the CVD method or the sputtering method has a poor step coverage (step coverage), which adversely affects reliability, yield, and characteristics. FIG. 2 is a view of a typical conventional TFT seen from above,
And a cross-sectional view taken along line AA ′ and BB ′ of the drawing. The TFT is formed on the substrate 21, the thin film semiconductor region is located below the impurity region (source / drain region, which shows N-type conductivity here) 23 and the gate electrode 27, and is a substantially intrinsic channel forming region. A gate insulating film 25 is provided so as to cover the semiconductor region. In the impurity region 23, a contact hole is opened through an interlayer insulator 29, and an electrode / wiring 28 is provided.

As can be seen from the figure, the coverage of the end portion of the semiconductor region of the gate insulating film 25 is extremely poor, and typically only half the thickness of the flat portion is present. Generally, when the island-shaped semiconductor region is thick, it is extremely large. Particularly, from the AA 'cross section along the gate electrode, it can be seen that such deterioration of the covering property adversely affects the characteristics, reliability and yield of the TFT. That is, paying attention to the region 26 indicated by a dotted circle in the AA ′ sectional view of FIG. 2, the electric field of the gate electrode 27 is intensively applied to the end portion of the thin film semiconductor region. That is, since the thickness of the gate insulating film in this portion is half that of the flat portion, the electric field strength thereof is doubled.

As a result, the gate insulating film in this region 26 is easily destroyed by applying a high voltage for a long time. If the signal applied to the gate electrode is positive, the semiconductor in this region 26 is also N-type, so that the gate electrode 27 and the impurity region 28 (particularly, the drain region) become conductive, which causes deterioration of reliability. Becomes Further, when a voltage opposite to the normal voltage (a positive voltage to the drain and a negative voltage to the gate in the N-channel transistor) is applied to the gate electrode, the current (off current) flowing between the source and the drain increases. Oops. Typically, this off-current cannot be reduced, preferably below 1 × 10 ⁻¹² A.

When the gate insulating film is destroyed,
It happens that some charge is trapped, for example
If the negative charges are trapped, the semiconductor in the region 26 exhibits an N type and a path (passage) of the same conductivity type as the source / drain is formed, regardless of the voltage applied to the gate electrode. Therefore, the two impurity regions 28 become electrically conductive in the peripheral portion on the side of the island-shaped semiconductor region, which deteriorates the characteristics. Further, in order to use the TFT without causing the above deterioration, only half the voltage can be applied, and the performance cannot be fully utilized.

The presence of such a weak portion in a part of the TFT means that the TFT is easily destroyed due to charging or the like in the manufacturing process, which is a major factor for lowering the yield. An object of the present invention is to solve such a problem.

[0008]

According to the present invention, the electrically weak edge portion is processed into a taper shape to improve the coverage, and the edge portion is made of an element different from the main component of the semiconductor region. Is introduced or high-speed ions are implanted to increase the resistance between the region and the source / drain, thereby improving the breakdown voltage of this portion. A typical structure of the present invention is shown in FIG. Similar to FIG. 2, FIG. 1 also shows a drawing of the TFT viewed from above and cross-sectional views of AA ′ and BB ′ cross sections thereof. The TFT is formed on the substrate 11, and the thin film semiconductor region is an impurity region (source and drain regions, which are N-type conductivity type here, but may be P-type) 1.
3 and the gate electrode 17 and is divided into a substantially intrinsic channel forming region 12, and a gate insulating film 15 is provided so as to cover this semiconductor region. A contact hole is formed in the impurity region 13 through an interlayer insulator 19, and an electrode / wiring 18 is provided.

The difference from the conventional TFT shown in FIG. 2 is that
The island-shaped semiconductor region 10 has a tapered edge, and the region 14 having a high resistance is provided in the vicinity of the tapered edge. Since the edge has a tapered shape, the coverage of the gate insulating film 15 is improved, the film thickness becomes uniform, and locally thin regions are eliminated. The following three types of methods can be considered as the method of forming this region 14.

The first is a small amount selected from oxygen, carbon and nitrogen.
By adding at least one element, carbon, oxygen,
Any one or more elements of nitrogen are island-shaped
By increasing the average concentration of the semiconductor region,
In that part, the chemical formula Si_xC _1-x(0 <x <1), Si
O_2-x(0 <x <2), Si₃N_4-x(0 <x <4)
Rui, SiC_yN_zO_zSemi-insulating or insulation indicated by
This is a method of forming the limbic region. For example, semiconductor area
The average nitrogen concentration in the area is 1 x 10¹⁸cm^-3If,
The concentration of nitrogen in this part is 1 × 10¹⁹cm^-3That's all
Kuha 1 × 10²⁰cm^-3Nitrogen is introduced to reach the above concentration.
Put it in and let it react with the silicon of the semiconductor, Si₃N
_4-x(0 <x <4) is formed. As a result, the area 14
The resistance rises significantly. The same applies when oxygen or carbon is used
So 1 x 10¹⁹cm^-3Or more, preferably 1 × 10²⁰cm
^-3Introducing oxygen and carbon to the above concentration
Therefore, the high resistance region 14 could be formed.

Thus, the other channel forming region 1
Since the energy band width is larger than that of 2,
When a high voltage is applied to the gate electrode, the electric field strength between the side edge portion and the channel is intentionally made weaker than that in the channel formation region, so that electrical breakdown and leakage can be suppressed.

Second, impurity regions (source, drain)
A semiconductor impurity having a conductivity type opposite to that of 13 is added. As a result, even if the source and drain are formed thereafter, at least the region below the gate electrode in the region 14 is the impurity region (source and drain region) 13
The conductivity type is opposite to that of. For example, if the impurity region is N-type, an impurity exhibiting a P-type conductivity type is introduced into the region 14, and if the impurity region is P-type, the region 14 is N-type.
An impurity exhibiting the conductivity type of the type is introduced. In particular, the impurity concentration of the region 14 is sufficient below the gate electrode so as not to be inverted by the voltage applied to the gate electrode (specifically, 1 × 10 ^{15 to} 3 × 10 ¹⁸ cm ⁻³ , preferably 1 ×). 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ ) is desired. When the impurity concentration is 1 × 10 ¹⁹ cm ⁻³ or higher, the breakdown voltage with the drain becomes weak and avalanche hot carriers are generated. In addition, except for the portion below the gate electrode, the conductivity type of the region 14 may be inverted when the impurity region 13 is doped, but there is practically no problem.

The third method is to implant high-speed ions. Ions to be implanted include silicon, carbon, oxygen,
Examples include nitrogen, phosphorus, and boron. For example, 1 × 10 ¹³ to 1 × 10 ¹⁶ cm ^{-2 of} silicon ions are added to an island-shaped semiconductor region crystallized by a solid-phase growth method by long-time thermal annealing, or irradiation of a laser or strong light equivalent thereto.
By implanting with a dose of preferably 1 × 10 ^{14 to} 5 × 10 ¹⁵ cm ^{−2 and} with an accelerating energy of 30 to 100 KeV, the crystallinity of that portion is lowered and a sufficiently high resistance can be realized. As a matter of course, since the optimum values of the dose amount and the acceleration energy depend on the thickness of the island-shaped semiconductor film,
It is not necessarily required to fall within the above range.

In the region 14 thus formed, even if the gate insulating film is destroyed at the end portion 16 of the semiconductor region and a pinhole is generated, the region 14 has a conductivity opposite to that of the source and drain. Since the type is high and the resistance is high, the leak current between the gate electrode and the drain region can be remarkably reduced. Further, even when undesired charges are trapped by the breakdown of the gate insulating film, the conductivity type of the semiconductor region in the region 14 is opposite to that of the source and drain, or the resistance is high.
Conduction between the source region and the drain region can be prevented. If there is no problem in characteristics and reliability even if the gate insulating film is destroyed in this way, the voltage limit during use will be less, and the probability of occurrence of defective products due to electrostatic breakdown during manufacturing. Also decreases and the yield improves. Hereinafter, the present invention will be described with reference to examples.

[0015]

[Embodiment] [Embodiment 1] FIG. 3 shows a cross-sectional view of a manufacturing process of this embodiment. In the drawings of the following embodiments including this embodiment, only the cross-sectional view of the TFT is shown, and in each case, a surface perpendicular to the gate electrode (corresponding to the cross section BB ′ in FIGS. 1 and 2) is provided on the left side. An example is shown in which the TFT having the same is formed, and the TFT having the surface parallel to the gate electrode (corresponding to the cross section AA ′ in FIGS. 1 and 2) is formed on the right side.

First, a base film 31 of silicon oxide or silicon nitride having a thickness of 2000 Å or a multilayer film thereof was formed on a substrate (Corning 7059) 30 by a plasma CVD method or a sputtering method. Further, an amorphous silicon film is formed with a plasma CVD method or an LPCVD method in an amount of 100 to 5000 Å, preferably 300 to 1000.
Å Accumulated. A silicon oxide film was deposited on the amorphous silicon film as a protective film in an amount of 100 to 500 liters. And
The resist masks 33a and 33b were formed by a known photolithography method, and the amorphous silicon was etched by a dry etching method.
The etching conditions at this time were as follows. RF power: 500 W Pressure: 100 mTorr Gas flow rate CF ₄ : 50 sccm O ₂ ; 45 sccm

As a result, as shown in FIG. 3A, island-shaped silicon regions 32a and 32b were obtained, but the edge portions thereof were tapered as shown in the figure. The angle of this taper was 20 to 60 °. In etching, if the ratio CF ₄ / O ₂ becomes large, such a tapered edge could not be obtained. Next, using this resist as a mask, boron is added at 1 × 10 ^{15 to} 3 × 10 5.
^It was introduced at a concentration of ¹⁸ cm ^-3 , preferably 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ^-3 . A plasma doping method was used to introduce boron. Diborane (B ₂ H) is used as a doping gas.
₆ ) is used to generate plasma by discharging with rf power of 10 to 30 W, for example, 10 W, and accelerating voltage of 20 to
It was accelerated to 60 kV, for example 20 kV, and introduced into the silicon region. The dose amount is 1 × 10 ^{13 to} 5 × 10 ¹⁵ c
m ⁻² , for example, 3 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² .
As a result, P-type regions 34a, 34b, 34c, 34d
Was formed. (Fig. 3 (A))

After that, a photoresist mask material 63
The amorphous silicon was crystallized by irradiating a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) with the islands of silicon film exposed by removing the protective films a and 63b. . As the laser, XeCl excimer laser (wavelength 30
8 nm, pulse width 50 nsec) may be used.
The planes of the island-shaped silicon regions 32a and 32b thus obtained which are parallel to the substrate are the (110) planes,
It was revealed from the X-ray diffraction method that it consisted of the (111) plane and the (311) plane.

Next, a sputtering method or plasma C
According to the VD method, the thickness is 500 to 1500Å, for example, 100
A 0Å silicon oxide film 35 is deposited as a gate insulating film, and subsequently a thickness of 6000 to 80 is formed by a low pressure CVD method.
00Å, for example 6000Å silicon film (0.1-2%
Containing phosphorus). It is desirable that the steps of forming the silicon oxide and the silicon film are continuously performed. Then, the silicon film is patterned to form the wirings 36a, 3
6b was formed. Each of these wirings functions as a gate electrode. (Fig. 3 (B))

Next, impurities (phosphorus) were implanted into the silicon region by plasma doping using the wiring 36a as a mask. As doping gas, phosphine (PH
₃ ) is used and the acceleration voltage is 60 to 90 kV, for example 80 kV.
It was set to V. The dose is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 ,
For example, 5 × 10 ^{15 which} is larger than the previous dose of boron.
It was cm ^-2 . (FIG. 3C) After that, in a reducing atmosphere,
The impurities were activated by annealing at 550 to 600 ° C. for 48 hours. Thus, the impurity regions 37a and 37b were formed. In this case, among the boron regions previously formed, the regions 34c and 34d in which phosphorus is not introduced afterwards show P-type, while the regions 34a and 34b in which phosphorus is introduced contain a large amount of phosphorus. Although it is N-type by doping, there is no problem from the technical idea of the present invention. (Fig. 3 (D))

Then, a silicon oxide film 38 having a thickness of 3000 Å is formed.
Is formed by plasma CVD as an interlayer insulator,
A contact hole is formed in this, and the wiring 3 is made of a metal material, for example, a multilayer film of titanium nitride and aluminum.
9a and 39b were formed. The semiconductor circuit is completed through the above steps. (Fig. 3 (E))

[Embodiment 2] FIG. 4 shows a cross-sectional view of a manufacturing process of this embodiment. First, the substrate (Corning 7059) 4
An underlayer film 41 of silicon oxide having a thickness of 2000 Å was formed on the substrate 0 by sputtering. Further, by the plasma CVD method, the thickness is 500 to 1500Å, for example 1500Å
Deposited an amorphous silicon film. The nitrogen concentration in the amorphous silicon film is determined by secondary ion mass spectrometry (SI
It was 1 × 10 ¹⁸ cm ⁻³ or less as measured by the MS method. Continuously, a thickness of 200 is obtained by the sputtering method.
A Å silicon oxide film was deposited as a protective film. Then, this was annealed at 600 ° C. for 48 hours in a reducing atmosphere to be crystallized. According to the X-ray diffraction method, the (111) plane appeared most strongly in the silicon film thus obtained. The crystallization step may be a method using strong light such as a laser. Then, the crystalline silicon film was patterned to form island-shaped silicon semiconductor regions 42a and 42b. A protective film is left on the island-shaped silicon film. This protective film has a function of preventing the island-shaped silicon region from being contaminated in the subsequent photolithography process.

Next, a photoresist is applied on the entire surface, resist masks 43a and 43b are formed by a known photolithography method, and amorphous silicon is etched by a dry etching method.
The etching conditions at this time were as follows. RF power: 500 W Pressure: 100 mTorr Gas flow rate CF ₄ : 50 sccm O ₂ ; 45 sccm

As a result, as shown in FIG. 4 (A), island-shaped silicon regions 42a and 42b were obtained, but the edge portions thereof were tapered as shown in the figure. The angle of this taper was 20 to 60 ° with respect to the substrate surface. In etching, if the ratio CF ₄ / O ₂ increases,
It was not possible to obtain such a tapered edge. Then, using this resist as a mask, nitrogen, carbon,
Oxygen, here nitrogen, was selectively introduced at the edge of the island-shaped semiconductor region. A plasma doping method was used to introduce nitrogen. Nitrogen gas is used as a doping gas, and plasma is generated by discharging with rf power of 10 to 30 W, for example, 10 W, and accelerating voltage of 20 to 60 kV, for example, 2
It was accelerated at 0 kV and introduced into the silicon region. The dose amount is 1 × 10 ^{15 to} 5 × 10 ¹⁶ cm ⁻² , for example, 1 × 10
¹⁶ cm ^-2 . As a result, the nitrogen-doped region 4
4a, 44b, 44c and 44d were formed. Under this condition, the concentration of nitrogen in the nitrogen-doped region is 1 × 1.
It was 0 ^{20 to} 2 × 10 ²² cm ⁻³ , for example, about 1 × 10 ²¹ cm ^−3, and a remarkably large amount of nitrogen was introduced compared to other semiconductor regions. (Fig. 4 (A))

Next, the masks 43a and 43b are removed, the protective film of silicon oxide thereunder is also removed, and the surfaces of the semiconductor regions 42a and 42b are exposed. The film 45 is deposited as a gate insulating film, and then the thickness is 1000Å to 3μ.
m aluminum (1 wt% Si, or 0.1
A 0.3 wt% Sc (scandium) -containing film was formed by an electron beam evaporation method or a sputtering method.

Then, a photoresist was applied on the surface by a known spin coating method, and patterning was performed by a known photolithography method. Then, the aluminum film was etched with phosphoric acid. In this way, the gate electrodes / wirings 46a, 4
6b was formed. The photoresist masks 47a and 47b were left on the gate electrode / wiring. Also, due to overetching,
The side surface of the wiring is inside the side surface of the photoresist.
(Fig. 4 (B))

In this state, impurities are implanted into the active semiconductor layers 42a and 42b of the TFT by ion doping using the photoresists 47a and 47b as masks,
An N type source 48a and drain 48b were formed. Here, with respect to the photoresist 47a, the gate electrode 46a
Is inside by the distance x, and therefore, as shown in the figure, the gate electrode and the source / drain are in an offset state where they do not overlap each other. The distance x can be increased or decreased by adjusting the etching time for aluminum wiring. As x, 0.3 to 5 μm was preferable. (Fig. 4 (C))

After that, the photoresists 47a and 47b are peeled off, and a KrF excimer laser (wavelength 248 nm,
A pulse width of 20 nsec) was applied to activate the impurity ions introduced into the active layer. In this laser annealing, the side end portions 44a and 44b of the island-shaped regions 42a and 42b are also laser-irradiated, and react with silicon in the regions to react with the chemical formula Si ₃ N _4-x (0 <x <4). Is formed. Even when carbon and oxygen are introduced instead of nitrogen, the chemical formulas of Si _x C
_The substances represented by _1-x (0 <x <1) and SiO _2−x (0 <x <2) are obtained. (Fig. 4 (D))

Finally, a silicon oxide film having a thickness of 2000 Å or more is formed on the entire surface as an interlayer insulator 49 by a plasma CVD method.
1 μm was formed. Further, contact holes are formed in the source 48a and the drain 48b of the TFT, and the aluminum wirings 50a and 50b are 2000 Å to 1 μm, for example, 50.
It was formed to a thickness of 00Å. The reliability can be further improved by forming, for example, titanium nitride as a barrier metal under the aluminum wiring (FIG. 4).
(E))

[Third Embodiment] FIG. 5 shows the present embodiment. First, a base film 52 of silicon oxide having a thickness of 1000 to 3000 Å was formed on a substrate 51. Furthermore, an amorphous silicon film is formed by plasma CVD or LPCVD.
~ 5000Å, preferably 300-1000Å. A silicon oxide film was deposited on the amorphous silicon film as a protective film in an amount of 100 to 500 liters. Then, this was annealed at 600 ° C. for 48 hours in a reducing atmosphere to be crystallized. The crystallization step may be a method using strong light such as a laser. Further, resist masks 54a and 54b were formed by a known photolithography method, and amorphous silicon was etched by a dry etching method. The etching conditions at this time were as follows. RF power: 500 W Pressure: 100 mTorr Gas flow rate CF ₄ : 50 sccm O ₂ ; 45 sccm

As a result, as shown in FIG. 5A, island-shaped silicon regions 53a and 53b were obtained, but the edge portions thereof were tapered as shown in the figure. The angle of this taper was 20 to 60 °. In etching, if the ratio CF ₄ / O ₂ becomes large, such a tapered edge could not be obtained. Next, silicon was injected using this resist as a mask. A known ion implantation method is used for implanting silicon, for example, 8
Silicon was implanted at an accelerating voltage of 0 keV and a dose amount of 5 × 10 ¹⁵ cm ⁻² . As a result, the edge portions 55a, 55 of the silicon region having no or thin resist are formed.
Silicon was injected into b, 55c, and 55d. (Fig. 5
(A))

Next, a thickness of 10 is obtained by the sputtering method.
A silicon oxide film 56 of 00Å is deposited as a gate insulating film,
Subsequently, a thickness of 6000 to 80 is obtained by a sputtering method.
An aluminum film (containing 0.2% by weight of scandium) of 00Å, for example 6000Å, was deposited. In addition, it is desirable that the steps of forming the silicon oxide film and the aluminum film are continuously performed. Then, the aluminum film was patterned to form wirings 57a and 57b. Each of these wirings functions as a gate electrode. Further, the surface of this aluminum wiring was anodized to form oxide layers 58a and 58b on the surface. (Fig. 5 (B))

The anodization was carried out in a 1-5% ethylene glycol solution of tartaric acid. The thickness of the obtained oxide layer was 2000Å. Next, the wiring 57a and the oxide 58a are formed in the silicon region by plasma doping.
Impurities (phosphorus) were implanted using the as a mask. Phosphine (PH ₃ ) was used as a doping gas, and the acceleration voltage was set to 60 to 90 kV, for example, 80 kV. Dose is 1
× 10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 , for example, 1 × 10 ¹⁵ cm
^-2 . In this way, the N type impurity regions 59a, 5
9b was formed. (Fig. 5 (C))

After that, the impurities were activated by the laser annealing method. As a laser, a KrF excimer laser (wavelength 248 nm, pulse width 20 nse
Although c) is used, other lasers such as XeF excimer laser (wavelength 353 nm), XeCl excimer laser (wavelength 308 nm), ArF excimer laser (wavelength 193 nm) and the like may be used. The energy density of the laser was 200 to 350 mJ / cm ² , for example, 250 mJ / cm ^2, and the irradiation was performed for 2 to 10 shots, for example, 2 shots per location. The substrate may be heated to about 200 to 450 ° C. during laser irradiation. It should be noted that the optimum laser energy density changes when the substrate is heated.

In this embodiment, of the regions 55a, 55b, 55c and 55d in which silicon ions are implanted,
55a and 55b are crystallized in this laser annealing step. However, the portions 55c and 55d below the gate electrode are not crystallized because they are not irradiated with laser light, and therefore function as an extremely large resistance and are effective for the purpose of reducing the leak current. In this embodiment, since the phosphorus-doped region is separated from the gate electrode by the thickness x of the anodic oxide, the gate electrode and the source / drain are in an offset state. (Figure 5 (D))

Then, a silicon oxide film 60 having a thickness of 3000 Å is formed.
Is formed by plasma CVD as an interlayer insulator,
A contact hole is formed in this, and the wiring 6 is made of a metal material, for example, a multilayer film of titanium nitride and aluminum.
1a and 61b were formed. The TFT was completed by the above steps. (Fig. 5 (E))

[0037]

According to the present invention, it is possible to improve the yield of thin film semiconductor devices, enhance their reliability, and maximize the characteristics. The thin film semiconductor device of the present invention is particularly preferable as a transistor for controlling pixels in an active matrix circuit of a liquid crystal display because it has a low leak current between a gate and a drain and a leak current between a gate and a source and can withstand a high gate voltage. .

Although the present invention has been described by taking the N-channel type TFT as an example, the P-channel type TFT or the N-channel type TFT on the same substrate.
It goes without saying that the same can be applied to the case of the phase trapping type circuit in which the channel type and the P channel type are mixed. Also, not only the simple structure shown in the embodiment,
For example, a TFT having a structure having silicide in the source / drain as shown in Japanese Patent Application No. 5-256567.
May be used for.

Further, although the present embodiment mainly shows the TFT, other circuit elements such as a thin film integrated circuit having a plurality of gate electrodes in one island region, a stacked gate type TFT, a diode, a resistor. Needless to say, it can be applied to a capacitor, or a thin film semiconductor circuit in which the capacitor is integrated. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

FIG. 1 shows a configuration example of a semiconductor device (TFT) of the present invention.

FIG. 2 shows a configuration example of a conventional semiconductor device (TFT).

3A to 3C are cross-sectional views of a manufacturing process of the TFT of Example 1.

4A to 4C show cross-sectional views of a manufacturing process of a TFT of Example 2.

5A to 5C show cross-sectional views of a manufacturing process of a TFT of Example 3.

[Explanation of symbols]

 10 ... Island semiconductor region 11 ... Substrate 12 ... Channel formation region (substantially intrinsic) 13 ... Impurity region (source / drain) 14 ... High resistance region 15 ... Gate insulation Film 16 ... Edge of island-shaped semiconductor region 17 ... Gate electrode 18 ... Source / drain electrode

Claims (11)

[Claims] 1. A thin film semiconductor device having an island-shaped non-single-crystal thin film semiconductor region having a tapered edge formed on an insulating surface, and a gate electrode crossing the semiconductor region, wherein the semiconductor region has a taper. A thin film semiconductor device, wherein the edge portion contains an element different from the main component of the semiconductor region. 2. The thin film semiconductor according to claim 1, wherein the element different from the main component of the semiconductor region is an impurity exhibiting a conductivity type opposite to the conductivity type of the source and drain of the semiconductor device. apparatus. 3. The thin film semiconductor device according to claim 1, wherein the element different from the main component of the semiconductor region is at least one of carbon, nitrogen and oxygen. 4. A thin film semiconductor device having an island-shaped non-single crystal thin film semiconductor region having a tapered edge formed on an insulating surface and a gate electrode crossing the semiconductor region, the periphery of the semiconductor region. A thin-film semiconductor device, characterized in that there is a region into which fast ions are implanted, and a gate electrode crosses the region. 5. The thin film semiconductor device according to claim 4, wherein the implanted fast ions are impurities that exhibit a conductivity type opposite to the conductivity type of the source and drain of the semiconductor device. 6. The thin film semiconductor device according to claim 4, wherein the implanted fast ions are at least one of carbon, nitrogen and oxygen. 7. The thin film semiconductor device according to claim 4, wherein the implanted fast ions are silicon. 8. A step of directly or indirectly forming a mask material on a non-single-crystal semiconductor thin film and patterning it in an island shape by a photolithography method, and a step of forming the mask material by a dry etching method or a wet etching method. According to the pattern, the semiconductor thin film is etched into an island shape, and at the same time, the edge portion of the island semiconductor region is processed into a taper shape. A method of manufacturing a thin film transistor, comprising: a step of accelerating irradiation and a step of forming a gate electrode across the semiconductor thin film. 9. The method for manufacturing a thin film transistor according to claim 8, wherein the ion is an impurity ion which exhibits a conductivity type opposite to a conductivity type of a source and a drain of the semiconductor device. 10. The method for manufacturing a thin film transistor according to claim 8, wherein the ion is at least one of carbon, nitrogen, and oxygen. 11. The method for manufacturing a thin film transistor according to claim 8, wherein the ions are silicon.