JP3535493B2 - CMOS circuit and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a structure and a manufacturing method of a thin film transistor (TFT).
The thin film transistor manufactured by the present invention is formed on either an insulating substrate such as glass or a semiconductor substrate such as single crystal silicon.

[0002]

2. Description of the Related Art Conventionally, a thin film transistor is formed by patterning a thin film semiconductor region (active layer) in an island shape, and then forming an insulating film as a gate insulating film by a CVD method or a sputtering method, and then forming a gate film thereon. The electrode was formed.

[0003]

The insulating coating formed by the CVD method or the sputtering method has a poor step coverage (step coverage), which adversely affects reliability, yield, and characteristics. FIG. 3 is a top view of a typical conventional TFT,
And a cross-sectional view taken along line AA ′ and BB ′ of the drawing. The TFT is formed on the substrate 31, the thin-film semiconductor region is located below the impurity region (source and drain regions, which shows N-type conductivity here) 33 and the gate electrode 37, and is a substantially intrinsic channel forming region. A gate insulating film 35 is provided so as to cover the semiconductor region. A contact hole is opened in the impurity region 33 through an interlayer insulator 39, and an electrode / wiring 38 is provided.

As can be seen from the figure, the coverage of the end portion of the semiconductor region of the gate insulating film 35 is extremely poor, and typically only half the thickness of the flat portion is present. Generally, when the island-shaped semiconductor region is thick, it is extremely large. Particularly, from the AA 'cross section along the gate electrode, it can be seen that such deterioration of the covering property adversely affects the characteristics, reliability and yield of the TFT. That is, paying attention to the region 36 indicated by the dotted circle in the AA ′ sectional view of FIG. 5, the electric field of the gate electrode 37 is intensively applied to the end portion of the thin film semiconductor region. That is, since the thickness of the gate insulating film in this portion is half that of the flat portion, the electric field strength thereof is doubled.

As a result, the gate insulating film in this region 36 is easily destroyed by applying a high voltage for a long time. If the signal applied to the gate electrode is positive, the semiconductor in this region 36 is also N-type, so that the gate electrode 37 and the impurity region 38 (particularly, the drain region) become conductive, which causes a decrease in reliability. Become.

When the gate insulating film is destroyed,
It happens that some charge is trapped, for example
If the negative charges are trapped, the semiconductor in the region 36 exhibits N type and the two impurity regions 38 become conductive regardless of the voltage applied to the gate electrode, which deteriorates the characteristics. Further, in order to use the TFT without causing the above deterioration, only half the voltage as in the ideal case can be applied, and the performance cannot be fully utilized.

The presence of such a weak portion in a part of the TFT means that the TFT is easily destroyed due to charging or the like in the manufacturing process, which is a major factor for lowering the yield. An object of the present invention is to solve such a problem.

[0008]

The present invention is characterized in that the semiconductor in such an electrically weak region is supplemented by making it an intrinsic semiconductor having a high resistance or the same conductivity type as that of the channel forming region. A typical structure of the present invention is shown in FIG.
Shown in. As shown in FIG. 1 (A), in the present invention, in the vicinity of the portion where the gate electrode 11 crosses at the end of the island-shaped semiconductor region, in the portion which is the impurity region (source, drain) in the conventional TFT. A region 14 having the same conductivity type as the intrinsic region or the channel formation region is provided. That is,
In the TFT of the present invention, in the island-shaped semiconductor region, in the portion not covered with the gate electrode, other than the impurity region (source, drain) 13 doped with impurities,
There is a substantially intrinsic region or a region 14 of the same conductivity type as the channel forming region.

FIG. 1B shows another example of the present invention, but the substantial structure is the same as that of FIG. 1A except that the shape of the island-shaped semiconductor region is different. Reference numeral 16 in the figure denotes an electrode connected to the source and drain.

The effect of providing the intrinsic region 14 or the region of the same conductivity type as that of the channel forming region in this manner will be described with reference to FIG. FIG. 4A shows a structure and an equivalent circuit of a conventional TFT. In the figure, X and Y are portions where the gate electrode crosses the island-shaped semiconductor region, but the gate insulating film in this portion is thinner than the flat portion as described above.
Therefore, as shown in the equivalent circuit, a parasitic TFT having a lower threshold value and lower withstand voltage than the original TFT is formed.

If an excessive voltage is applied to the gate, the parasitic TFT is destroyed before the original TFT is destroyed, and the parasitic TFT becomes a mere conductor, and the source,
The leak current between the drains or between the source and the gate increases.

On the other hand, the present invention has a structure as shown in FIG. 4B and an equivalent circuit. Also in the present invention, the parasitic TF
The formation of T, X, and Y is the same as in the conventional case.
However, in the present invention, since a part of the island-shaped semiconductor region is an intrinsic semiconductor region, the resistance is high, and this resistance R is inserted in series to the parasitic TFT, so that the source and drain voltages are not directly applied to the parasitic TFT. It becomes a structure. Also,
When a region of the same conductivity type as the channel formation region is provided, the conductivity type is opposite to that of the source and drain, so
The PN junction forms a barrier equivalent to resistance.

Therefore, even when an excessive voltage is applied to the gate electrode, the voltage is reduced by the above resistance inserted in series with the source and drain of the parasitic resistance, and the parasitic TFT is not destroyed. As a result, the deterioration of reliability, yield, and deterioration of characteristics which have been problems in the conventional TFT can be solved.

The steps for carrying out the present invention are shown in FIG.
A brief description will be given using (H). First, the island-shaped semiconductor region 10 is formed on the substrate. Usually this semiconductor region is substantially intrinsic, but may be weakly N-type or P-type. (Fig. 1 (C))

Then, after forming the gate insulating film, as shown in FIG.
A gate electrode 11 is provided as shown in FIG. afterwards,
Impurities are implanted as indicated by 12 in FIG. As a result, as shown in FIG. 1F, an impurity region 13 and a region 14 sandwiched between the impurity region and the gate electrode are formed. The area 14 is preferably an area having a dimension of 2 to 5 μm. The conductivity type of this region is the same as that of the island semiconductor, and if the island semiconductor is intrinsic, this region 14 is also intrinsic, and the typical resistivity is 10 ⁶ Ωcm or more.

FIG. 1G shows the T shown in FIG.
The state where the gate electrode of FT is removed is shown. As is clear from this figure, the channel formation region 15 and the region 14 shown in FIG. 1F have the same conductivity type. Finally, electrodes 16 are formed on the source and drain to complete the TFT. (Fig. 1
(H))

In the present invention, for example, either N-channel type or P-channel type TFT is provided on the substrate.
In the case of forming only the structure, the number of photolithography steps is increased by one, but this does not cause any obstacle in view of the improvement in the characteristics, reliability and yield obtained by the present invention.

Furthermore, when the present invention is applied to a complementary circuit (CMOS circuit) in which N-channel type TFTs and P-channel type TFTs are mixed, the effect becomes more apparent. In a CMOS circuit, the simplest manufacturing method is to reverse the process of first introducing N-type or P-type impurities into the entire surface of the substrate, then masking necessary portions, and canceling the previously introduced impurities. A conductive type impurity is introduced. This method is tentatively called the first method. However, in the first method, for example, the N-type region has a dose amount of 1 × 10 ¹⁵ cm ⁻² , but the P-type region requires a dose amount of 5 × 10 ¹⁵ cm ⁻² , and the withstand voltage is high. In some cases, the N-channel TFT and the P-channel TFT cannot be balanced in terms of threshold value and the like.

The most reliable method, however, is to first perform masking to introduce N-type or P-type impurities, and then again to carry out masking to introduce impurities of a conductivity type opposite to the previous impurities. . This method is called the second method. In this case, since the concentrations of the N-type impurity and the P-type impurity can be set completely independently, ideal characteristics as a CMOS circuit can be expected. However, in this case, one photolithography process is added as compared with the first method.

In the CMOS circuit according to the present invention, N type, P type
If it is to be applied to both type TFTs, N-type impurities and P-type impurities must be masked and introduced separately. Therefore, the second method of the above two methods is adopted. Although the second method complicates the manufacturing process, the obtained characteristics are excellent, as described above. Since the effect of the present invention is obtained in addition to the effect, the demerit of adding one photolithography step is completely canceled. Examples will be shown below for implementing the present invention particularly in manufacturing a CMOS circuit.

[0021]

EXAMPLE FIG. 2 shows a cross-sectional view of the manufacturing process of this example.
A base film 21 of silicon oxide having a thickness of 200 nm was formed on the substrate (Corning 7059) 20 by sputtering. Furthermore, by plasma CVD method, a thickness of 50 to 1
A 50 nm, for example 150 nm, amorphous silicon film was deposited. Subsequently, a 20-nm-thick silicon oxide film was deposited as a protective film by a sputtering method. Then, this was annealed at 600 ° C. for 48 hours in a reducing atmosphere to be crystallized. The crystallization step may be a method using strong light such as a laser. Then, the obtained crystalline silicon film was patterned to form island-shaped silicon regions 22P and 22N.

Next, a thickness of 10 is obtained by the sputtering method.
A 0 nm silicon oxide film 23 is deposited as a gate insulating film,
Subsequently, the thickness of 600 to 80 is obtained by the low pressure CVD method.
0 nm, for example 600 nm silicon film (0.01-2
% Phosphorus) was deposited. It is desirable that the steps of forming the silicon oxide and the silicon film are continuously performed.
Then, the silicon film is patterned to form the gate electrode 2
4P and 24N were formed. (Fig. 2 (A))

Next, the semiconductor region 22P is masked with a photoresist 25N, and plasma doping is performed by a plasma doping method.
Impurities (phosphorus) were implanted into the silicon region 22N using the wiring 24N as a mask. As the material of the mask 25, metal materials such as chromium, titanium, titanium nitride, and aluminum, and metal nitride materials can be used in addition to the above. The doping pattern has a shape as shown in FIG. Phosphine (PH ₃ ) was used as a doping gas, and the acceleration voltage was set to 60 to 90 kV, for example, 80 kV. The dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 , for example, 1 × 10
^{It was set to 15} cm ^-2 . As a result, the N-type impurity region 26N was formed. After doping, resist mask 25N
Was removed by an ashing process in an oxygen atmosphere. Typical ashing condition is 1 Torr, RF
The power was 300 W.

Further, when the activation is performed by a laser later, the silicon oxide 2 on the silicon region 22N is formed by hydrofluoric acid before removing the resist mask.
3 should be selectively removed. This is effective in preventing unevenness on the surface due to the reaction between the silicon oxide 23 and the silicon region 22N during laser irradiation. (Fig. 2 (B))

Further, this time, the semiconductor region 22N was masked with the photoresist 25P, and an impurity (boron) was implanted into the silicon region 22P by the plasma doping method using the wiring 24P as a mask. Also in this case, the doping pattern has a shape as shown in FIG. Diborane (B ₂ H ₆ ) was used as a doping gas, and the acceleration voltage was set to 20 to 70 kV, for example, 65 kV. The dose amount was set to 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 1 × 10 ¹⁵ cm ⁻² . As a result, the P-type impurity region 26P is formed. After doping, resist mask 2
5P was removed by the ashing process. (Fig. 2
(C))

Then, the impurities were activated by annealing at 600 ° C. for 48 hours in a reducing atmosphere.
This step may be performed by laser annealing. In that case, a KrF excimer laser (wavelength 248 nm), a XeF excimer laser (wavelength 353 nm), a XeCl excimer laser (wavelength 308 nm), an ArF excimer laser (wavelength 193 nm), or the like is used as the laser.
200 to 350 mJ / cm ² , for example 250 mJ / cm ²
Therefore, it is sufficient to irradiate 2 to 10 shots, for example, 2 shots, at one place. Substrate 200-
You may heat to about 450 degreeC. It should be noted that the optimum laser energy density changes when the substrate is heated.

After activation of the impurities, the thickness of 300-
A silicon oxide film 27 having a thickness of 1000 nm, for example 600 nm, is formed as an interlayer insulator by a plasma CVD method, a contact hole is formed in the film, and a wiring 28P is formed of a metal material such as a multilayer film of titanium nitride and aluminum.
28N was formed. Through the above steps, a CMOS semiconductor circuit is completed. (Fig. 2 (D))

[0028]

According to the present invention, it is possible to improve the yield of TFTs, enhance their reliability, and bring out the maximum characteristics. Moreover, in obtaining such a large effect, there is a great merit that it can be carried out without involving a large process change, investment, and technological development. Although the present invention has been described by taking the TFT on the insulating substrate as an example,
Needless to say, the present invention can be applied to a TFT formed on a single crystal semiconductor substrate. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

1A and 1B are conceptual diagrams showing a structure of a TFT of the invention and a manufacturing method thereof.

2A to 2C show cross-sectional views of a manufacturing process of a TFT of an example.

FIG. 3 shows a configuration example of a conventional TFT.

FIG. 4 illustrates electrical characteristics of the present invention and a conventional TFT.

[Explanation of symbols]

10 ... Island semiconductor region 11 ... Gate electrode 12 ... Impurity introduction region 13 ... Impurity region (source, drain) 14: Area where impurities are not introduced 15 ... Channel formation region 16 ... Source electrode, drain electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/78 621 27/08 321A (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21 / 336 H01L 21/8238 H01L 27/08 H01L 27/092

Claims (8)

(57) [Claims] 1. A CMOS circuit having an N-channel type TFT and a P-channel type connected to the N-channel type TFT, wherein the N-channel type TFT and the P-channel type TFT are provided.
Each has a cross-shaped thin film semiconductor, a gate insulating film on the cross-shaped thin film semiconductor, and a gate electrode on the gate insulating film, and the cross-shaped thin film semiconductor has the gate electrode above. No. 1 region, a second region in contact with an end of the first region and an end of the cross-shaped thin film semiconductor, and in the vicinity of a portion traversed by the gate electrode, the first region and the first region. The second region is a non-implanted region of an n-type or p-type impurity and is divided into a third region which is an n-type or p-type impurity-implanted region not including the second region. A CMOS circuit, wherein the gate insulating film is selectively removed before the activation process. 2. A CMOS circuit having an N-channel TFT and a P-channel TFT connected to the N-channel TFT, wherein the N-channel TFT and the P-channel TFT are provided.
Each has a cross-shaped thin film semiconductor, a gate insulating film on the cross-shaped thin film semiconductor, and a gate electrode on the gate insulating film. The cross thin film semiconductor has the gate electrode above. Region, which is in contact with the end of the first region and the end of the cross-shaped thin film semiconductor, and is in the vicinity of a portion of the cross-shaped thin film semiconductor crossed by the gate electrode. And does not include the first region and the second region,
The third region is an n-type or p-type impurity implantation region into which an impurity is introduced, the second region has the same conductivity type as the channel formation region, and the gate insulating film is , A CMOS circuit characterized by being selectively removed before the activation process. 3. The CMOS circuit according to claim 2, wherein the first region and the second region have weak P-type or weak N-type conductivity. 4. The CMOS circuit according to claim 1, wherein the electric resistance value of the second region is higher than the electric resistance value of the third region. 5. A cross-shaped thin film semiconductor is formed on a substrate, an insulating film is formed on the cross-shaped thin film semiconductor, a gate electrode is formed on the insulating film, and ends of the cross-shaped thin film semiconductor are formed. Part and an end portion of the gate electrode, and impurities are introduced by using a first mask which overlaps at least with the vicinity of a portion traversed by the gate electrode, and the insulating film is removed by using the first mask. An impurity having a conductivity type opposite to that of the impurity is used by using a second mask which is in contact with the end of the thin film semiconductor and the end of the gate electrode and at least overlaps with the vicinity of a portion crossed by the gate electrode. And a method for manufacturing a CMOS circuit in which the impurities are introduced and then activated. 6. A cross-shaped thin film semiconductor is formed on a substrate, an insulating film is formed on the cross-shaped thin film semiconductor, a gate electrode is formed on the insulating film, and impurities are introduced into the entire surface of the substrate. Using a mask that is in contact with the end of the thin film semiconductor and the end of the gate electrode and does not at least overlap with the vicinity of the portion traversed by the gate electrode, the reverse cross-section only cancels the impurities in the cross-shaped thin film semiconductor. The method for manufacturing a CMOS circuit, wherein the conductivity type impurity is introduced, and after the impurity is introduced, the insulating film is removed using the mask and activation is performed. 7. The method for manufacturing a CMOS circuit according to claim 5, wherein the activation is performed by irradiating a laser. 8. The C according to claim 5, wherein the insulating film is C removed by hydrofluoric acid.
Manufacturing method of MOS circuit.