JPH06314698A - Thin-film semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To enhance the yield of a thin-film semiconductor device, to increase its reliability and to draw out its characteristic to the full by a method wherein a region in which the concentration of at least one chemical element out of oxygen, carbon and nitrogen is larger than the average concentration of an island-shaped semiconductor region is formed at the peripheral part of the semiconductor region. CONSTITUTION:A thin-film semiconductor device is provided with an island- shaped thin-film semiconductor region 10 and with a gate electrode 17 which traverses the semiconductor region 10. In the thin-film semiconductor device, regions 14 in which the concentration of at least one chemical element out of oxygen, carbon and nitrogen is larger than the average concentration of the semiconductor region 10 exist at peripheral parts of the semiconductor region 10, and the gate electrode 17 travserses the regions 14. For example, when the average concentration of nitrogen in a semiconductor region 10 is at 1X10<18>cm<-3>, the nitrogen is introduced in such a way that the concentration of nitrogen in regions 14 is at a concentration of 1X10<19>cm<-3> or higher, preferably 1X10<20>cm<-3>, the nitrogen is reacted with silicon as a semiconductor and Si3N4-x is formed. As a result, the resistance of the regions 14 rises remarkably.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and manufacturing method of a circuit element used in a thin film integrated circuit, for example, a thin film transistor (TFT). The thin film transistor manufactured by the present invention is on an insulating substrate such as glass,
It is formed on any insulator formed on a semiconductor substrate such as single crystal silicon.

[0002]

2. Description of the Related Art Conventionally, a thin film transistor is formed by patterning a thin film semiconductor region (active layer) in an island shape, and then forming an insulating film as a gate insulating film by a CVD method or a sputtering method, and then forming a gate film thereon. The electrode was formed.

[0003]

The insulating coating formed by the CVD method or the sputtering method has a poor step coverage (step coverage), which adversely affects reliability, yield, and characteristics. FIG. 5 is a top view of a typical conventional TFT,
And a cross-sectional view taken along line AA ′ and BB ′ of the drawing. The TFT is formed on the substrate 51, the thin film semiconductor region is located below the impurity region (source / drain region, which shows N type conductivity here) 53 and the gate electrode 57, and is a substantially intrinsic channel forming region. A gate insulating film 55 is provided so as to cover the semiconductor region. A contact hole is opened in the impurity region 53 through an interlayer insulator 59, and an electrode / wiring 58 is provided.

As can be seen from the figure, the coverage of the end portion of the semiconductor region of the gate insulating film 55 is extremely poor, and typically only half the thickness of the flat portion is present. Generally, when the island-shaped semiconductor region is thick, it is extremely large. Particularly, from the AA 'cross section along the gate electrode, it can be seen that such deterioration of the covering property adversely affects the characteristics, reliability and yield of the TFT. That is, paying attention to the region 56 indicated by the dotted circle in the AA ′ sectional view of FIG. 5, the electric field of the gate electrode 57 is intensively applied to the end portion of the thin film semiconductor region. That is, since the thickness of the gate insulating film in this portion is half that of the flat portion, the electric field strength thereof is doubled.

As a result, the gate insulating film in the region 56 is easily destroyed by applying a high voltage for a long time. If the signal applied to the gate electrode is positive, the semiconductor in this region 56 is also N-type, so that the gate electrode 57 and the impurity region 58 (particularly, the drain region) become conductive, which causes deterioration in reliability. Becomes In addition, a slow leak (current leakage) occurs between the source and the drain, and a reverse polarity voltage (negative for an N-channel TFT, P
If it is a channel type, even if a positive voltage is applied,
A minute leak current is generated and the off current increases.

When the gate insulating film is destroyed,
It happens that some charge is trapped, for example
If the negative charges are trapped, the semiconductor in the region 56 exhibits N-type and the two impurity regions 58 become conductive regardless of the voltage applied to the gate electrode, which deteriorates the characteristics. Further, in order to use the TFT without causing the above deterioration, only half the voltage as in the ideal case can be applied, and the performance cannot be fully utilized.

The presence of such a weak portion in a part of the TFT means that the TFT is easily destroyed due to charging or the like in the manufacturing process, which is a major factor for lowering the yield. An object of the present invention is to solve such a problem.

[0008]

According to the present invention, in the semiconductor of such an electrically weak region, any one element or a plurality of elements of carbon, oxygen and nitrogen is averaged in an island-shaped semiconductor region. By increasing the concentration above that, the chemical formula Si _x C _1-x (0 <x <1), SiO
_2-x (0 <x <2), Si ₃ N _4-x (0 <x <4) or a semi-insulating or insulating region represented by SiC _y N _z O _z should be formed, and in that region It is characterized by supplementing by increasing the resistance of. A typical structure of the present invention is shown in FIG. Similarly to FIG. 5, FIG. 1 also shows a drawing in which the TFT is viewed from above and cross-sectional views taken along the lines AA ′ and BB ′. The TFT is formed on the substrate 11, and the thin film semiconductor region is an impurity region (source and drain regions, which are N-type conductivity type here, but may be P-type).
A gate insulating film 15 is provided under the gate electrode 17 and the gate electrode 17, and is divided into a substantially intrinsic channel forming region 12 and covers this semiconductor region. A contact hole is formed in the impurity region 13 through an interlayer insulator 19, and an electrode / wiring 18 is provided.

The difference from the conventional TFT shown in FIG. 5 is that
A region 14 in which the concentration of at least one element of nitrogen, oxygen, and carbon is higher than the average concentration of the semiconductor region is provided at least at the peripheral portion of the island-shaped semiconductor region 10 below the gate electrode, that is, at the end of the region 10. That is. For example,
If the average nitrogen concentration in the semiconductor region is 1 × 10 ¹⁸ cm ⁻³ , the nitrogen concentration in this portion should be 1 × 10 ¹⁹ cm ⁻³ or higher, preferably 1 × 10 ²⁰ cm ⁻³ or higher. Introduce nitrogen so that it reacts with semiconductor silicon,
Si ₃ N _4-x (0 <x <4) is formed. As a result, the resistance of the region 14 increases significantly. The same applies when oxygen or carbon is used, 1 × 10 ¹⁹ cm ⁻³ or more, preferably 1 × 1
By introducing oxygen and carbon so as to have a concentration of 0 ²⁰ cm ^-3 or more, the high resistance region 14 could be formed. By doing so, the energy band width becomes larger than that of the other channel forming regions 12, so that when a high voltage is applied to the gate electrode, the electric field strength channel forming region is intentionally formed between the side edge portion and the channel. It can be made weaker than the above, and electrical breakdown and leakage can be suppressed.

The effect of the region 14 will be described by focusing on the region 16 of the AA 'cross section. As in the case of the conventional TFT, the coverage of the gate insulating film at the end of such a semiconductor region is not good. Therefore, in this portion, the gate insulating film is destroyed by a voltage of about half that in the ideal case, and pinholes are generated or charges are trapped. However, when the region 14 exists, the resistance of the region 14 reduces the voltage applied to the gate insulating film. As a result, the breakdown of the gate insulating film can be prevented. Further, even if a pinhole is generated or charge is trapped in the gate insulating film at the end of the semiconductor region, this portion is isolated from the impurity region 13 and the channel forming region 12 below the gate electrode by the region 14. As it is done, it has almost no effect.

Therefore, the leak current between the gate electrode and the drain region and the leak current between the source and the drain can be remarkably reduced. In addition, if the characteristics and reliability are not affected even when the gate insulating film is destroyed in this way, the voltage limit during use is reduced, and defective products are generated due to electrostatic breakdown during manufacturing. The probability of is also reduced and the yield is improved.

Although FIG. 1 shows a state in which nitrogen, carbon, oxygen or the like is introduced into all the ends of the thin film semiconductor region 10 on the side where the gate electrode crosses, such a region is at least under the gate electrode. It will be apparent from the above description that it is sufficient to provide the area. It should be noted that when an organic material such as a photoresist is used as a mask when doping oxygen, the mask is oxidized and disappears if the dose amount is large. When introducing nitrogen, oxygen, and carbon, not only a method of defining a region by a photolithography method but also a method of determining an introduction portion in a self-aligned manner by taper etching may be used. Hereinafter, the present invention will be described with reference to examples.

[0013]

【Example】

Example 1 FIG. 2 shows a cross-sectional view of a manufacturing process of this example. In the drawings of the following embodiments including this embodiment, TF
Only the cross-sectional view of T is shown, and in each case, a TFT having a surface perpendicular to the gate electrode (corresponding to the cross section BB ′ in FIGS. 1 and 5) is formed on the left side, and the TFT is parallel to the gate electrode on the right side An example of forming a TFT having a flat surface (corresponding to the cross section AA ′ in FIGS. 1 and 5) is shown.

First, a base film 21 of silicon oxide having a thickness of 2000 Å was formed on a substrate (Corning 7059) 20 by sputtering. Further, an amorphous silicon film having a thickness of 500 to 1500 Å, for example 1500 Å, was deposited by the plasma CVD method. The concentration of nitrogen in the amorphous silicon film is determined by secondary ion mass spectrometry (SIM
It was 1 × 10 ¹⁸ cm ⁻³ or less as measured by the S) method.
Subsequently, a 200 Å-thick silicon oxide film was deposited as a protective film by a sputtering method. Then, this was annealed at 600 ° C. for 48 hours in a reducing atmosphere to be crystallized. The crystallization step may be a method using strong light such as a laser. Then, the obtained crystalline silicon film was patterned to form island-shaped silicon semiconductor regions 22a and 22b. Protective films 23a and 23b are respectively placed on the island-shaped silicon film. This protective film has a function of preventing the island-shaped silicon region from being contaminated in the subsequent photolithography process.

Next, a photoresist is applied on the entire surface and the resist 24 is formed by a known photolithography method.
Patterning was performed leaving a and 24b. Then, using this resist as a mask, nitrogen, carbon, oxygen, here, nitrogen was selectively introduced into the end portion of the island-shaped semiconductor region. A plasma doping method was used to introduce nitrogen. Nitrogen gas is used as a doping gas, rf power is 10 to 30 W,
For example, it is discharged at 10 W to generate plasma, which is accelerated by an accelerating voltage of 20 to 60 kV, for example, 20 kV,
Introduced into the silicon area. The dose amount is 1 × 10 ^{15 to} 5
It was set to × 10 ¹⁶ cm ^-2 , for example, 1 × 10 ¹⁶ cm ^-2 . As a result, the nitrogen-doped regions 25a, 25b, 25
c, 25d were formed. Under these conditions, the nitrogen concentration in this nitrogen-doped region is 1 × 10 ²⁰ to 2 × 10 ²² cm 2.
⁻³ , for example, about 1 × 10 ²¹ cm ^−3, and a significantly large amount of nitrogen was introduced compared to other semiconductor regions. (Fig. 2
(A))

Next, the masks 24a and 24b are removed, the silicon oxide protective films 23a and 23b thereunder are also removed to expose the surfaces of the semiconductor regions 22a and 22b, and then a thickness of 1000Å is obtained by a sputtering method. Of the silicon oxide film 26 as a gate insulating film is deposited, and subsequently, a low pressure CVD method is used to form a silicon film having a thickness of 6000 to 8000Å, for example, 6000Å (containing 0.1 to 2% phosphorus).
Was deposited. It is desirable that the steps of forming the silicon oxide and the silicon film are continuously performed. Then, by patterning the silicon film, the wiring 27 of the silicon semiconductor doped with the impurities that constitutes the gate electrode and the lead 27 is formed.
a and 27b were formed. Each of these wirings functions as a gate electrode. (Fig. 2 (B))

Next, impurities (phosphorus) were implanted into the silicon region by plasma doping using the wiring 27a as a mask. As doping gas, phosphine (PH
₃ ) is used and the acceleration voltage is 60 to 90 kV, for example 80 kV.
It was set to V. The dose is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 ,
For example, it is set to 5 × 10 ¹⁵ cm ⁻² . Then, the impurities were activated by annealing at 600 ° C. for 48 hours in a reducing atmosphere. In this way, the impurity region 28
a and 28b were formed. In this heating anneal,
Side end portions 25a, 25b, 25 of the island regions 22a, 22b
The c and 25d are also heated and react with the silicon in the region to form a substance represented by the chemical formula Si ₃ N _4-x (0 <x <4). Even when carbon and oxygen are introduced instead of nitrogen, the chemical formula Si _x C _1-x (0 <x <
1), a substance represented by SiO _2−x (0 <x <2) is obtained. (Fig. 2 (C))

Subsequently, a silicon oxide film having a thickness of 3000 Å is formed as an interlayer insulating film by a plasma CVD method, a contact hole is formed in this film, and a wiring 29a is formed by a metal material, for example, a multilayer film of titanium nitride and aluminum.
29b was formed. The wiring 29a connects the wiring 27b and one of the impurity regions 28b of the TFT. The semiconductor circuit is completed through the above steps. (Fig. 2 (D))

[Embodiment 2] FIG. 3 is a sectional view of a manufacturing process of this embodiment. A base film 302 of silicon oxide having a thickness of 2000 Å was formed on the insulating surface of the substrate (Corning 7059) 301 by sputtering. Further, the thickness is 500 to 1500Å, for example, 1 by plasma CVD method.
A 500Å amorphous silicon film was deposited. Subsequently, a 200 Å-thick silicon oxide film was deposited as a protective film by a sputtering method. Then, this was annealed at 600 ° C. for 48 hours in a reducing atmosphere to be crystallized.
The crystallization step may be a method using strong light such as a laser.
Then, the obtained crystalline silicon film was patterned by a known photolithography method to form island-shaped silicon regions 303a and 303b. A protective film is left on the island-shaped silicon film. Further, the photoresist masks 304a and 304b used for etching are also left. In this etching process, isotropic etching method (for example, wet etching with hydrofluoric nitric acid)
Is used, and the side end portion of the semiconductor region is tapered as shown in the figure. This angle was 30 to 60 with respect to the substrate.

Next, oxygen was introduced using this resist as a mask. A plasma doping method was used to introduce oxygen. Oxygen gas (O ₂ ) or nitrous oxide (N ₂ O) is used as the doping gas, and the acceleration voltage is 20 to 60 k.
It was accelerated in V, for example 20 kV, and introduced into the silicon region. The dose amount was set to 1 × 10 ^{15 to} 5 × 10 ¹⁶ cm ⁻² , for example, 1 × 10 ¹⁶ cm ⁻² . As a result, oxygen-doped regions 305a, 305b, 305c, and 305d were formed. (Fig. 3 (A))

Next, a sputtering method or plasma C
A silicon oxide film 306 having a thickness of 1000 Å was deposited as a gate insulating film by the VD method, and subsequently, an aluminum film (containing 2% silicon) having a thickness of 6000 to 8000 Å, for example, 6000 Å was deposited by a sputtering method.
In addition, it is desirable that the steps of forming the silicon oxide film and the aluminum film are continuously performed. Then, the aluminum film was patterned to form wirings 307a and 307b. Each of these wirings functions as a gate electrode. Further, the surface of this aluminum wiring was anodized to form oxide layers 309a and 309b on the surface. Before the anodization, a mask 308 was selectively formed by using a photosensitive polyimide (photonice) at a portion where a contact was to be formed later. During the anodization, no anodic oxide was formed on this mask portion due to this mask.

The anodic oxidation was performed in a 1-5% ethylene glycol solution of tartaric acid. The thickness of the obtained oxide layer was 2000Å. Next, the wiring 307a and the oxide 30 are formed in the silicon region by plasma doping.
Impurities (phosphorus) were implanted using 9a as a mask. Phosphine (PH ₃ ) was used as a doping gas, and the acceleration voltage was set to 60 to 90 kV, for example, 80 kV. The dose amount is 1 × 10 ¹⁴ to 8 × 10 ¹⁵ cm ⁻² , for example, 5 × 10 ¹⁵
It was cm ^-2 . Thus, the N-type impurity region 310 is formed.
a, 310b was formed. (Fig. 3 (B))

After that, the impurities were activated by the laser annealing method. As a laser, a KrF excimer laser (wavelength 248 nm, pulse width 20 nse
Although c) is used, other lasers such as XeF excimer laser (wavelength 353 nm), XeCl excimer laser (wavelength 308 nm), ArF excimer laser (wavelength 193 nm) and the like may be used. The energy density of the laser was 200 to 350 mJ / cm ² , for example, 250 mJ / cm ^2, and the irradiation was performed for 2 to 10 shots, for example, 2 shots per location. The substrate may be heated to about 200 to 450 ° C. during laser irradiation. It should be noted that the optimum laser energy density changes when the substrate is heated. The polyimide mask 37 was left during the laser irradiation. This is because the exposed aluminum is damaged by laser irradiation. After laser irradiation, this polyimide mask can be easily removed by exposure to oxygen plasma.

In the present embodiment, unlike the case of the first embodiment, the oxygen-implanted region 305 under the gate electrode is formed.
Since c and 305d do not receive the laser light, the crystallization rate is low, but the crystallinity is destroyed during the ion implantation, so that it functions as an extremely large resistance and is effective for the purpose of reducing the leak current. It was (FIG. 3C) However, since the added impurity is oxygen, it is possible to simultaneously react with the silicon semiconductor in the island region to form SiO _2−x when the source and drain are activated. In addition to the examples shown in the examples, first, in FIG. 3A, an island region having tapered side ends is formed, and then carbon, nitrogen,
Oxygen, such as carbon, is selectively introduced at the tapered end. Further, if the photoresists 33a and 33b are removed and then crystallized by laser annealing,
Further, the tapered end portion is formed by Si _x C _1-x (0 <x <
It may be silicon carbide represented by 1). And
Since its energy band width is higher than that of the island-shaped semiconductor region, it is possible to prevent the occurrence of dielectric breakdown and leak in a single portion.

Then, a silicon oxide film 31 having a thickness of 3000 Å is formed.
1 was formed as an interlayer insulator by a plasma CVD method, a contact hole was formed in this, and wirings 312a and 312b were formed by a metal material, for example, a multilayer film of titanium nitride and aluminum. The wiring 312a is the wiring 3
07b is connected to one of the impurity regions 310b of the TFT. Through the above steps, the TFT 313a and the TFT 313 are
The semiconductor circuit consisting of b is completed. (FIG. 3 (D)) In this embodiment, it is apparent that a capacitor is formed between the gate electrode and the remaining impurity region unless either the source electrode or the drain electrode of the TFT is provided. Therefore, even if the same means as this embodiment is used, it is possible to obtain a capacitor having excellent characteristics such as a high breakdown voltage and a small leak, and reliability. Then, a pixel circuit of an active matrix type liquid crystal display may be configured using the TFT and the capacitor thus formed.

[Embodiment 3] FIG. 4 is a cross-sectional view of a manufacturing process of this embodiment. The left side of the figure shows the TFT corresponding to the AA ′ cross section of FIG. 1, and the right side of the figure shows the BB ′ of FIG.
An example of a TFT corresponding to a cross section is shown. Substrate (Corning 7
059) Sputtering method or plasma C on 40
According to VD method, 2000 Å thick silicon oxide, silicon nitride,
Alternatively, a single-layer or multi-layer base film 41 of aluminum nitride was formed. Further, an amorphous silicon film having a thickness of 500 to 1500 Å, for example 1500 Å, was deposited by the plasma CVD method. Then, the obtained amorphous silicon film was patterned to form island-shaped silicon regions 42a and 42b.

Next, a photoresist is applied on the entire surface, and the resist 43 is formed by a known photolithography method.
Patterning was carried out leaving a and 43b. Then, nitrogen was introduced using this resist as a mask. A plasma doping method was used to introduce nitrogen. As a result, nitrogen-doped regions 44a, 44b, 44c and 44d were formed. (Fig. 4 (A))

Next, with the photoresist remaining, a silicon oxide film 45a having a thickness of 1000 Å was deposited by the sputtering method. (FIG. 4B) Then, the photoresist was peeled off to remove the silicon oxide film formed thereon. The silicon oxide film remains as it is in the portion where the photoresist was not present. This was crystallized by annealing at 600 ° C. for 48 hours in a reducing atmosphere. The crystallization step may be a method using strong light such as a laser.

Next, a thickness of 10 is obtained by the sputtering method.
A silicon oxide film 45b of 00Å is deposited as a gate insulating film, and subsequently, a thickness of 6000 is obtained by a low pressure CVD method.
~ 8000Å, eg 6000Å silicon film (0.1
˜2% phosphorus) was deposited. It is desirable that the steps of forming the silicon oxide and the silicon film are continuously performed. Then, the silicon film is patterned to form the wiring 46.
a and 46b were formed. Each of these wirings functions as a gate electrode. Also, paying attention to the peripheral portion of the silicon region on the island (the region where nitrogen was previously implanted), the thickness of the insulating film is approximately doubled here by the silicon oxides 45a and 45b. Therefore, it is effective for preventing the breakdown of the gate insulating film. (Fig. 4 (C))

Next, impurities (phosphorus) were implanted into the silicon region by plasma doping using the wiring 46a as a mask. As doping gas, phosphine (PH
₃ ) was used. Then, in a reducing atmosphere, at 48 ° C at 48
The impurities were activated by annealing for a period of time. Thus, the impurity regions 47a and 47b were formed. Then, a silicon oxide film 48 having a thickness of 3000 Å is formed as an interlayer insulator by a plasma CVD method, a contact hole is formed in the film, and wirings 49a and 49 are made of a metal material, for example, a multilayer film of titanium nitride and aluminum.
b was formed. The wiring 49a connects the wiring 46b and one of the impurity regions 47b of the TFT. The semiconductor circuit is completed through the above steps. (FIG. 4 (D)) The present embodiment improved the yield more than double that of the conventional one. Further, the deterioration of the TFT characteristics was not particularly recognized. On the contrary, since the maximum voltage that can be used has increased 1.5 to 2 times that of the conventional one, the maximum operating speed has increased 2 to 4 times.

[Embodiment 4] FIG. 6 shows the present embodiment. First, a base film 61 of silicon oxide having a thickness of 1000 to 3000 Å was formed on a substrate 60. Furthermore, an amorphous silicon film is formed by plasma CVD or LPCVD.
~ 5000Å, preferably 300-1000Å. A silicon oxide film was deposited on the amorphous silicon film as a protective film in an amount of 100 to 500 liters. Then, the resist mask 63 is formed by a known photolithography method.
A and 63b were formed, and the amorphous silicon was etched by the dry etching method. The etching conditions at this time were as follows. RF power: 500 W Pressure: 100 mTorr Gas flow rate CF ₄ : 50 sccm O ₂ ; 45 sccm

As a result, as shown in FIG.
The silicon regions 62a and 62b of
The area was tapered as shown in the figure. This taper
Angle was 20 to 60 ° with respect to the substrate surface. D
Ratio CF _Four/ O₂Becomes larger,
It is not possible to obtain such a tapered edge
It was Next, using this resist as a mask, oxygen, carbon, and nitrogen are removed.
A source such as nitrogen was introduced. Plasma for introduction of nitrogen
The doping method was used. Nitrogen as doping gas
(N₂), The acceleration voltage is 20 to 60 kV, for example, 20
It was accelerated in kV and introduced into the silicon region. Dose
Is 1 × 10¹⁵~ 5 x 10¹⁶cm^-2, For example, 1 × 10
¹⁶cm^-2And As a result, there was no resist,
The edges 64a, 64 of the thin silicon region
b, 64c, and 64d were doped with nitrogen. (Fig. 6
(A))

After that, a photoresist mask material 63
The amorphous silicon was crystallized by irradiating a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) with the island-shaped silicon film exposed by removing the protective films a and 63b. . As the laser, XeCl excimer laser (wavelength 30
8 nm, pulse width 50 nsec) may be used.
Then, a silicon oxide film 65 having a thickness of 1000 to 1500Å is formed by a sputtering method or a plasma CVD method, and subsequently, aluminum having a thickness of 1000Å to 3 μm (1 wt% Si or 0.1 to 0.3 wt% S is formed).
A film containing c (scandium) was formed by an electron beam evaporation method or a sputtering method.

Then, a photoresist was applied on the surface by a known spin coating method, and patterning was performed by a known photolithography method. Then, the aluminum film was etched with phosphoric acid. In this way, the gate electrodes / wirings 66a, 6a
6b was formed. The photoresist masks 67a and 67b were left on the gate electrode / wiring. Also, due to overetching,
The side surface of the wiring is inside the side surface of the photoresist.
(Fig. 6 (B))

In this state, impurities are implanted into the active semiconductor layers 62a and 62b of the TFT by ion doping using the photoresists 67a and 67b as masks.
An N type source 68a and a drain 68b were formed. Here, with respect to the photoresist 67a, the gate electrode 66a is formed.
Is inside by the distance x, and therefore, as shown in the figure, the gate electrode and the source / drain are in an offset state where they do not overlap each other. The distance x can be increased or decreased by adjusting the etching time for aluminum wiring. As x, 0.3 to 5 μm was preferable. (Fig. 6 (C))

Then, the photoresists 67a and 67b are peeled off, and a KrF excimer laser (wavelength 248 nm,
A pulse width of 20 nsec) was applied to activate the impurity ions introduced into the active layer. (Fig. 6
(D)) Finally, plasma CVD is performed on the entire surface as an interlayer insulator 69.
A silicon oxide film having a thickness of 2000 Å to 1 μm was formed by the method. Further, contact holes are formed in the source 68a and the drain 68b of the TFT, and the aluminum wiring 70a,
70b was formed to a thickness of 2000Å to 1 μm, for example 5000Å. If, for example, titanium nitride is formed under the aluminum wiring as a barrier metal, the reliability can be further improved (FIG. 6 (E)).

[0037]

According to the present invention, it is possible to improve the yield of thin film semiconductor devices, enhance their reliability, and maximize the characteristics. The thin film semiconductor device of the present invention is particularly preferable as a transistor for controlling pixels in an active matrix circuit of a liquid crystal display because it has a low leak current between a gate and a drain and a leak current between a gate and a source and can withstand a high gate voltage. .

Although the present invention has been described by taking the N-channel type TFT as an example, the P-channel type TFT or the N-channel type TFT on the same substrate.
It goes without saying that the same can be applied to the case of the phase trapping type circuit in which the channel type and the P channel type are mixed. Also, not only the simple structure shown in the embodiment,
For example, a TFT having a structure having silicide in the source / drain as shown in Japanese Patent Application No. 5-256567.
May be used for. The present invention has been described focusing on the TFT. However, it goes without saying that the present invention can also be applied to other circuit elements, for example, a thin film integrated circuit having a plurality of gate electrodes in one island-shaped semiconductor region, a stacked gate type TFT, a diode, a resistor and a capacitor. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

FIG. 1 shows a structural example of a TFT of the present invention.

2A to 2C show cross-sectional views of a manufacturing process of the TFT of Example 1.

3A to 3C show cross-sectional views of a manufacturing process of a TFT of Example 2.

4A to 4C show cross-sectional views of a manufacturing process of a TFT of Example 3.

FIG. 5 shows a configuration example of a conventional TFT.

6A to 6C show cross-sectional views of a manufacturing process of a TFT of Example 4.

[Explanation of symbols]

10 ... Island semiconductor region 11 ... Substrate 12 ... Channel formation region (substantially intrinsic) 13 ... Impurity region (source, drain) 14 ... Doping region (nitrogen, carbon, oxygen) 15 ... Gate insulating film 16 ... Island semiconductor region end 17 ... Gate electrode 18 ... Source / drain electrode

Claims (7)

[Claims] 1. A thin film semiconductor device having an island-shaped thin film semiconductor region and a gate electrode that crosses the semiconductor region, wherein a concentration of at least one element of oxygen, carbon, and nitrogen is provided in a peripheral portion of the semiconductor region. A thin film semiconductor device, wherein a region having a concentration higher than the average concentration of the semiconductor region exists, and a gate electrode crosses the region. 2. The thin film semiconductor device according to claim 1, wherein the island-shaped thin film semiconductor region has a tapered edge. 3. The region according to claim 1, wherein the concentration of at least one element of oxygen, carbon, and nitrogen provided in the peripheral portion of the semiconductor region is larger than the average concentration of the semiconductor region, the width of the region is 0. 05-5 μm, preferably 0.1-1
A thin film semiconductor device having a thickness of μm. 4. A step of forming an island-shaped thin film semiconductor region, and at least one element of oxygen, carbon, and nitrogen is selectively applied to at least a portion of the peripheral portion of the thin film semiconductor region where the gate electrode crosses. A method of manufacturing a thin film semiconductor device, comprising: a step of introducing, a step of forming a gate electrode across the thin film semiconductor area, and an step of introducing an impurity into the thin film semiconductor area to form source and drain areas. 5. A step of forming an island-shaped thin film semiconductor region using a semiconductor material in a substantially amorphous state, and at least one element selected from oxygen, carbon and nitrogen is provided in a peripheral portion of the thin film semiconductor region. A thin film comprising: a step of introducing, a step of irradiating the thin film semiconductor region with a laser or strong light equivalent thereto to crystallize, and a step of forming a gate electrode across the thin film semiconductor region. Manufacturing method of semiconductor device. 6. A step of directly or indirectly forming a mask material on a non-single crystal semiconductor thin film and patterning it in an island shape by a photolithography method, and a step of forming the mask material by a dry etching method or a wet etching method. According to a pattern, a step of etching the semiconductor thin film into islands, and accelerating ions of at least one element of oxygen, carbon, and nitrogen with the mask material left on the island-shaped semiconductor thin film. A method of manufacturing a thin film semiconductor device, comprising: a step of irradiating and a step of forming a gate electrode across the semiconductor thin film. 7. The method for manufacturing a thin film semiconductor device according to claim 6, wherein the island-shaped semiconductor thin film has a tapered edge.