JPS6199347A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6199347A JPS6199347A JP22102884A JP22102884A JPS6199347A JP S6199347 A JPS6199347 A JP S6199347A JP 22102884 A JP22102884 A JP 22102884A JP 22102884 A JP22102884 A JP 22102884A JP S6199347 A JPS6199347 A JP S6199347A
- Authority
- JP
- Japan
- Prior art keywords
- film
- single crystal
- silicon film
- crystal silicon
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は半導体装置の製造方法のうち、特にSOI構造
半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an SOI structure semiconductor device.
半導体集積回路(IC)はLSI、VLSIと二次元(
平面的)領域でwLIII化、高集積化されてきたが、
その微細化にも限度があって、それを更に高集積化する
ための手段として、現在、立体的に積み上げる三次元L
SIが大きくクローズアップしている。Semiconductor integrated circuits (ICs) are LSI, VLSI, and two-dimensional (
WLIII and high integration have been achieved in the planar) area,
There is a limit to miniaturization, and as a means to further increase integration, we are currently using three-dimensional L
SI is getting a big close-up.
このような三次元LSIの基礎となるのが、SOT
(Silicon On In5ulator)構造の
半導体素子であって、それは、絶縁基板上に非単結晶性
半導体層を被着し、ビームアニールして単結晶化し、そ
の単結晶半導体層に素子を形成する方法によって作成さ
れる。The basis of this type of 3D LSI is SOT.
It is a semiconductor device with a (Silicon On In5ulator) structure, which is manufactured by depositing a non-single-crystalline semiconductor layer on an insulating substrate, converting it into a single crystal by beam annealing, and forming a device on the single-crystal semiconductor layer. Created.
そうして、このような半導体素子が絶縁膜を介して多層
に禎み上げられて三次元LSIに形成されるが、且つ、
このSOI構造の半導体素子は、従tの半導体基板上に
形成した半導体素子に比べて、一層高性能化・高集積化
される利点がある。In this way, such a semiconductor element is formed into a three-dimensional LSI by being multilayered through an insulating film, and,
A semiconductor element having this SOI structure has the advantage of higher performance and higher integration than a semiconductor element formed on a conventional semiconductor substrate.
例えば、CMO5素子からなるICを形成する場合、半
導体領域が絶縁膜上にあるために、特性上からはラッチ
アップの心配がなく、更に、チャネルストッパも不要と
なる。チャネルストッパ領域が除去されると、集積度は
一層高められる。For example, when forming an IC consisting of five CMO elements, since the semiconductor region is on an insulating film, there is no need to worry about latch-up in terms of characteristics, and furthermore, there is no need for a channel stopper. If the channel stopper region is removed, the degree of integration is further increased.
しかし、このような単結晶化半導体N(半導体膜)に設
けられる半導体素子は、出来るだけ品質の高い素子であ
ることが要望され、本件はかような半導体素子の高品質
化に関するものである。However, it is desired that the semiconductor element provided in such a single crystal semiconductor N (semiconductor film) be an element of as high quality as possible, and the present case relates to improving the quality of such a semiconductor element.
[従来の技術]
さて、このようなSOI構造の半導体素子としては、一
般にMOSトランジスタが多く、例えばRAMメモリと
して構成されている。[Prior Art] Now, as a semiconductor element having such an SOI structure, a MOS transistor is generally used, and is configured as, for example, a RAM memory.
このSOI構造のMOS)ランジスタ素子について、従
来の形成方法の一例を説明する。第2図(a)ないしく
dlはその工程順断面図であるが、まず、同図(a)に
示すように、シリコン基板1の上に二酸化シリコン(S
iO2)膜2を形成し、その絶縁膜上に多結晶シリコン
膜3°を化学気相成長(CVD)法によって被着し、パ
ターンニングする。An example of a conventional method for forming this SOI structured MOS transistor element will be described. FIGS. 2(a) to dl are cross-sectional views in the order of the process. First, as shown in FIG. 2(a), silicon dioxide (S
An iO2) film 2 is formed, and a polycrystalline silicon film 3° is deposited on the insulating film by chemical vapor deposition (CVD) and patterned.
次いで、第2図中)に示すように、その多結晶シリコン
膜31の上から連続アルゴンレーザ(CW−Ar La
5er)ビームをスキャン(走査)して加熱溶融させ、
多結晶シリコン膜を単結晶シリコン膜3に変成させる。Next, as shown in FIG. 2), a continuous argon laser (CW-Ar La
5er) scan the beam to heat and melt it,
The polycrystalline silicon film is transformed into a single crystalline silicon film 3.
即ち、一定方向よりレーザビーl ムをスキ
ャンして多結晶シリコン膜3′を加熱溶融させ、これを
凝固させると、走査方向に沿って単結晶シリコン膜3が
成長する。That is, when the polycrystalline silicon film 3' is heated and melted by scanning the laser beam in a fixed direction and solidified, the single crystal silicon film 3 grows along the scanning direction.
次いで、第2図(C)に示すように、その単結晶シリコ
ン膜3全面に砒素イオンを注入して単結晶シリコン膜3
をn型とした後、単結晶シリコン膜3の上面を酸化して
、膜厚数100人のゲート絶縁膜4を生成し、その上に
多結晶シリコン膜からなるゲート電極5を形成する。こ
の際、ゲート絶縁膜4は塩酸ガス雰囲気中で約950℃
に加熱し、シリコン膜3を表面酸化して形成する。又、
ゲート電極5は、CVD法を用いて多結晶シリコン膜を
被着し、これをパターンニングして形成する。Next, as shown in FIG. 2(C), arsenic ions are implanted into the entire surface of the single crystal silicon film 3 to form the single crystal silicon film 3.
After making n-type, the upper surface of the single-crystal silicon film 3 is oxidized to form a gate insulating film 4 several hundred thick, and a gate electrode 5 made of a polycrystalline silicon film is formed thereon. At this time, the gate insulating film 4 is heated to approximately 950°C in a hydrochloric acid gas atmosphere.
The silicon film 3 is formed by heating to oxidize the surface thereof. or,
The gate electrode 5 is formed by depositing a polycrystalline silicon film using the CVD method and patterning the film.
次いで、第2図(d)に示すように、上面より硼素イオ
ンを注入してゲート電極5の両側にp型のソース領域、
ドレイン領域6を形成し、更に、燐シリケートガラス(
P S G”)膜7を被着し、これに窓開けしてアルミ
ニウム電極8を接続して、MOSトランジスタが完成さ
れζ。Next, as shown in FIG. 2(d), boron ions are implanted from the top surface to form p-type source regions on both sides of the gate electrode 5.
A drain region 6 is formed, and a phosphorus silicate glass (
A MOS transistor is completed by depositing a PSG film 7, opening a window thereon, and connecting an aluminum electrode 8.
[発明が解決しようとする問題点]
ところで、このような形成方法は既にSOI構
゛造以外の一般なMOS構造でも公知の形成方法であ
り、広く使用されている方法である。しかし、SOI構
造のMOSトランジスタの場合には、表面酸化して生成
するゲート絶縁膜4の膜質が、余り良質ではないと云う
問題がある。[Problems to be solved by the invention] By the way, such a formation method has already been applied to SOI structures.
This is a well-known and widely used method for forming general MOS structures other than the MOS structure. However, in the case of a MOS transistor having an SOI structure, there is a problem in that the quality of the gate insulating film 4 produced by surface oxidation is not very good.
それは、単結晶シリコン膜3が直接レーザビーム照射を
受けて、表面汚染を起こしていることが、原因と考えら
れ、レーザビームで照射すると、シリコン膜が1000
℃以上の高温になって溶融するから、その際、大気中の
酸素やゴミなどが表面に生成中の酸化膜に取り込まれる
。そのため、ゲート耐圧が劣化したり、表面準位が増え
てリーク電流が増加したり、しきい値が変動したりする
問題が起こると推定されている。This is thought to be because the single crystal silicon film 3 is directly irradiated with a laser beam, causing surface contamination.When irradiated with a laser beam, the silicon film 3
As it melts at temperatures exceeding ℃, oxygen and dust from the atmosphere are absorbed into the oxide film that is forming on the surface. Therefore, it is estimated that problems such as gate breakdown voltage deterioration, surface states increasing and leakage current increasing, and threshold voltage fluctuations occur.
本発明は、このような問題点を取り除き、高品質なトラ
ンジスタ素子を形成するSOI構造半導体装置の形成方
法を提案するものである。The present invention proposes a method for forming an SOI structure semiconductor device that eliminates these problems and forms a high-quality transistor element.
[問題点を解決するための手段]
その問題は、非晶質半導体層をビームアニールして単結
晶半導体層に変成し、該単結晶半導体層の表面を酸化し
て半導体酸化膜を生成し、次いで該半導体酸化膜をエツ
チング除去した後、再び前記単結晶半導体層の表面を酸
化して第2の半導体酸化膜を生成し、該第2の半導体酸
化膜を半導体素子の構成部分とする半導体装置の製造方
法によって解決できる。[Means for solving the problem] The problem is solved by beam annealing an amorphous semiconductor layer to transform it into a single crystal semiconductor layer, oxidizing the surface of the single crystal semiconductor layer to generate a semiconductor oxide film, Next, after removing the semiconductor oxide film by etching, the surface of the single crystal semiconductor layer is oxidized again to produce a second semiconductor oxide film, and the second semiconductor oxide film is used as a component of a semiconductor device. This can be solved by the manufacturing method.
[作用]
即ち、ビームアニール(ビーム照射)シ、高温溶融して
汚染させた単結晶半導体層の表面を、一度エッチングし
て除去し、再び酸化して新たな第2の半導体酸化膜を形
成する。そうして、その新しい半導体酸化膜をゲート絶
縁膜などの素子構成部分に使用する。[Operation] That is, the surface of the single crystal semiconductor layer that has been contaminated by beam annealing (beam irradiation) is melted at a high temperature and is once etched and removed, and then oxidized again to form a new second semiconductor oxide film. . The new semiconductor oxide film is then used for device components such as the gate insulating film.
そうすれば、第2の半導体酸化膜は汚染されていないか
ら、半導体素子は高品質化される。In this case, the second semiconductor oxide film is not contaminated, so that the quality of the semiconductor element can be improved.
[実施例] 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.
第1図(a)ないしくf)は本発明にががる形成工程順
断面図を示している。まず、第1図(a)に示すように
、”io2模12が形成されたシリコン基板11の上面
に、モノシランガスを分解して被着するCVD法によっ
て、膜厚4000人の多結晶シリコン膜13′を被着し
、これをパターンニングする。FIGS. 1(a) to 1(f) show sequential cross-sectional views of the forming steps according to the present invention. First, as shown in FIG. 1(a), a polycrystalline silicon film 13 with a thickness of 4000 nm is deposited on the upper surface of the silicon substrate 11 on which the IO2 pattern 12 is formed by CVD method, in which monosilane gas is decomposed and deposited. ′ is deposited and patterned.
次いで、第1図(b)に示すように、連続アルゴンレー
ザビームを走査して、多結晶シリコン膜13゜を加熱溶
融し、単結晶シリコン膜13に変成させる。Next, as shown in FIG. 1(b), a continuous argon laser beam is scanned to heat and melt the polycrystalline silicon film 13° and transform it into a single crystal silicon film 13.
この時、シリコン基板は約450℃に加熱し、レーザア
ニール条件はレーザ出力8〜10W、ビームスポット径
30〜50μmφ、走査速度を10cm/sec程度に
する。At this time, the silicon substrate is heated to about 450° C., and the laser annealing conditions are a laser output of 8 to 10 W, a beam spot diameter of 30 to 50 μmφ, and a scanning speed of about 10 cm/sec.
次いで、第1図(C)に示すように、その単結晶シリコ
ン膜13全面に砒素イオンを注入して単結晶シリコン膜
13をn型とし、次にその単結晶シリコン膜13の表面
を酸化して、膜厚200〜400人の二酸化シリコン(
SiO2)膜14を生成する。生成条件は、例えば温度
950℃に加熱し、高湿酸素ガス。Next, as shown in FIG. 1C, arsenic ions are implanted into the entire surface of the single crystal silicon film 13 to make the single crystal silicon film 13 n-type, and then the surface of the single crystal silicon film 13 is oxidized. The film thickness is 200 to 400 silicon dioxide (
A SiO2) film 14 is produced. The generation conditions are, for example, heating to a temperature of 950°C and high humidity oxygen gas.
または塩酸ガス雰囲気中で酸化する。Or oxidize in a hydrochloric acid gas atmosphere.
次いで、第F図(d)に示すように、上記の5i02膜
14を弗酸液によってエツチング除去する。Next, as shown in FIG. F(d), the 5i02 film 14 is removed by etching with a hydrofluoric acid solution.
次いで、第1図(e)に示すように、再び単結晶シリコ
ン膜13の表面を酸化して、第2の5toz1*からな
るゲート絶縁膜15を生成し、更に、その上にCVD法
を用いて多結晶シリコン膜を被着し、これをパターンニ
ングしてゲート電極16を形成する。Next, as shown in FIG. 1(e), the surface of the single-crystal silicon film 13 is oxidized again to form a second gate insulating film 15 made of 5toz1*, and then a CVD method is applied thereon. Then, a polycrystalline silicon film is deposited and patterned to form a gate electrode 16.
この時、ゲート絶縁膜15の生成には、特に酸素の混入
を少なくするように注意し、例えば高圧塩酸ガス雰囲気
中で、温度950℃の低温度で処理する方法が望ましい
。At this time, for the formation of the gate insulating film 15, it is preferable to take special care to reduce the mixing of oxygen, and to perform the process at a low temperature of 950° C., for example, in a high-pressure hydrochloric acid gas atmosphere.
次いで、第1図(flに示すように、公知の方法によっ
て、硼素イオンを注入してゲート電極16の両側にソー
ス領域、ドレイン領域17を形成し、更にPSG膜18
を被着し、次に、窓開けしてアルミニウム電極19を形
成する。Next, as shown in FIG. 1 (fl), boron ions are implanted by a known method to form a source region and a drain region 17 on both sides of the gate electrode 16, and then a PSG film 18 is formed.
Then, a window is opened to form an aluminum electrode 19.
このようにすれば、汚染されたSiO□膜14が一旦エ
ッチング除去され、膜質の良い第2の5i02膜15が
生成されて、ゲート絶縁膜になる。従って、MOS)ラ
ンジスタのゲート耐圧などの特性は改善され、そのバラ
ツキが減少する。In this way, the contaminated SiO□ film 14 is once removed by etching, and a second 5i02 film 15 of good quality is produced, which becomes a gate insulating film. Therefore, characteristics such as gate breakdown voltage of the MOS transistor are improved and variations thereof are reduced.
[発明の効果]
以上の説明から明らかなように、本発明によればsor
構造半導体素子の製造方法において、高品質な絶縁膜が
形成されるため、半導体素子が高品質化される効果があ
る。[Effect of the invention] As is clear from the above explanation, according to the present invention, sor
In the method for manufacturing a structural semiconductor element, a high quality insulating film is formed, which has the effect of improving the quality of the semiconductor element.
なお、上記例はゲート絶縁膜を用いて説明したが、その
他のトランジスタの絶縁膜にも通用できることは云うま
でもない。Note that although the above example has been explained using a gate insulating film, it goes without saying that the present invention can also be applied to insulating films of other transistors.
第1図(a)〜(f)は本発明にかかる形成方法を説明
するための工程順断面図、
第2図(a)〜(d)は従来のの形成方法を説明するた
めの工程断面図である。゛
図において、
1.11はシリコン基板、2.12は絶縁膜、3’、1
3’は多結晶シリコン膜、
3.13は単結晶シリコン膜、FIGS. 1(a) to (f) are process cross-sectional views for explaining the forming method according to the present invention, and FIGS. 2(a) to (d) are process cross-sectional views for explaining the conventional forming method. It is a diagram. In the figure, 1.11 is a silicon substrate, 2.12 is an insulating film, 3', 1
3' is a polycrystalline silicon film, 3.13 is a single crystal silicon film,
Claims (1)
に変成し、該単結晶半導体層の表面を酸化して半導体酸
化膜を生成し、次いで該半導体酸化膜をエッチング除去
した後、再び前記単結晶半導体層の表面を酸化して第2
の半導体酸化膜を生成し、該第2の半導体酸化膜を半導
体素子の構成部分とすることを特徴とする半導体装置の
製造方法。The amorphous semiconductor layer is beam-annealed to transform it into a single-crystal semiconductor layer, the surface of the single-crystal semiconductor layer is oxidized to produce a semiconductor oxide film, and then the semiconductor oxide film is removed by etching. A second layer is formed by oxidizing the surface of the crystalline semiconductor layer.
1. A method of manufacturing a semiconductor device, comprising: producing a second semiconductor oxide film, and using the second semiconductor oxide film as a component of a semiconductor element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22102884A JPS6199347A (en) | 1984-10-19 | 1984-10-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22102884A JPS6199347A (en) | 1984-10-19 | 1984-10-19 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6199347A true JPS6199347A (en) | 1986-05-17 |
Family
ID=16760351
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22102884A Pending JPS6199347A (en) | 1984-10-19 | 1984-10-19 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6199347A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01287964A (en) * | 1988-05-13 | 1989-11-20 | Seiko Epson Corp | Manufacture of semiconductor device |
JPH02109337A (en) * | 1988-10-18 | 1990-04-23 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH06314698A (en) * | 1993-03-05 | 1994-11-08 | Semiconductor Energy Lab Co Ltd | Thin-film semiconductor device and its manufacture |
JPH06314785A (en) * | 1993-03-05 | 1994-11-08 | Semiconductor Energy Lab Co Ltd | Thin film semiconductor device and its manufacture |
JPH0745518A (en) * | 1993-07-27 | 1995-02-14 | Semiconductor Energy Lab Co Ltd | Forming method of semiconductor device |
US6071764A (en) * | 1993-07-27 | 2000-06-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and process for fabricating the same |
WO2001061760A1 (en) * | 2000-02-15 | 2001-08-23 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing thin-film transistor, and liquid-crystal display |
WO2002025739A1 (en) * | 2000-09-21 | 2002-03-28 | Matsushita Electric Industrial Co.,Ltd. | Thin-film transistor, and liquid crystal display and electroluminescence display which comprise it |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5210681A (en) * | 1975-07-15 | 1977-01-27 | Matsushita Electronics Corp | Method for treating surface of semiconductor substrate |
JPS57208124A (en) * | 1981-06-18 | 1982-12-21 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1984
- 1984-10-19 JP JP22102884A patent/JPS6199347A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5210681A (en) * | 1975-07-15 | 1977-01-27 | Matsushita Electronics Corp | Method for treating surface of semiconductor substrate |
JPS57208124A (en) * | 1981-06-18 | 1982-12-21 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01287964A (en) * | 1988-05-13 | 1989-11-20 | Seiko Epson Corp | Manufacture of semiconductor device |
JPH02109337A (en) * | 1988-10-18 | 1990-04-23 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH06314698A (en) * | 1993-03-05 | 1994-11-08 | Semiconductor Energy Lab Co Ltd | Thin-film semiconductor device and its manufacture |
JPH06314785A (en) * | 1993-03-05 | 1994-11-08 | Semiconductor Energy Lab Co Ltd | Thin film semiconductor device and its manufacture |
US6077758A (en) * | 1993-07-27 | 2000-06-20 | Semiconductor Energy Laboratory Co., Ltd. | Method of crystallizing thin films when manufacturing semiconductor devices |
US6071764A (en) * | 1993-07-27 | 2000-06-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and process for fabricating the same |
JPH0745518A (en) * | 1993-07-27 | 1995-02-14 | Semiconductor Energy Lab Co Ltd | Forming method of semiconductor device |
US6455401B1 (en) | 1993-07-27 | 2002-09-24 | Semiconductor Energy Laboratory Co., Ltd. | Methodology for producing thin film semiconductor devices by crystallizing an amorphous film with crystallization promoting material, patterning the crystallized film, and then increasing the crystallinity with an irradiation |
US6924213B2 (en) | 1993-07-27 | 2005-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and process for fabricating the same |
US7056775B2 (en) | 1993-07-27 | 2006-06-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and process for fabricating the same |
WO2001061760A1 (en) * | 2000-02-15 | 2001-08-23 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing thin-film transistor, and liquid-crystal display |
US6716768B2 (en) | 2000-02-15 | 2004-04-06 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing thin-film transistor, and liquid-crystal display |
WO2002025739A1 (en) * | 2000-09-21 | 2002-03-28 | Matsushita Electric Industrial Co.,Ltd. | Thin-film transistor, and liquid crystal display and electroluminescence display which comprise it |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4204894A (en) | Process for fabrication of semiconductors utilizing selectively etchable diffusion sources in combination with melt-flow techniques | |
JPS6199347A (en) | Manufacture of semiconductor device | |
JPS5921067A (en) | Semiconductor device and manufacture thereof | |
JPS58192381A (en) | Manufacture of mos field effect transistor | |
JP2001102590A (en) | Method for fabrication of semiconductor device | |
JPS5885520A (en) | Manufacture of semiconductor device | |
JP3031398B2 (en) | Method for manufacturing MIS transistor | |
JPS62202559A (en) | Semiconductor device and its manufacture | |
JPS58175844A (en) | Manufacture of semiconductor device | |
JP2939819B2 (en) | Method for manufacturing thin film transistor | |
JPS61166074A (en) | Insulated gate type transistor and manufacture thereof | |
JPS62262431A (en) | Manufacture of semiconductor device | |
JPH02263465A (en) | Lamination type semiconductor device and manufacture thereof | |
JPH0548100A (en) | Manufacture of semiconductor device | |
JPH0746698B2 (en) | Method for manufacturing semiconductor device | |
JPH0684939A (en) | Manufacture of mis field-effect semiconductor device | |
JPH0669430A (en) | Manufacture of semiconductor device | |
JPS59182570A (en) | Semiconductor device | |
JPS59132120A (en) | Manufacture of semiconductor device | |
JPS6229910B2 (en) | ||
JPS6346777A (en) | Semiconductor element and manufacture thereof | |
JPS5893224A (en) | Preparation of semiconductor single crystal film | |
JPS58114422A (en) | Manufacture of substrate for semiconductor device | |
JPS63281418A (en) | Manufacture of semiconductor device | |
JPS58114440A (en) | Manufacture of substrate for semiconductor device |