JPS58114422A - Manufacture of substrate for semiconductor device - Google Patents

Manufacture of substrate for semiconductor device

Info

Publication number
JPS58114422A
JPS58114422A JP20977081A JP20977081A JPS58114422A JP S58114422 A JPS58114422 A JP S58114422A JP 20977081 A JP20977081 A JP 20977081A JP 20977081 A JP20977081 A JP 20977081A JP S58114422 A JPS58114422 A JP S58114422A
Authority
JP
Japan
Prior art keywords
substrate
insulating film
window
film
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20977081A
Other languages
Japanese (ja)
Other versions
JPS6347252B2 (en
Inventor
Haruhisa Mori
森 治久
Junji Sakurai
桜井 潤治
Hajime Kamioka
上岡 元
Seiichiro Kawamura
河村 誠一郎
Motoo Nakano
元雄 中野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20977081A priority Critical patent/JPS58114422A/en
Publication of JPS58114422A publication Critical patent/JPS58114422A/en
Publication of JPS6347252B2 publication Critical patent/JPS6347252B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Abstract

PURPOSE:To obtain a substrate appropriate for an MOSFET, etc. by a method wherein, on a single crystal or a polycrystalline substrate, an insulation film having well curb form windows is formed, a thin insulation film is provided in the window, then a polycrystalline or an amorphous Si film having sufficient thickness is deposited over the entire surface, thereafter a laser is scanned, and thus the window is filled with Si. CONSTITUTION:On the single crystal or the polycrystalline Si substrate 11, the insulation film 12 constituted of SiO2 or Si3N4, etc. is adhered, then is selectively etched, thus a plurality of windows 13 are opened, and accordingly a part of the substrate 11 is exposed. Next, a thin insulation film 14 is provided on the exposed surface, and, over the entire surface including it, the polycrystalline or the amorphous Si film 15 is deposited by a CVD method. Thereat, the thickness of the film 15 is one having an amount enough to fill the window 13 when the fusion flow of Si thereafter. Thereafter, the substrate 11 is allowed to increase the temperature up to approx. 500 deg.C, then, while scanning a laser on the film 15 in this state, it is irradiated resulting in the fusion flow, and thus the window 13 is filled. Thus, after an irradiation spot moves, the Si in the window 13 is solidified, and simultaneously changed into single crystals 16A-16C.

Description

【発明の詳細な説明】 (1)  発明の技術分野 本発明は、半導体装置、より詳しく述べるならば、レー
ず照射によって多結晶シリコンから単結晶シリコンに非
晶質の絶縁膜上にて変光られかつ誘電体分離されている
複数の半導体装音形成領域を有する基板の製造方法に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device, and more specifically, to a method for changing light on an amorphous insulating film from polycrystalline silicon to single crystal silicon by laser irradiation. The present invention relates to a method of manufacturing a substrate having a plurality of semiconductor sound device formation regions which are separated and separated by a dielectric material.

(2)技術の背景 レーず照射によって非晶質又は多結晶の薄膜を単結晶膜
に変え、半導体装置の製造に利用することが研究開発さ
れている(例えば、徳山、車状。
(2) Background of the technology Research and development is underway to convert amorphous or polycrystalline thin films into single-crystalline films by laser irradiation and use them in the manufacture of semiconductor devices (for example, Tokuyama and Kurashira).

宮尾:研究が急速に広がるレーザー・アニール技術2臼
経エレクトロニクス、1979年6月11日号、嬉11
6頁〜第151頁、′によび林 裕久:新しいLSIを
実現する非晶質絶縁膜上の単結晶成長法9日経エレクト
ロニクス、1980年2月18日号、第82頁〜菖90
頁参照)。
Miyao: Laser annealing technology where research is rapidly expanding 2. Electronics, June 11, 1979 issue, Yuki 11
Pages 6 to 151, Hirohisa Nibibayashi: Single crystal growth method on amorphous insulating film to realize new LSI 9 Nikkei Electronics, February 18, 1980 issue, pages 82 to 90
(see page).

(3)  従来技術と問題点 本出願人は、特願昭55−98397号および特願昭5
6−    号(昭和56年9月30日出願)にて、レ
ーず照射によって絶縁体の凹所内に単結晶領域を非単結
晶材料から形成する半導体!!愛用基板の製造方法を提
案し九。
(3) Prior art and problems The applicant has filed Japanese Patent Application No. 55-98397 and Japanese Patent Application No. 5
No. 6- (filed on September 30, 1981), a semiconductor in which a single crystal region is formed from a non-single crystal material in a recess of an insulator by laser irradiation! ! Propose a manufacturing method for your favorite board.9.

特願昭56−     号にて提案した製造方法は次の
ようなものであった。
The manufacturing method proposed in Japanese Patent Application No. 1983 was as follows.

#!1図に示し九ように9台板1 (シリコン、金属、
アルミナ、高純度石英等の板)の上に絶縁層(二酸化シ
リコン)の基板2を形成し、フオトリ1) ソグラフィ技術によってこの基板2を選択エツチングし
て凹所3を形成する。次に、多結晶シリコン膜4を全面
に形成し、必須ではないが燐硅酸ガラス(PEG)層5
をその上に形成する。例えば。
#! As shown in Figure 1, 9 base plates 1 (silicon, metal,
A substrate 2 of an insulating layer (silicon dioxide) is formed on a plate (of alumina, high-purity quartz, etc.), and a recess 3 is formed by selectively etching this substrate 2 using a photolithography technique. Next, a polycrystalline silicon film 4 is formed on the entire surface, and a phosphosilicate glass (PEG) layer 5 is formed, although it is not essential.
is formed on top of it. for example.

基板2の厚さ4 if 1μ肩であり、凹所のサイズけ
30X50μ諷であり、凹所底部の基板2の厚さl。
The thickness of the substrate 2 is 4 if 1μ, the size of the recess is 30×50μ, and the thickness of the substrate 2 at the bottom of the recess is l.

は0.l#菖であり、凹所間の幅t、は5μ島であ勺。is 0. It is an irises, and the width t between the depressions is 5μ islands.

多結晶シリコン膜4の厚さt4は0.5〜1μ簿であp
、および燐硅酸ガラス層の厚さは1μ篇である。
The thickness t4 of the polycrystalline silicon film 4 is 0.5 to 1 μm.
, and the thickness of the phosphosilicate glass layer is 1 μm.

第1図の状態で全体を500℃程度に加熱保持しながら
、連続発振(CW”)レーザを走査させて照射して多結
晶シリコン膜4を溶融し、溶融体が凹所3内に溜まる。
While heating and maintaining the entire structure at about 500° C. in the state shown in FIG. 1, a continuous wave (CW") laser is scanned and irradiated to melt the polycrystalline silicon film 4, and the molten material accumulates in the recess 3.

照射スポットの移動による照射の終了後に溶融体が凹所
内で凝固して単線晶化する。このようにして得られたシ
リコン単結晶領域6A、 6B、 6C(第2図)はI
m!縁層に囲まれており、相互に誘電体分離(アイソレ
ージ謬ン)されている。そして、燐硅酸ガラス層5を除
去すると第2図に示した半導体装置用基板が得られ、シ
リコン単結晶領域6A、6B、6C内に通常の技法にて
半導体装置(バイポーラトランジスタ、MOSFET等
)が作られる。
After the irradiation is completed due to the movement of the irradiation spot, the melt solidifies in the recess and becomes a single line crystal. The silicon single crystal regions 6A, 6B, and 6C (Fig. 2) thus obtained are I
m! They are surrounded by an edge layer and are dielectrically isolated from each other. Then, by removing the phosphosilicate glass layer 5, the semiconductor device substrate shown in FIG. is made.

このようKして製造された半導体装置用基板のシリコン
単結晶領域内にトランジスタ(例えばMOS FET)
を形成するならば、シリコン単結晶基板(ウェハ)に形
成した普通42)MOS FET  よりも動作速度が
早−ものが得られるが、シリコン台板1と形成し九FE
Tのソースおよびドレインとの間の薄い絶縁層があっで
ある程度の寄生容量が生じるために動作速度に限界があ
る。
A transistor (for example, MOS FET) is placed in the silicon single crystal region of the semiconductor device substrate manufactured in this manner.
If formed on a silicon base plate 1, a faster operating speed can be obtained than an ordinary 42) MOS FET formed on a silicon single crystal substrate (wafer).
The thin insulating layer between the source and drain of T causes a certain amount of parasitic capacitance, which limits the operating speed.

(4)  発明の目的 本発明の目的は、上述した従来の半導体装置用基板を改
良して、動作速度がより速くそして消費電力がより少な
いMOS FETを形成することのできる基板を提供す
ることである。
(4) Purpose of the Invention The purpose of the present invention is to improve the above-mentioned conventional substrate for semiconductor devices and to provide a substrate on which a MOS FET can be formed with higher operating speed and lower power consumption. be.

(5)  発明の構成 本発明に係る製造方法は、従来の半導体装置用基板の製
造方法に次のような工程: シリコン単結晶領域および絶縁膜の上に第2絶縁膜を形
成する工程。
(5) Structure of the Invention The manufacturing method according to the present invention includes the following steps in addition to the conventional method for manufacturing a semiconductor device substrate: A step of forming a second insulating film on the silicon single crystal region and the insulating film.

第2絶縁膜の上に第2絶縁膜と同質又は異質の担持層を
形成する工程、および シリコン等の台板(例えば、シリコンサブストレート)
をエツチング除去してシリコン単結晶領域を表出する工
程。
forming a support layer on the second insulating film, which is the same or different from the second insulating film; and a base plate made of silicon or the like (e.g., a silicon substrate).
A process in which the silicon single crystal region is exposed by etching away.

を追加したことを特徴として論る。この表出したシリコ
ン単結晶領域の表出面は従来の表出面とは反対側であり
、この単結晶領域が第2絶縁膜および担持層によって支
持されている。
We will discuss the addition of this as a feature. The exposed surface of this exposed silicon single crystal region is opposite to the conventional exposed surface, and this single crystal region is supported by the second insulating film and the support layer.

(6)発明の実施態様 添付図面を参照して本発明の好壕し込実施態様例によっ
て本発明を説明する。
(6) Embodiments of the Invention The present invention will be described by way of embodiments suitable for trench penetration with reference to the accompanying drawings.

館3図ないし第9図は本発明に係る半導体装置用基板の
製造方法の各工程を説明するための基板の概略断面図お
よび斜視図である。そして、第11図はMOS FET
を第10図の基仮に形成したときの概略断面図である。
Figures 3 to 9 are a schematic cross-sectional view and a perspective view of a substrate for explaining each step of the method for manufacturing a semiconductor device substrate according to the present invention. And, Figure 11 shows the MOS FET
FIG. 10 is a schematic cross-sectional view when the structure is formed based on the base shown in FIG. 10;

第3図に示すように単結晶又は多結晶のシリコンサブス
トレート11の上に二酸化シリコン(又は窒化シリコン
)の絶縁膜12を形成する。絶縁膜12の厚さは2例え
ば、1μ鶏とし、二酸化シリコン膜であればシリコンサ
ブストレートIIC)熱酸化によっであるいは化学的気
相成法(CVD法)によって形成することができ、窒化
シリコン膜であればCVD法によって形成する。
As shown in FIG. 3, an insulating film 12 of silicon dioxide (or silicon nitride) is formed on a single-crystal or polycrystalline silicon substrate 11. The thickness of the insulating film 12 is 2, for example, 1 μm, and if it is a silicon dioxide film, it can be formed on a silicon substrate by thermal oxidation or chemical vapor deposition (CVD method); If it is a film, it is formed by the CVD method.

次に2通常のホトエツチング法によって絶縁膜12を選
択的にエツチングして窓13を開け、シリコンサブスト
レート11の一部を露出させる(第4図)。
Next, the insulating film 12 is selectively etched using a conventional photoetching method to open a window 13 and expose a portion of the silicon substrate 11 (FIG. 4).

この絶縁1112を有するシリコンサブストレート11
を熱酸化又は熱窒化処理等をして、露出部の表面に薄い
絶縁l[14を形成する(第5図)。
Silicon substrate 11 with this insulation 1112
A thin insulating layer 14 is formed on the surface of the exposed portion by thermal oxidation or thermal nitridation treatment (FIG. 5).

又は、第3図の状態よ1絶縁膜12をコントロールエツ
チングして絶縁膜14を残し、第5図の構造を得ても良
い。このときの状態の斜視図が第6図であって、多数の
窓13が絶縁膜12に形成されているわけであり、l1
13の寸法は1例えば20μllX20声藁である。そ
して、薄い絶縁膜14の厚さは1例えば、 0.1μ簾
である。
Alternatively, the structure shown in FIG. 5 may be obtained by performing controlled etching on the first insulating film 12 in the state shown in FIG. 3, leaving the insulating film 14. A perspective view of the state at this time is shown in FIG. 6, and a large number of windows 13 are formed in the insulating film 12.
The dimensions of 13 are, for example, 20 μll x 20 straws. The thickness of the thin insulating film 14 is 1, for example, 0.1 μm.

次に、多結晶(場合によっては非晶質)シリコン膜15
をCVD法によって全表面上に形成する(第7図)。こ
の多結晶シリコン915の厚さは。
Next, a polycrystalline (or amorphous in some cases) silicon film 15
is formed on the entire surface by CVD method (FIG. 7). What is the thickness of this polycrystalline silicon 915?

例えば、0.4μ富である。このシリコン膜15の上に
燐硅酸ガラス膜(例えば、厚さ:IJ1m)  をCV
D法によって形成しても良い(図示せず)。このガラス
膜は熱放散を抑止する働きがあシ、後工楊での単結晶化
の際に有利な温度勾配を形成するのに役立つ。
For example, it is 0.4μ rich. A phosphosilicate glass film (for example, thickness: IJ1m) is deposited on this silicon film 15 by CVD.
It may also be formed by method D (not shown). This glass film acts to suppress heat dissipation and helps create a favorable temperature gradient during single crystallization in the post-processing process.

得られたシリコンサブストレー)11t−、N、tば、
500℃程度に加熱保持しているときに、レーザを走査
照射して多結晶シリコン膜15を溶融する。この照射は
2例えば、連続発振(CW)のアルゴン・レーずで、パ
ワー12W、!)査速210cIM/秒、スポットサイ
ズ50μ簿径の条件で行なう。
Obtained silicon substrate) 11t-, N, tba,
While heating and maintaining the temperature at about 500° C., the polycrystalline silicon film 15 is melted by scanning laser irradiation. This irradiation is carried out using, for example, a continuous wave (CW) argon laser with a power of 12 W! ) The scanning speed was 210 cIM/sec and the spot size was 50 μm.

絶縁膜12上で溶融したシリコンは窓13内へ流れ、照
射スポットが移動したところで窓13内で凝固しく単結
晶化し)、シリコン単結晶領域16A。
The silicon melted on the insulating film 12 flows into the window 13, and when the irradiation spot moves, it solidifies and becomes a single crystal within the window 13), forming a silicon single crystal region 16A.

16B、16C(第8図)が形成される。もし燐硅酸ガ
ラス膜を形成していたならば9次に、エツチング除去す
る。
16B and 16C (FIG. 8) are formed. If a phosphosilicate glass film is formed, it is removed by etching in the ninth step.

従来は、シリコン単結晶領域16A、16B。Conventionally, silicon single crystal regions 16A and 16B are used.

16C内の所定のトランジスタ、拡散抵抗などの回路素
子が公知の工程で作られるわけであるが。
Circuit elements such as predetermined transistors and diffused resistors in the 16C are manufactured using known processes.

本発明によるとそうしe−でこれらシリコン単結晶領域
16A、16B、16Cの上および絶縁膜12の上に化
学的気相成長法(CVD法)又は蒸着法等によって別の
絶縁膜17を形成する(第9図)。
According to the present invention, another insulating film 17 is then formed on these silicon single crystal regions 16A, 16B, 16C and on the insulating film 12 by chemical vapor deposition (CVD) or vapor deposition. (Figure 9).

この別の絶縁II[17Fi二酸化シリコン又は窒化シ
リコンであり、その厚さは1例えば、1カいし2μ罵で
ある。この絶縁膜17の上に担持層18を形成する(第
9図)。この担持層18はその厚さが100Js以上で
あることが望ましく、多結晶シリコンあるいは樹脂であ
ってより0さらには、接着剤とガラス(又はセラミック
)基板でとの担持層18を構成してもよい。
This further insulation II (17Fi) is silicon dioxide or silicon nitride and has a thickness of 1, for example 1 to 2 microns. A support layer 18 is formed on this insulating film 17 (FIG. 9). This support layer 18 preferably has a thickness of 100Js or more, and may be made of polycrystalline silicon or resin.Furthermore, the support layer 18 may be composed of an adhesive and a glass (or ceramic) substrate. good.

次に、  シリコンサブストレート11をエツチング除
去し、さらに、薄し/I絶縁膜14を適切なエツチング
剤でエツチング除去する(第10図)。 このようにし
て、シリコン単結晶領域16A、16B。
Next, the silicon substrate 11 is etched away, and the thin/I insulating film 14 is further etched away using an appropriate etching agent (FIG. 10). In this way, silicon single crystal regions 16A and 16B are formed.

16Cはその底面が別の絶縁膜17によってかつその側
面が絶縁層12によ゛つて囲まれて完全な誘電体分離が
されてシシ、このような単結晶領域を有する半導体装置
用基板が得られる。
16C is surrounded by another insulating film 17 at its bottom and by an insulating layer 12 at its side to achieve complete dielectric isolation, thereby obtaining a semiconductor device substrate having such a single crystal region. .

この半導体装置用基板に公知の工程でMOSFETを形
成した場合を第11図に示す。シリコン単結晶領域16
B (16Aおよび16Cでも同様であるが便宜上との
領域にかぎって説明する)にソース領域およびドレイン
領域21を形成し、単結晶領域表面の絶縁膜22上にゲ
ート23を設け。
FIG. 11 shows a case where a MOSFET is formed on this semiconductor device substrate by a known process. Silicon single crystal region 16
A source region and a drain region 21 are formed in B (the same is true for 16A and 16C, but only the region will be explained for convenience), and a gate 23 is provided on the insulating film 22 on the surface of the single crystal region.

燐硅酸ガラス等の絶縁膜24の窓を通して所定の電極、
すなわち、ソース電極25.ゲート電極26およびドレ
イン電極27を形成することでMOS FETが得られ
る。
Through the window of the insulating film 24 such as phosphosilicate glass, a predetermined electrode is
That is, the source electrode 25. A MOS FET is obtained by forming the gate electrode 26 and the drain electrode 27.

(7)発明の効果 上述したようなシリコン単結晶領域内のMOS FET
では従来の場合のMOS FETよりもその底面での絶
縁膜が非常に厚くソースおよびドレインの寄生容量も/
」・さroしたがって、MOSFETの動作速度は速く
9回路の速度も向上しかつ消費電力の少ない、従来より
も高性能のMOSFETを本%明の製造方法で作られた
半導体装置用基板に形成することができる。
(7) Effects of the invention MOS FET in a silicon single crystal region as described above
The insulating film at the bottom of the MOS FET is much thicker than that of a conventional MOS FET, and the parasitic capacitance of the source and drain is also small.
Therefore, MOSFETs with higher performance than conventional ones, which have faster operating speeds and improved circuit speeds and lower power consumption, can be formed on semiconductor device substrates made using the manufacturing method of this invention. be able to.

【図面の簡単な説明】[Brief explanation of the drawing]

第1FIAおよび第2図は牛導体装置用基板の従来の製
造工程を説明する丸めのこの基板の概略部分断面図であ
り、第3図ないし鮪11図は本発明に係る製造工程を説
明するための半導体装曾用基板の概略部分断面図であり
、第6図は第5図のときの半導体装習用基板の部分斜視
図である。 11  ・・・ シリコン!フストレート12 ・・・
 絶縁膜 13・・・窓 14 ・・・ 薄い絶縁膜 15 ・・・ 多結晶シリコン膜 16A、 16B、 16C・・・シリコン単結晶領域
17 ・・・ 絶縁膜 18 ・・・ 担持層 第1図 第 2図 第3図 第 7図・ 第8図 第9図
1 FIA and FIG. 2 are schematic partial cross-sectional views of a rounded board for explaining the conventional manufacturing process of a board for a conductor device, and FIGS. 3 to 11 are for explaining the manufacturing process according to the present invention. FIG. 6 is a partial perspective view of the semiconductor device substrate shown in FIG. 5. FIG. 11... Silicon! Fast rate 12...
Insulating film 13... Window 14... Thin insulating film 15... Polycrystalline silicon film 16A, 16B, 16C... Silicon single crystal region 17... Insulating film 18... Support layer FIG. Figure 2 Figure 3 Figure 7/ Figure 8 Figure 9

Claims (1)

【特許請求の範囲】 1、下記工程ω〜に): (7)シリコンサブストレート上に厚い第4絶縁膜を形
成する工程。 ←)前記厚Lf−h第1絶縁膜を選択エツチングして所
定の窓部を設け、窓内は落込絶縁膜が基板上にある構造
とする工程。 し) 前記窓を壌めるのに見合った量と(また多結晶シ
リコン膜を全表面上に形成する工程。 に) レー望照射によって前記多結晶シリコンを溶かし
、そのために前記第1絶縁膜上にある部分の多結晶シリ
コンが前記窓内へ流動し、照射波に前記窓内の薄Vk絶
jl&藤の上にシリコン単結晶領域を形成する工程。 を含んでなる誘電体分離されたシリコン単結晶領域・を
有する半導体装置用基板の製造方法において。 前記製造方法がさらに下記工程に)〜(ハ):に)前記
シリコン単結晶領域および絶縁膜の上に第2絶縁膜を形
成する工程。 (ロ)前記第2絶縁膜の上に第2絶縁膜と同質又は異質
の担持層を形成する工程、および(ホ)前記シリコンサ
ブストレートをエツチング除去して、前記シリコン単結
晶領域を表出する工程。 を含んでなることを特徴とする牛導体装蓋用基板の製造
方法。
[Claims] 1. The following steps ω~): (7) A step of forming a thick fourth insulating film on a silicon substrate. ←) A step of selectively etching the first insulating film having a thickness of Lf-h to form a predetermined window portion, and forming a structure in which a depressed insulating film is on the substrate within the window. (b) melting the polycrystalline silicon by laser beam irradiation in an amount appropriate to deepen the window (and forming a polycrystalline silicon film over the entire surface); A step in which the polycrystalline silicon in the portion flowing into the window and forming a silicon single crystal region on the thin Vk layer inside the window by the irradiation wave. In a method of manufacturing a substrate for a semiconductor device having a dielectrically isolated silicon single crystal region comprising: The manufacturing method further includes the following steps) to (c): d) forming a second insulating film on the silicon single crystal region and the insulating film. (b) forming a support layer of the same or different quality as the second insulating film on the second insulating film; and (e) etching away the silicon substrate to expose the silicon single crystal region. Process. A method for manufacturing a substrate for a cow conductor cover, comprising:
JP20977081A 1981-12-28 1981-12-28 Manufacture of substrate for semiconductor device Granted JPS58114422A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20977081A JPS58114422A (en) 1981-12-28 1981-12-28 Manufacture of substrate for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20977081A JPS58114422A (en) 1981-12-28 1981-12-28 Manufacture of substrate for semiconductor device

Publications (2)

Publication Number Publication Date
JPS58114422A true JPS58114422A (en) 1983-07-07
JPS6347252B2 JPS6347252B2 (en) 1988-09-21

Family

ID=16578317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20977081A Granted JPS58114422A (en) 1981-12-28 1981-12-28 Manufacture of substrate for semiconductor device

Country Status (1)

Country Link
JP (1) JPS58114422A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5079183A (en) * 1983-07-15 1992-01-07 Kabushiki Kaisha Toshiba C-mos device and a process for manufacturing the same
US5401683A (en) * 1987-12-04 1995-03-28 Agency Of Industrial Science And Technology Method of manufacturing a multi-layered semiconductor substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5079183A (en) * 1983-07-15 1992-01-07 Kabushiki Kaisha Toshiba C-mos device and a process for manufacturing the same
US5401683A (en) * 1987-12-04 1995-03-28 Agency Of Industrial Science And Technology Method of manufacturing a multi-layered semiconductor substrate

Also Published As

Publication number Publication date
JPS6347252B2 (en) 1988-09-21

Similar Documents

Publication Publication Date Title
US6919238B2 (en) Silicon on insulator (SOI) transistor and methods of fabrication
US4725561A (en) Process for the production of mutually electrically insulated monocrystalline silicon islands using laser recrystallization
US5310446A (en) Method for producing semiconductor film
KR101169058B1 (en) Thin film transistor and fabrication method of the same
JPS59195871A (en) Manufacture of metal oxide semiconductor field-effect transistor
JPH10223495A (en) Semiconductor device having flexible structure and manufacture thereof
US5116768A (en) Fabrication method of a semiconductor integrated circuit having an SOI device and a bulk semiconductor device on a common semiconductor substrate
JPS58114422A (en) Manufacture of substrate for semiconductor device
JPS6199347A (en) Manufacture of semiconductor device
JPS6347253B2 (en)
JPH0223027B2 (en)
JP5231772B2 (en) Method for manufacturing transmissive liquid crystal display element substrate
JPH0335822B2 (en)
JPS5893224A (en) Preparation of semiconductor single crystal film
JPS62203364A (en) Manufacture of semiconductor device
JP2857480B2 (en) Method for manufacturing semiconductor film
JPS6229910B2 (en)
KR100219574B1 (en) Manufacturing method of mono-crystalline semiconductive film
JPH0793259B2 (en) Method for manufacturing semiconductor thin film crystal layer
JPS61117821A (en) Manufacture of semiconductor device
JPS60189218A (en) Manufacture of semiconductor integrated circuit substrate
JPS59158515A (en) Manufacture of semiconductor device
JP2003309068A (en) Semiconductor film and forming method therefor, and semiconductor device and manufacturing method therefor
JPH04299859A (en) Manufacture of semiconductor device
JPS5880830A (en) Manufacture of substrate for semiconductor device