JP3325945B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor (T
FT) and a method of manufacturing the same. The thin film transistor manufactured by the present invention is formed on an insulating substrate such as glass and a semiconductor substrate such as single crystal silicon.

[0002]

2. Description of the Related Art Conventionally, a thin film transistor is formed by patterning a thin film semiconductor region (active layer) into an island shape, forming an insulating film as a gate insulating film by a CVD method or a sputtering method, and forming a gate insulating film thereon. An electrode was formed.

[0003]

An insulating film formed by a CVD method or a sputtering method has poor step coverage (step coverage) and adversely affects reliability, yield, and characteristics. FIG. 3 is a top view of a typical conventional TFT,
And a cross-sectional view along AA ′ and BB ′ of the drawing. The TFT is formed on a substrate 31, and the thin film semiconductor region is located below an impurity region (source / drain region, here, N-type conductivity type) 33 and a gate electrode 37, and is substantially an intrinsic channel forming region. The gate insulating film 35 is provided to cover the semiconductor region. In the impurity region 33, a contact hole is opened through an interlayer insulator 39, and an electrode / wiring 38 is provided.

[0004] As can be seen from the figure, the coverage of the gate insulating film 35 at the end of the semiconductor region is extremely poor, and typically there is only half the thickness of the flat portion. Generally, it is severe when the island-shaped semiconductor region is thick. In particular, it can be seen from the AA 'cross section along the gate electrode that such a deterioration in the covering property has an adverse effect on the characteristics, reliability, and yield of the TFT. That is, focusing on the region 36 indicated by the dotted circle in the AA 'cross-sectional view of FIG. 5, the electric field of the gate electrode 37 is applied intensively to the end of the thin film semiconductor region. That is, since the thickness of the gate insulating film is half that of the flat portion in this portion, the electric field intensity is doubled.

As a result, the gate insulating film in the region 36 is easily broken by a long-time or high voltage application. If the signal applied to the gate electrode is positive, the semiconductor in this region 36 is also N-type, so that the gate electrode 37 and the impurity region 38 (especially, the drain region) conduct, causing a decrease in reliability. Become.

When the gate insulating film is broken,
Some charge is trapped, for example,
If the negative charge is trapped, the semiconductor in the region 36 becomes N-type, regardless of the voltage applied to the gate electrode, and the two impurity regions 38 become conductive, thereby deteriorating the characteristics. In addition, in order to use a TFT without causing the above-described deterioration, only half the voltage in an ideal case can be applied, and the performance cannot be fully utilized.

The presence of such a weak portion in a portion of the TFT means that the TFT is easily destroyed due to charging or the like in a manufacturing process, which is a major factor in lowering the yield. An object of the present invention is to solve such a problem.

[0008]

The present invention is characterized in that the semiconductor in such an electrically weak region is supplemented by using an intrinsic semiconductor having a high resistance or the same conductivity type as that of a channel forming region. FIG. 1 shows a typical structure of the present invention.
Shown in As shown in FIG. 1A, in the present invention, in the vicinity of a portion where the gate electrode 11 traverses at the end of the island-shaped semiconductor region, a portion which is regarded as an impurity region (source, drain) in the conventional TFT is used. A region 14 of the same conductivity type as the intrinsic region or the channel formation region was provided. That is,
In the TFT of the present invention, the portion of the island-shaped semiconductor region that is not covered with the gate electrode is replaced with the impurity regions (source and drain) 13 doped with impurities.
There is a region 14 of substantially the same conductivity type as the intrinsic region or the channel formation region.

FIG. 1B shows another example of the present invention. The substantial structure is the same as that of FIG. 1A except that the shape of the island-shaped semiconductor region is different. In the figure, reference numeral 16 denotes an electrode connected to the source and the drain.

The effect of the provision of the region of the same conductivity type as the intrinsic region 14 or the channel formation region is described with reference to FIG. FIG. 4A shows a structure and an equivalent circuit of a conventional TFT. In the figure, X and Y are portions where the gate electrode crosses the island-shaped semiconductor region, and the gate insulating film in this portion is thinner than the flat portion as described above.
Therefore, as shown in the equivalent circuit, a parasitic TFT having a lower threshold voltage and lower breakdown voltage than the original TFT is formed.

If an excessive voltage is applied to the gate, the parasitic TFT is destroyed before the original TFT is destroyed.
The leakage current between the drains or between the source and the gate increases.

On the other hand, the present invention has a structure and an equivalent circuit as shown in FIG. In the present invention, the parasitic TF
T, X, and Y are formed as in the conventional case.
However, in the present invention, since a part of the island-shaped semiconductor region is an intrinsic semiconductor region, the resistance is high. This resistance R is inserted in series with the parasitic TFT, and the source and drain voltages are not directly applied to the parasitic TFT. Structure. Also,
When a region of the same conductivity type as the channel formation region is provided, the conductivity type is opposite to that of the source and the drain.
The PN junction forms a barrier equivalent to a resistor.

Therefore, even when an excessive voltage is applied to the gate electrode, the voltage is reduced by the above-described resistor inserted in series with the source and drain of the parasitic resistor, and the parasitic TFT is not destroyed. As a result, the reliability degradation, the yield, and the characteristic degradation, which are problems in the conventional TFT, are solved.

The steps for implementing the present invention are shown in FIGS.
This will be described briefly using (H). First, an island-shaped semiconductor region 10 is formed on a substrate. Normally, this semiconductor region is substantially intrinsic, but may be weak N-type or P-type. (Fig. 1 (C))

After the formation of the gate insulating film, FIG.
A gate electrode 11 is provided as shown in FIG. afterwards,
As shown by 12 in FIG. 1E, impurities are implanted. As a result, as shown in FIG. 1F, an impurity region 13 and a region 14 sandwiched between the impurity region and the gate electrode are formed. The region 14 is preferably a region indicated by a dimension of 2 to 5 μm. The conductivity type of this region is the same as the conductivity type of the island-shaped semiconductor. If the island-shaped semiconductor is intrinsic, this region 14 is also intrinsic, and the typical resistivity is 10 ⁶ Ωcm or more.

FIG. 1 (G) shows the T shown in FIG. 1 (F).
The state where the gate electrode of FT is removed is shown. As is clear from this figure, the conductivity type of the channel forming region 15 is the same as that of the region 14 shown in FIG. Finally, an electrode 16 is formed on the source and the drain to complete the TFT. (Figure 1
(H))

In the present invention, for example, either an N-channel type or a P-channel type TFT is provided on a substrate.
In the case of forming only one, the number of photolithography steps is increased by one, but this does not pose any obstacle in view of the improvement in characteristics, reliability and yield obtained by the present invention.

Further, when the present invention is applied to a complementary circuit (CMOS circuit) in which N-channel and P-channel TFTs are mixed, the effect becomes more apparent. In a CMOS circuit, the simplest manufacturing method is the reverse of simply introducing an N-type or P-type impurity over the entire surface of a substrate, then masking a necessary portion and canceling out the impurity introduced earlier. This is for introducing conductivity type impurities. This method is temporarily referred to as a first method. However, in the first method, for example, while the N-type region has a dose of 1 × 10 ¹⁵ cm ⁻² , the P-type region requires a dose of 5 × 10 ¹⁵ cm ^−2. In some cases, the N-channel TFT and the P-channel TFT cannot be balanced in terms of threshold value and the like.

However, a reliable method is to mask first to introduce N-type or P-type impurities, and then to mask again to introduce impurities of the opposite conductivity type to the previous impurities. . This method is called a second method. In this case, since the concentrations of the N-type impurity and the P-type impurity can be set completely independently, ideal characteristics can be expected as a CMOS circuit. However, in this case, one photolithography step is added as compared with the first method.

According to the present invention, in a CMOS circuit, an N-type, P-type
If it is to be applied to both TFTs, N-type impurities and P-type impurities must be separately masked and introduced. Therefore, the second of the above two methods is adopted. Although the second method complicates the manufacturing process, the obtained characteristics are excellent as described above. Since the effect of the present invention can be obtained in addition to the effect, the disadvantage of adding one photolithography step is completely canceled. Hereinafter, an example will be described with respect to a case where the present invention is practiced particularly in manufacturing a CMOS circuit.

[0021]

FIG. 2 is a sectional view showing a manufacturing process of this embodiment.
A 200 nm thick silicon oxide base film 21 was formed on a substrate (Corning 7059) 20 by sputtering. Further, by plasma CVD, a thickness of 50 to 1
An amorphous silicon film of 50 nm , for example, 150 nm was deposited. Subsequently, a silicon oxide film having a thickness of 20 nm was deposited as a protective film by a sputtering method. Then, this was annealed at 600 ° C. for 48 hours in a reducing atmosphere to be crystallized. The crystallization step may be a method using strong light such as a laser. Then, the obtained crystalline silicon film was patterned to form island-shaped silicon regions 22P and 22N.

Next, a thickness of 10
A 0 nm silicon oxide film 23 is deposited as a gate insulating film,
Subsequently, a thickness of 600 to 80 is applied by a low pressure CVD method.
0 nm , for example, a 600 nm silicon film (0.01 to 2 nm ).
% Phosphorus). It is desirable that the step of forming the silicon oxide and the silicon film be performed continuously.
Then, the silicon film is patterned to form a gate electrode 2.
4P and 24N were formed. (Fig. 2 (A))

Next, the semiconductor region 22P is masked with a photoresist 25N, and is subjected to a plasma doping method.
Impurity (phosphorus) was implanted into the silicon region 22N using the wiring 24N as a mask. As a material of the mask 25, a metal material such as chromium, titanium, titanium nitride, and aluminum, or a metal nitride material can also be used. The doping pattern was shaped as shown in FIG. Phosphine (PH ₃ ) was used as the doping gas, and the acceleration voltage was 60 to 90 kV, for example, 80 kV. The dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 1 × 10 ^{15
It was 15} cm ^-2 . As a result, an N-type impurity region 26N was formed. After doping, resist mask 25N
Was removed by an ashing step in an oxygen atmosphere. Typical ashing conditions are 1 Torr, RF
The power was 300 W.

In the case where activation is performed later by a laser, before the resist mask is removed, the silicon oxide 2 on the silicon region 22N is removed with hydrofluoric acid.
3 may be selectively removed. This is effective in preventing irregularities on the surface due to the reaction between the silicon oxide 23 and the silicon region 22N during laser irradiation. (FIG. 2 (B))

Further, this time, an impurity (boron) was implanted into the silicon region 22P by using the wiring 24P as a mask by plasma doping with the semiconductor region 22N being masked with a photoresist 25P. Also in this case, the doping pattern was shaped as shown in FIG. As the doping gas, diborane (B ₂ H _6), the accelerating voltage 20～70KV, for example, 65 kV. The dose was 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 1 × 10 ¹⁵ cm ⁻² . As a result, a P-type impurity region 26P was formed. After doping, resist mask 2
5P was removed by the ashing process. (Figure 2
(C))

Thereafter, annealing was performed at 600 ° C. for 48 hours in a reducing atmosphere to activate the impurities.
This step may be performed by laser annealing. In that case, a KrF excimer laser (wavelength 248 nm), a XeF excimer laser (wavelength 353 nm), a XeCl excimer laser (wavelength 308 nm), an ArF excimer laser (wavelength 193 nm), or the like is used as a laser.
200 to 350 mJ / cm ² , for example, 250 mJ / cm
^It is sufficient to irradiate 2 to 10 shots, for example, 2 shots per one place. During laser irradiation, the substrate
You may heat to about 450 degreeC. It should be noted that the optimal laser energy density changes when the substrate is heated.

[0027] After activation of impurities, followed by, thickness 30 0
A 1000 nm , for example, 600 nm , silicon oxide film 27 is formed as an interlayer insulator by a plasma CVD method, a contact hole is formed in the silicon oxide film 27, and a wiring 28P is formed by a metal material, for example, a multilayer film of titanium nitride and aluminum.
28N was formed. Through the above steps, a CMOS semiconductor circuit was completed. (FIG. 2 (D))

[0028]

According to the present invention, it is possible to improve the yield of TFTs, increase the reliability thereof, and extract the maximum characteristics. In addition, in obtaining such a great effect, there is a great advantage that the method can be implemented without particularly large process change, investment, and technological development. In the present invention, a TFT on an insulating substrate has been described as an example.
Needless to say, the present invention can be applied to a TFT formed on a single crystal semiconductor substrate. As described above, the present invention is an industrially useful invention.

[Brief description of the drawings]

FIG. 1 shows a conceptual diagram of a structure and a manufacturing method of a TFT of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a TFT according to an example.

FIG. 3 shows a configuration example of a conventional TFT.

FIG. 4 illustrates electrical characteristics of the present invention and a conventional TFT.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Island-shaped semiconductor area 11 ... Gate electrode 12 ... Impurity introduction area 13 ... Impurity area (source, drain) 14 ... Area where impurity was not introduced 15 ... Channel formation area 16 Source electrode, drain electrode

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Claims (2)

(57) [Claims] An island-shaped thin film semiconductor is formed, an insulating film is formed on the island-shaped thin film semiconductor, a gate electrode is formed on the insulating film, and an end of the island-shaped thin film semiconductor and In contact with the end of the gate electrode, and masking at least a part of the region without the gate electrode above the island-shaped thin film semiconductor, introducing an impurity into the island-shaped thin film semiconductor, and after introducing the impurity, The mask is used to remove the insulating film.
And irradiating with a laser . 2. The thin film transistor according to claim 1, wherein said insulating film is removed by hydrofluoric acid.
How to make a transistor.