JP4727647B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a structure of a thin film element using a thin film semiconductor, particularly a thin film transistor (hereinafter abbreviated as TFT). The present invention also relates to a configuration of a semiconductor device such as an electro-optical device or a semiconductor circuit including the thin film transistor.

  In recent years, with the spread of liquid crystal displays (LCDs), there has been a demand for higher performance of active matrix liquid crystal display devices (hereinafter abbreviated as AMLCDs). However, various problems have been raised in demanding higher performance.

  One improvement in performance is an increase in operating speed. It is known that as the operating speed increases, the self-heating (self-heating) of the TFT increases accordingly. This is also a problem with ICs.

  In particular, in a circuit composed of TFTs having a very large channel width (W), such as driver circuits (buffers, analog switches, etc.) that require a large current to flow, the self-heating of each TFT is large, and the temperature of the entire circuit Becomes abnormally high. There is also a report that the temperature rises to several hundred degrees Celsius in some cases.

  Such self-heating causes changes in characteristics and deterioration of the TFT, making it difficult to realize a highly reliable product. Therefore, conventionally, the following technique has been disclosed in order to suppress self-heating of a TFT having a large channel width.

  2A is an enlarged schematic view of the TFT active layer (thin film semiconductor layer), FIG. 2A is a top view, and FIGS. 2B, 2C, and 2D are diagrams. It is sectional drawing which cut | disconnected 2 (A) by AA ', BB', and CC '.

  In FIG. 2A, 201 is a substrate having an insulating surface, and 202 and 203 are a pair of impurity regions formed by adding N-type or P-type impurities to an active layer made of a semiconductor thin film. Note that the pair of impurity regions 202 and 203 functions as a source region or a drain region.

  The pair of impurity regions 202 and 203 are formed in a self-aligned manner using the gate electrode 204 as a mask. At that time, no impurity is added under the gate electrode 204, and a channel formation region 205 is formed (FIGS. 2B and 2D).

  At this time, the conventional example shown in FIG. 2 is characterized in that an opening 206 is provided inside the active layer when the active layer is patterned, and the channel formation region is divided into a plurality of parts. In other words, the channel formation region is divided into a plurality, and a plurality of TFTs are substantially arranged in parallel.

  The opening 206 functions as a heat sink for releasing Joule heat generated in the channel formation region 205. That is, a technique has been proposed in which the Joule heat generated by the self-heating of the channel formation region is efficiently released, thereby suppressing the heat generation amount of the TFT and ensuring the reliability.

  In the conventional technique having the configuration as shown in FIG. 2, the region used as the heat sink is configured by the gate insulating film 207. That is, since the opening 206 is covered with the gate insulating film 207, the plurality of channel formation regions 205 are insulated and separated by the gate insulating film 207.

  Therefore, the Joule heat generated in the channel formation region 205 is released to the gate insulating film (typically a silicon oxide film) 207. However, since the thermal conductivity of silicon oxide (about 1.4 W / mK) is about two orders of magnitude smaller than that of silicon (silicon) (about 150 W / mK), the efficiency of heat release is not so high. . Therefore, there is a problem that a high heat dissipation effect cannot be obtained.

  Accordingly, an object of the present invention is to manufacture a TFT provided with a heat sink having a higher heat release effect than the above prior art, and to realize a highly reliable semiconductor device.

The configuration of the invention disclosed in this specification is as follows.
A semiconductor device comprising a semiconductor circuit formed of a plurality of thin film transistors having a thin film semiconductor as an active layer,
The active layer includes a pair of impurity regions exhibiting N-type or P-type and an intrinsic or substantially intrinsic region sandwiched between the pair of impurity regions,
The intrinsic or substantially intrinsic region includes a first region and a second region provided so as to protrude from the first region, and only the first region overlaps the gate electrode. And

  The present invention is characterized in that, in the above-described configuration, the first region is formed in a self-aligned manner using a gate electrode as a mask, and the second region is intentionally formed by photolithography.

In addition, the configuration of other inventions is as follows:
A semiconductor device comprising a semiconductor circuit formed of a plurality of thin film transistors having a thin film semiconductor as an active layer,
The active layer includes a pair of impurity regions exhibiting N-type or P-type and an intrinsic or substantially intrinsic region sandwiched between the pair of impurity regions,
The intrinsic or substantially intrinsic region is formed in a skewer shape having a trunk part substantially perpendicular to the channel direction and a branch part substantially parallel to the channel direction, and only the trunk part overlaps the gate electrode.

  Note that in the above two structures, silicon (silicon) or a compound semiconductor containing silicon can be used as the thin film semiconductor.

In addition, the configuration of other inventions is as follows:
Forming an active layer by patterning a thin film semiconductor; and
Forming a gate electrode above the active layer via an insulating film;
Forming one or more island mask patterns intersecting the gate electrode and perpendicular to the longitudinal direction of the gate electrode;
Adding an N-type or P-type impurity in the active layer using the gate electrode and mask pattern as a mask;
It is characterized by including.

In addition, the configuration of other inventions is as follows:
Forming a gate electrode;
Forming an active layer made of a thin film semiconductor over an insulating film above the gate electrode;
Forming a skewer-shaped insulating film pattern above the active layer;
Adding an N-type or P-type impurity in the active layer using the insulating film pattern as a mask;
It is characterized by including.

  Note that, in the above structure, the pair of impurity regions formed by the N-type or P-type impurity addition step has a comb-tooth shape, and the portions corresponding to the teeth are arranged facing each other. In other words, a skewer-shaped intrinsic or substantially intrinsic region is formed under the region where the mask is provided in the N-type or P-type impurity addition step.

  The configuration of the present invention having the above-described configuration will be described in detail in the embodiments described below.

  By utilizing the present invention, an effective heat dissipation measure is taken against the generation of Joule heat accompanying the TFT operation, and thermal deterioration of the TFT caused by heat accumulation can be prevented. As a result, a highly reliable circuit resistant to self-heating and a highly reliable electronic device including such a circuit can be realized.

  An embodiment of the present invention will be described with reference to FIG. FIG. 1A shows a top view of an active layer using the present invention, and FIGS. 1B, 1C, and 1D respectively show FIG. 1A as AA ′ and BB ′. FIG.

  In FIG. 1A, reference numeral 101 denotes a substrate having an insulating surface, and reference numerals 102 and 103 denote a pair of impurity regions (source or source) formed by adding N-type or P-type impurities to an active layer made of a semiconductor thin film. Drain region).

  An intrinsic or substantially intrinsic semiconductor region 104 is formed between the pair of impurity regions 102 and 103. Note that an intrinsic semiconductor region means a completely neutral semiconductor region to which an impurity exhibiting one conductivity is not added at all.

In addition, a substantially intrinsic semiconductor region means a range in which threshold voltage can be controlled (impurity concentration of N-type or P-type is 1 × 10 ¹⁷ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ or less) means a region exhibiting N-type or P-type or a region intentionally canceling the conductivity type.

  Only this intrinsic or substantially intrinsic region 104 is shown in FIG. As shown in FIG. 3, the region 104 includes a trunk portion (hereinafter referred to as a first region) 104a substantially perpendicular to the channel direction and a branch portion (hereinafter referred to as a second region) 104b substantially parallel to the channel direction. The pair of impurity regions 102 and 103 are comb-shaped.

  In addition, the first region 104a is a region existing directly below the gate electrode 105 through the gate insulating film 106 in FIG. 1A, and the gate electrode is used as a mask when forming the source / drain regions. It is formed consistently.

  On the other hand, the second region 104b is provided so as to protrude from the first region 104a (preferably substantially vertically), and is intentionally formed by photolithography.

  Further, as apparent from FIG. 1A, since the arrangement is such that only the first region 104a overlaps the gate electrode 105, the channel region formed during the TFT operation is formed only in the first region 104a. Is done. In that sense, the first region 104a can also be referred to as a channel formation region.

  On the other hand, since the second region 104b does not overlap with the gate electrode 105, it is always an intrinsic or substantially intrinsic semiconductor region. That is, since only this portion has a high resistance, it does not function as a source / drain and a channel is not formed.

  Instead, in the present invention, the second region 104b has a role as a heat sink for releasing Joule heat generated in the channel formation region and a role for substantially dividing the channel formation region into a plurality of regions.

  That is, by providing the second region 104b, the channel formation region is divided into a plurality of parts, and Joule heat generated in each channel formation region is released to the second region (as a result, a gate electrode or a source / drain electrode) To escape). As a result, it is possible to effectively prevent the accumulation of Joule heat in the active layer (especially easy to accumulate near the center).

  In the conventional example, a case where an opening is provided in the active layer to radiate heat is taken as an example. However, in that case, the difference in thermal conductivity is too large to obtain an efficient heat radiating effect. In that respect, in the configuration of the present invention, since the heat sink is formed of the same semiconductor layer as the channel formation region, the difference in thermal conductivity is negligible, and heat dissipation is performed very efficiently.

  Here, the channel length and the channel width are defined with reference to FIG. FIG. 4 is a view focusing on the active layer shown in FIG.

  In this specification, the shortest distance (corresponding to the gate electrode width) connecting the pair of impurity regions 102 and 103 in FIG. 4 is defined as the channel length (L) (the direction along this channel length is defined as the channel direction). Call). Further, the width of the channel formation region in the direction perpendicular thereto is defined as the channel width (W).

  By the way, since a channel is formed directly below the gate electrode, the channel formation region becomes the first region (trunk) 104a. Therefore, based on the above definition, the channel length (considered as a carrier movement path) has a channel length of L and a channel width of W.

  However, in practice, carriers are preferentially moved in a region where the pair of impurity regions 102 and 103 are closest to each other, so that an effective channel region that works effectively is a region 401 surrounded by a dotted line. That is, it can be said that the channel formation region sandwiched between the branch portions 104b functioning as a heat sink hardly contributes to the movement of carriers and functions mainly as a part of the heat sink.

  Therefore, although the channel width is W when considered as a channel formation region, the effective channel width (the channel width that actually contributes to carrier movement) is expressed as the sum of the channel widths of the effective channel region 401.

  As described above, the TFT using the present invention has a skew-shaped intrinsic or substantially intrinsic region in the active layer, and a part of the TFT is used as a channel formation region contributing to carrier movement. It is characterized in that it is used as a heat sink that releases Joule heat generated by other parts.

  The most important point is that the region used as the heat sink is formed of the same semiconductor layer as the channel formation region, and the heat dissipation effect is improved by eliminating the difference in thermal conductivity.

  Next, specific examples for carrying out the present invention will be described below.

  A manufacturing process of a TFT using the present invention will be described with reference to FIGS. In addition, in FIG. 5, the cross section seen from two cut ends is demonstrated. That is, FIGS. 5 (A) to 5 (E) are cut lines obtained by cutting FIG. 1 (A) along BB ′, and FIGS. 5 (A ′) to 5 (E ′) are FIGS. It is a cut with '.

  5A and 5A, reference numeral 501 denotes a substrate having an insulating surface, and a glass substrate provided with a base film, a silicon substrate, a glass ceramic substrate, or the like can be used. Further, if the substrate is a quartz substrate, a base film may not be provided.

  Next, an active layer 502 made of a crystalline silicon film is formed on the substrate 501. As the crystalline silicon film, either a single crystal thin film or a polycrystalline thin film can be used. If a single crystal thin film is used, a known SOI substrate such as SIMOX or UNIBOND may be used.

If a polycrystalline thin film is used, it may be a film produced by any process as long as it is a polycrystalline thin film obtained by a known means. Usually, the amorphous silicon film is crystallized by laser processing or furnace annealing. In addition to the silicon film, a compound semiconductor containing silicon as represented by Si _x Ge _1-x (0 <X <1) may be used.

  Next, a gate insulating film 503 having a thickness of 120 nm is formed so as to cover the active layer 502, and a gate electrode 504 is formed thereon using a metal film or a conductive silicon film. (FIGS. 5B and 5B)

  After the gate electrode 504 is formed, one or more resist masks 505 are formed so as to intersect the gate electrode 504 at right angles to the longitudinal direction of the gate electrode 504 (substantially parallel to the channel direction). The resist mask 505 is arranged in an island pattern.

  Then, in this state, an impurity exhibiting N-type or P-type is added into the active layer 502 using the gate electrode 504 and the resist mask 505 as a mask to form a pair of impurity regions 506 and 507. Note that phosphorus or arsenic may be added for N-type, and boron for P-type.

  At this time, as shown in FIG. 5C, an intrinsic or substantially intrinsic region 508 having a width wider than that of the gate electrode is formed in the portion where the resist mask 505 is intentionally provided. On the other hand, as shown in FIG. 5C ', in a portion where the resist mask 505 is not disposed, an intrinsic or substantially intrinsic region 508 is formed in a self-aligning manner using only the gate electrode 504 as a mask.

  Note that in the intrinsic or substantially intrinsic region 508 shown in FIG. 5C, the region immediately below the gate electrode is the first region (trunk portion), and the other regions are the second region (branch portion). Become. Then, substantially all of the region 508 that can be seen at the cut end functions as a heat sink.

  In addition, an intrinsic or substantially intrinsic region 508 illustrated in FIG. 5C ′ is a first region, and all functions as an effective channel region.

  After the pair of impurity regions (source / drain regions) and the skew-shaped intrinsic or substantially intrinsic semiconductor region are thus formed, the impurity is activated and the interlayer insulating film 509 is formed. (FIGS. 5D and 5D)

  Next, contact holes are opened to form source or drain electrodes 510 and 511, and finally hydrogenation is performed to complete a TFT having a structure as shown in FIGS.

  It is to be noted that the most important thing in this embodiment is to use an active layer having the structure as described with reference to FIG. 1, and the other structures and structures are not limited to this embodiment. .

  Therefore, if the structure of the active layer shown in the present invention is implemented, the present invention can be sufficiently applied to TFTs having other structures and TFTs manufactured by other manufacturing methods.

  For example, even if the structure is such that a low-concentration impurity region (LDD region) or an offset region is provided between the source / drain region and the channel formation region, the basic configuration does not change, which hinders the implementation of the present invention. Must not.

  In the first embodiment, an N-type TFT (NTFT) or a P-type TFT (PTFT) has been described. However, it is effective to form a CMOS circuit by combining them in a complementary manner. In particular, in an active matrix LCD, it is desirable that the driver circuit and other signal processing circuits are composed of CMOS circuits.

  Since the effect of the present invention can be obtained in the same way for both NTFT and PTFT, it is possible to realize a highly reliable semiconductor circuit by applying it to a semiconductor circuit composed of a CMOS circuit.

  In addition, it is possible to use only NTFT or only PTFT, and they can be combined freely according to the use as a circuit.

  Furthermore, in an active matrix LCD, a plurality of circuits are formed on the same substrate, but not all have Joule heat as a problem. Actually, circuits (buffer circuit, analog switch circuit, level shifter circuit, etc.) that need to pass a large current are greatly affected by Joule heat.

  Therefore, a configuration in which the present invention is applied only to a circuit that needs to pass such a serious large current (is likely to generate Joule heat) may be adopted.

  In the first and second embodiments, an example in which the present invention is applied to a top gate type TFT (typically a planar type TFT) is shown. However, the present invention is applied to a bottom gate type TFT (typically an inverted stagger type TFT). It is also possible.

  An example in which the present invention is applied to an inverted stagger type TFT will be described with reference to FIG. 6A shows a top view of an active layer using the present invention, and FIGS. 6B, 6C, and 6D show FIGS. 6A, 6A, 6A, and 6B, respectively. FIG.

  6A, reference numeral 601 denotes a substrate having an insulating surface, and reference numerals 602 and 603 denote a pair of impurity regions (source or source) formed by adding N-type or P-type impurities to an active layer made of a semiconductor thin film. Drain region). Reference numeral 604 denotes an insulating film pattern used as a mask when forming a pair of impurity regions.

  In the case of an inverted staggered TFT, a gate electrode 605 and a gate insulating film 606 are stacked on a substrate 601 and an active layer made of a thin film semiconductor is formed thereon. Therefore, in order to implement the present invention, an insulating film (silicon oxide film or silicon nitride film) is patterned in a skewer shape, and an N-type or P-type impurity is added using the insulating film as a mask.

  As a result of adding impurities using the skewer-shaped insulating film pattern 604 as a mask, a skewer-shaped intrinsic or substantially intrinsic region 607 is formed thereunder. This region 607 also has a channel formed in the trunk that overlaps the gate electrode 605, and the other part (branch) functions as a heat sink. Since the other detailed description was demonstrated in Example 1, it abbreviate | omits here.

  As will be described in this embodiment, it is easy to apply the present invention to an inverted staggered TFT if a skewer-shaped insulating film pattern is used. In the case of this embodiment, the effective channel region cannot be formed in a self-aligned manner, but the effective channel region can be formed in a self-aligned manner in combination with the backside exposure technique.

  Next, a manufacturing process of an inverted staggered TFT using the present invention will be described with reference to FIGS. In FIG. 7, a cross section viewed from two cut ends will be described. That is, FIGS. 7A to 7E are cut ends of FIG. 6A cut along BB ′, and FIGS. 7A to 7E are FIGS. It is a cut with '.

  First, a glass substrate 701 provided with a base film made of a silicon oxide film is prepared as a substrate having an insulating surface, and a gate electrode 702 made of a tantalum film is formed thereon. Then, a gate insulating film 703 made of a silicon nitride film, a silicon oxide film, and a laminated film is formed thereon. (Fig. 7 (A), (A '))

Next, an amorphous silicon film (which may be a Si _x Ge _1-x film) is laser crystallized to form a polycrystalline silicon film, and an active layer 704 is formed. (Fig. 7 (B), (B '))

  Next, an insulating film pattern 705 having a skewer shape (a shape as shown in FIG. 6A) is formed using a silicon oxide film. This film thickness needs to be sufficient to function as a mask when impurities are added, and is preferably 100 to 200 nm.

  When the insulating film pattern 705 is formed in this way, an impurity exhibiting N-type or P-type is added to form a pair of impurity regions 706 and 707. At the same time, an intrinsic or substantially intrinsic semiconductor region 708 is formed in a skewer shape. (FIG. 7 (C), (C ′))

  After the pair of impurity regions (source / drain regions) 706 and 707 and the skew-shaped intrinsic or substantially intrinsic semiconductor region 708 are thus formed, the impurity is activated and an interlayer insulating film 709 is formed. (FIG. 7 (D), (D ′))

  Note that the insulating film pattern used in the impurity addition step serves to protect the intrinsic or substantially intrinsic region 708. In particular, when an organic resin film is used as the interlayer insulating film, it is effective in preventing organic contamination.

  Next, contact holes are opened to form source or drain electrodes 710 and 711, and finally hydrogenation is performed to complete a TFT having a structure as shown in FIGS. 7E and 7E.

  As in the first embodiment, this embodiment is not limited to the present embodiment with respect to the TFT structure and configuration. Therefore, it is possible to use the present invention in a bottom gate type TFT having another structure or a purchased bottom gate type TFT manufactured by another manufacturing method. Of course, even a structure in which an LDD region or an offset region is provided does not hinder the implementation of the present invention.

  Needless to say, the inversely staggered TFT of the present invention may be configured as a CMOS circuit or partially used as shown in the second embodiment.

  In Example 1 or Example 3, it is necessary to intentionally provide a mask pattern such as a resist mask in order to form a branch (second region) of an intrinsic or substantially intrinsic semiconductor region. It is also possible to form a skewer-shaped intrinsic or substantially intrinsic region in a self-aligned manner by using a skewered shape.

  That is, the gate electrode is patterned in a skewer shape so that the source / drain region and the intrinsic or substantially intrinsic region are completely self-aligned.

  In the case of the bottom gate type TFT of Example 3, a resist pattern having the same shape as that of the gate electrode can be formed by using the back surface exposure. Therefore, by using the resist pattern as a mask, impurities are added in a self-aligning manner. be able to.

  In this embodiment, a channel is formed in all regions of the intrinsic or substantially intrinsic semiconductor region during TFT operation (when in the on state). However, since the resistance of the channel region is one digit or more higher than the resistance of the source / drain region, carriers move preferentially in the portion where the source / drain region is closest.

  As a result, the effects of the present invention as described in the first embodiment can be obtained. Of course, as in the configuration shown in the first embodiment, it is preferable that the second region function as a complete resistor without applying a gate voltage at all in terms of suppressing heat generation.

  However, if the configuration of the present embodiment is implemented, the impurity addition step can be performed by a complete self-alignment process using only the gate electrode as a mask. can get.

  In the first to fourth embodiments, the branch portion (second region) is provided for both of the pair of impurity regions (both the source / drain regions). However, the branch portion is present only on one of them. It is good also as a shape.

  In particular, since the drain junction (the junction between the channel region and the drain region) is the portion that generates heat most easily, the second region is provided only on the drain region side, and the second region is not provided on the source region side. A configuration is also possible.

  Further, the width and length of the second region need not all be the same, and may be different as necessary. For example, the second region may be thicker near the center of the active layer where Joule heat is likely to accumulate, and the second region provided at the end of the active layer may be thinner than that near the center.

  In this embodiment, the arrangement of contact holes for forming source / drain electrodes will be described with reference to FIG.

  First, FIG. 8A shows an example of arrangement of contact holes in the TFT having the structure shown in FIG. 1 (the same parts as those in FIG. 1A are denoted by the same reference numerals). In this case, the impurity regions 102 are all connected at the side edge of the active layer, and a contact hole 801 is formed in that portion.

  Similarly, the impurity regions 103 are all connected to the active layer on the side end portion side, and a contact hole 802 is formed in that portion.

  Such a configuration is effective when the interval between the second regions 803 is narrow. When this interval is as narrow as 3 μm or less, there is no margin for providing a contact hole between them, so a space for forming the contact hole must be secured.

  In addition, when the distance between the second regions is as wide as 3 μm or more (preferably 5 μm or more), a contact hole can be provided between them, so that a structure as shown in FIG. 8B is possible. .

  In the case of the structure shown in FIG. 8B, the impurity regions 804 and 805 are completely divided by a plurality of second regions 806, and each function as a plurality of source regions (or drain regions).

  The contact holes 807 and 808 are disposed in individual regions of the impurity regions 804 and 805 divided into a plurality of parts, thereby realizing a configuration in which a plurality of TFTs are substantially connected in series.

  In such a configuration, since the function as the heat sink of the second region 806 can be used effectively, there is an advantage that the heat dissipation effect is high.

  Various semiconductor circuits can be configured by configuring a circuit using the TFT having the configuration of the present invention shown in Embodiments 1 to 6. An electro-optical device typified by an active matrix LCD can be manufactured by integrally forming such a circuit on the same substrate.

  Further, as another electro-optical device, it is effective to use the present invention for an electro-optical device in which a TFT is used as a switching element such as an EL display device or an image sensor.

  Even when a semiconductor circuit such as a high-frequency circuit or a processor circuit is manufactured using a TFT having a high operating speed, it is effective to use the TFT having the configuration of the present invention.

  When these electro-optical devices and semiconductor circuits (these are collectively included in the semiconductor device) are used, TFTs having the configuration of the present invention are used to reduce thermal degradation of the entire circuit, and reliability (durability). A high semiconductor device can be realized.

  The electro-optical device and the semiconductor circuit as shown in Embodiment 7 can be incorporated into various electronic devices.

  Liquid crystal display devices and EL display devices can be used as display displays for personal computers, mobile terminal devices (mobile computers, mobile phones, etc.), projector display devices, and digital (video) cameras.

  The image sensor can be used as an imaging component such as a scanner or a digital (video) camera.

  Further, a semiconductor circuit such as a high-frequency circuit or a processor circuit can be used for an electronic device having a computer control function such as a personal computer or a daily household appliance.

  As described above, the present invention can be applied to any electronic device as long as the electronic device operates by incorporating therein a semiconductor device including a TFT formed using a thin film semiconductor.

The figure which shows the structure of an active layer. The figure which shows the structure of the conventional active layer. The figure which shows the structure of an intrinsic | native or substantially intrinsic area | region. The figure for demonstrating the definition of channel length and channel width. 10A and 10B show a manufacturing process of a TFT. The figure which shows the structure of an active layer. 10A and 10B show a manufacturing process of a TFT. The figure which shows arrangement | positioning of a contact hole.

Claims (8)

A semiconductor device having a crystalline silicon film, a gate insulating film, and a gate electrode overlapping with the crystalline silicon film via the gate insulating film,
The crystalline silicon film has one conductive impurity region and an intrinsic or substantially intrinsic region,
The intrinsic or substantially intrinsic region is provided so as to extend in a direction substantially perpendicular to the channel length direction, the first region overlapping the gate electrode, and the direction substantially parallel to the channel length direction. A plurality of second regions provided protruding from the first region,
The impurity region is divided into a plurality in a direction perpendicular to the channel length direction by the first region and the plurality of second regions,
A semiconductor device, wherein a contact hole is disposed in each of the plurality of impurity regions.   2. The semiconductor device according to claim 1, wherein the crystalline silicon film is a single crystal thin film or a polycrystalline thin film.   3. The semiconductor device according to claim 1, wherein the first region is formed in a self-aligned manner using the gate electrode as a mask, and the second region is formed by photolithography. Forming a gate electrode over the crystalline silicon film via an insulating film;
Crossing the gate electrode to form one or more island patterns substantially perpendicular to the longitudinal direction of the gate electrode;
By adding one conductive impurity to the crystalline silicon film using the gate electrode and the island pattern as a mask, the gate electrode overlaps with the gate electrode provided extending in a direction substantially perpendicular to the channel length direction. The first region, the plurality of second regions provided to protrude from the first region in a direction substantially parallel to the channel length direction, the first region and the plurality of second regions, Forming an impurity region divided into a plurality in a direction perpendicular to the channel length direction;
A method for manufacturing a semiconductor device, wherein a contact hole is disposed in each of the plurality of impurity regions. Forming a gate electrode,
Forming a crystalline silicon film over the gate electrode through an insulating film;
An insulating film pattern comprising a first region overlapping the gate electrode and a second region protruding from the first region substantially perpendicular to the longitudinal direction of the gate electrode is formed above the crystalline silicon film. And
By adding one conductive impurity to the crystalline silicon film using the insulating film pattern as a mask, an impurity region divided into a plurality in the longitudinal direction of the gate electrode is formed,
Forming an interlayer insulating film on the plurality of divided impurity regions and the insulating film pattern;
A method for manufacturing a semiconductor device, comprising: forming a contact hole reaching each of the plurality of impurity regions divided in the interlayer insulating film.   6. The method for manufacturing a semiconductor device according to claim 5, wherein the insulating film pattern is a silicon oxide film or a silicon nitride film.   7. The method for manufacturing a semiconductor device according to claim 5, wherein the interlayer insulating film is an organic resin film. 8. The method for manufacturing a semiconductor device according to claim 4, wherein the crystalline silicon film is a single crystal thin film or a polycrystalline thin film.

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