JPH06314784A - Thin film transistor and its manufacture - Google Patents

Abstract

PURPOSE:To improve the reliability and characteristics of a thin film transistor by improving the reliability of a gate insulating film, a gate electrode and gate wiring. CONSTITUTION:Impurity is introduced into the edges 14 of the active layer (island-shaped semiconductor part), especially at a part where a gate electrode crosses, in order to permit the edges to be insulators. Thus, defects of a part 16 are prevented.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a thin film transistor (T
FT) structure and manufacturing method. The thin film transistor manufactured by the present invention is formed on either an insulating substrate such as glass or a semiconductor substrate such as single crystal silicon.

[0002]

2. Description of the Related Art Conventionally, a thin film transistor is formed by patterning a thin film semiconductor region (active layer) in an island shape, and then forming an insulating film as a gate insulating film by a CVD method or a sputtering method, and then forming a gate film thereon. The electrode was formed.

[0003]

The insulating coating formed by the CVD method or the sputtering method has a poor step coverage (step coverage), which adversely affects reliability, yield, and characteristics. FIG. 5 is a top view of a typical conventional TFT,
And a cross-sectional view taken along line AA ′ and BB ′ of the drawing. The TFT is formed on the substrate 51, the thin film semiconductor region is located below the impurity region (source / drain region, which shows N type conductivity here) 53 and the gate electrode 57, and is a substantially intrinsic channel forming region. A gate insulating film 55 is provided so as to cover the semiconductor region. A contact hole is opened in the impurity region 53 through an interlayer insulator 59, and an electrode / wiring 58 is provided.

As can be seen from the figure, the coverage of the end portion of the semiconductor region of the gate insulating film 55 is extremely poor, and typically only half the thickness of the flat portion is present. Generally, when the island-shaped semiconductor region is thick, it is extremely large. Particularly, from the AA 'cross section along the gate electrode, it can be seen that such deterioration of the covering property adversely affects the characteristics, reliability and yield of the TFT. That is, paying attention to the region 56 indicated by the dotted circle in the AA ′ sectional view of FIG. 5, the electric field of the gate electrode 57 is intensively applied to the end portion of the thin film semiconductor region. That is, since the thickness of the gate insulating film in this portion is half that of the flat portion, the electric field strength thereof is doubled.

As a result, the gate insulating film in the region 56 is easily destroyed by applying a high voltage for a long time. If the signal applied to the gate electrode is positive, the semiconductor in this region 56 is also N-type, so that the gate electrode 57 and the impurity region 58 (particularly, the drain region) become conductive, which causes deterioration in reliability. Becomes

When the gate insulating film is destroyed,
It happens that some charge is trapped, for example
If the negative charges are trapped, the semiconductor in the region 56 exhibits N-type and the two impurity regions 58 become conductive regardless of the voltage applied to the gate electrode, which deteriorates the characteristics. Further, in order to use the TFT without causing the above deterioration, only half the voltage as in the ideal case can be applied, and the performance cannot be fully utilized.

The presence of such a weak portion in a part of the TFT means that the TFT is easily destroyed due to charging or the like in the manufacturing process, which is a major factor for lowering the yield. An object of the present invention is to solve such a problem.

[0008]

According to the present invention, in the semiconductor of such an electrically weak region, any one element or a plurality of elements of carbon, oxygen and nitrogen is averaged in an island-shaped semiconductor region. It is characterized in that it is compensated by increasing the resistance of the portion by increasing the concentration higher than that. A typical structure of the present invention is shown in FIG. Similarly to FIG. 5, FIG. 1 also shows a drawing in which the TFT is viewed from above and cross-sectional views taken along the lines AA ′ and BB ′. The TFT is formed on the substrate 11, and the thin film semiconductor region is composed of an impurity region (source and drain regions, which are of N-type conductivity type here, but may be P-type) 13 and a gate electrode 17. Located below and divided into a substantially intrinsic channel forming region 12,
A gate insulating film 15 is provided so as to cover this semiconductor region. A contact hole is formed in the impurity region 13 through an interlayer insulator 19, and an electrode / wiring 18 is provided.

The difference from the conventional TFT shown in FIG. 5 is that
That is, the region 14 in which the concentration of at least one element of nitrogen, oxygen, and carbon is higher than the average concentration of the semiconductor region is provided at least under the gate electrode. For example, if the average nitrogen concentration in the semiconductor region is 10 ¹⁸ cm ⁻³ , the nitrogen concentration in this portion should be 10 ¹⁹ cm ⁻³ or higher, preferably 10 ²⁰ cm ⁻³ or higher. To introduce. As a result, the resistance of the region 14 increases significantly. Similarly, when oxygen and carbon are used, a high resistance region could be formed by introducing oxygen and carbon at a concentration of 10 ¹⁹ cm ^-3 or more, preferably 10 ²⁰ cm ^-3 or more. .

The effect of the region 14 will be described by focusing on the region 16 of the AA 'cross section. As in the case of the conventional TFT, the coverage of the gate insulating film at the end of such a semiconductor region is not good. Therefore, in this portion, the gate insulating film is destroyed by a voltage of about half that in the ideal case, and pinholes are generated or charges are trapped. However, when the region 14 exists, the resistance of the region 14 reduces the voltage applied to the gate insulating film. As a result, the breakdown of the gate insulating film can be prevented. Further, even if a pinhole is generated or charge is trapped in the gate insulating film at the end of the semiconductor region, this portion is isolated from the impurity region 13 and the channel forming region 12 below the gate electrode by the region 14. As it is done, it has almost no effect.

Therefore, it is possible to remarkably reduce the leak current between the gate electrode and the drain region and the conduction between the source and the drain. If there is no problem in characteristics and reliability even if the gate insulating film is destroyed in this way, the voltage limit during use will be less, and the probability of occurrence of defective products due to electrostatic breakdown during manufacturing. Also decreases and the yield improves.

FIG. 1 shows a state in which nitrogen, carbon, oxygen, etc. are introduced into all the ends of the thin film semiconductor region on the side where the gate electrode crosses, but such a region is at least in the region below the gate electrode. It will be apparent from the above description that provision is sufficient. It should be noted that when an organic material such as a photoresist is used as a mask when doping oxygen, the mask is oxidized and disappears if the dose amount is large.

As still another invention, the present invention is directed to a semiconductor region (source / drain, channel forming region) forming an active layer (source / drain, channel forming region) of a TFT (in FIG. 5, impurity region 53 forming a source / drain and a channel forming region). The semiconductor region in which the region 52 is formed) itself is not formed in an island shape (island shape), but a semiconductor region forming this active layer is formed in the semiconductor film itself. In other words, the semiconductor regions forming the source / drain and channel forming regions are not patterned by island patterning but formed in the semiconductor film to function as source / drain and channel forming regions. And

For example, FIG. 7 shows an embodiment of the present invention. In FIG. 7, the active layer region in which the source / drain and channel forming regions are formed is a portion 207. Except for the portion 207, nitrogen, oxygen, carbon and an element for insulating the semiconductor are added to be insulated. That is, the present invention does not form an active layer by patterning, but insulates a portion other than the active layer by, for example, implanting oxygen ions by an ion implantation method, and selectively forms a region to be the active layer. To form.

In this case, at least the TFT can be formed if at least the periphery of the active layer region 207 is insulated. However, it is possible to suppress the occurrence of unnecessary leaks and parasitic points and improve reliability by insulating all but the active layer region 207. Further, when silicon is used as the semiconductor, the region to be insulated can be made of silicon oxide or silicon nitride, so that it can be made transparent to visible light and liquid crystal using a glass substrate. It can be used for optical devices.

In this structure, when silicon is used as the semiconductor forming the active layer, if oxygen ions, nitrogen ions or carbon ions are implanted into the portion other than the active layer,
The portion can be silicon oxide, silicon nitride, or silicon carbide. The amount of impurities introduced to insulate these semiconductors is set to a concentration of 10 ¹⁹ cm ^-3 or more, preferably 10 ²⁰ cm ^-3 or more.

[0017]

By introducing nitrogen, carbon and oxygen into all the ends of the thin film semiconductor region on the side where the gate electrode is crossed, the voltage applied to the gate insulating film is reduced and the gate insulating film is prevented from being destroyed. It is possible to improve reliability.

By selectively insulating a region other than the semiconductor film forming the active layer, the gate insulating film and the gate electrode provided above the active layer can be provided flat, which causes a problem of step coverage and causes a problem during operation. Problems such as dielectric breakdown and electric field concentration can be solved.

[0019]

【Example】

[Embodiment 1] FIG. 2 shows a cross-sectional view of a manufacturing process of this embodiment. In the drawings of the following embodiments including this embodiment, TF
Only the cross-sectional view of T is shown, and in each case, the left side is a plane perpendicular to the gate electrode (corresponding to the cross section BB 'in FIGS. 1 and 5), and the right side is a plane parallel to the gate electrode (FIG. , Corresponding to section AA 'in FIG. 5).

First, a base film 21 of silicon oxide having a thickness of 2000 Å was formed on a substrate (Corning 7059) 20 by sputtering. Further, an amorphous silicon film having a thickness of 500 to 1500 Å, for example 1500 Å, was deposited by the plasma CVD method. The nitrogen concentration in the amorphous silicon film was 1 × 10 ¹⁸ cm ⁻³ or less.
Subsequently, a 200 Å-thick silicon oxide film was deposited as a protective film by a sputtering method. Then, this was annealed at 600 ° C. for 48 hours in a reducing atmosphere to be crystallized. The crystallization step may be a method using strong light such as a laser. Then, the obtained crystalline silicon film was patterned to form island-shaped silicon regions 22a and 22b. Protective films 23a and 23b are respectively placed on the island-shaped silicon film. This protective film has a function of preventing the island-shaped silicon region from being contaminated in the subsequent photolithography process.

Next, a photoresist is applied on the entire surface and the resist 24 is formed by a known photolithography method.
Patterning was performed leaving a and 24b. Then, nitrogen was introduced using this resist as a mask. A plasma doping method was used to introduce nitrogen. Nitrogen gas is used as a doping gas, and rf power is 10 to 30 W, for example, 1
It was discharged at 0 W to generate plasma, which was accelerated at an accelerating voltage of 20 to 60 kV, for example, 20 kV, and was introduced into the silicon region. The dose amount is 1 × 10 ^{15 to} 5 × 10 ^16.
cm ⁻² , for example, 1 × 10 ¹⁶ cm ⁻² . As a result,
Nitrogen-doped regions 25a, 25b, 25c, 25
d was formed. Under these conditions, the concentration of nitrogen in this nitrogen-doped region was about 1 × 10 ²¹ cm ^−3, and a significantly larger amount of nitrogen was introduced than in other semiconductor regions. (Fig. 2 (A))

Next, a thickness of 10 is obtained by the sputtering method.
A silicon oxide film 26 of 00Å is deposited as a gate insulating film,
Subsequently, a thickness of 6000 to 8 is obtained by a low pressure CVD method.
000Å, for example 6000Å silicon film (0.1-2
% Phosphorus) was deposited. It is desirable that the steps of forming the silicon oxide and the silicon film are continuously performed.
Then, the silicon film is patterned to form the wiring 27a,
27b was formed. Each of these wirings functions as a gate electrode. (Fig. 2 (B))

Next, impurities (phosphorus) were implanted into the silicon region by plasma doping using the wiring 27a as a mask. As doping gas, phosphine (PH
₃ ) is used and the acceleration voltage is 60 to 90 kV, for example 80 kV.
It was set to V. The dose is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 ,
For example, it is set to 5 × 10 ¹⁵ cm ⁻² . Then, the impurities were activated by annealing at 600 ° C. for 48 hours in a reducing atmosphere. In this way, the impurity region 28
a and 28b were formed. (Fig. 2 (C))

Subsequently, a 3000 Å-thick silicon oxide film is formed as an interlayer insulating film by a plasma CVD method, a contact hole is formed in this film, and a wiring 29a is formed by a metal material such as a multilayer film of titanium nitride and aluminum.
29b was formed. The wiring 29a connects the wiring 27b and one of the impurity regions 28b of the TFT. The semiconductor circuit is completed through the above steps. (Fig. 2 (D))

[Embodiment 2] FIG. 3 shows a cross-sectional view of a manufacturing process of this embodiment. A base film 31 of silicon oxide having a thickness of 2000 Å was formed on a substrate (Corning 7059) 30 by sputtering. Further, an amorphous silicon film having a thickness of 500 to 1500 Å, for example 1500 Å, was deposited by the plasma CVD method. Subsequently, a 200 Å-thick silicon oxide film was deposited as a protective film by a sputtering method. Then, in a reducing atmosphere, this is 600 ° C.
It was annealed for 48 hours and crystallized. The crystallization step may be a method using strong light such as a laser. Then, the obtained crystalline silicon film is patterned by a known photolithography method to form island-shaped silicon regions 32a and 32a.
b was formed. A protective film is left on the island-shaped silicon film. Further, the photoresist masks 33a and 33b used for etching are also left. In this etching step, an isotropic etching method (for example, wet etching with hydrofluoric acid) was used, and the end face of the semiconductor region was tapered as shown in the figure.

Next, nitrogen was introduced using this resist as a mask. A plasma doping method was used to introduce nitrogen. Ammonia (NH ₃ ) or hydrazine (N ₂ H ₄ ) is used as the doping gas, and the acceleration voltage is 20 to 6
It was accelerated at 0 kV, for example 20 kV, and introduced into the silicon region. The dose amount is 1 × 10 ^{15 to} 5 × 10 ¹⁶ cm ^-2 ,
For example, it is set to 1 × 10 ¹⁶ cm ^-2 . As a result, nitrogen-doped regions 34a, 34b, 34c, 34d were formed. (Fig. 3 (A))

Further, since the base film 31 is also doped with nitrogen, the base film 31 can be a silicon oxynitride film, and there is an effect that the base film is not removed by a subsequent etching process. .

Next, a thickness of 10 is obtained by the sputtering method.
A silicon oxide film having a thickness of 00Å is deposited as a gate insulating film, and subsequently, a thickness of 6000 to 800 is formed by a low pressure CVD method.
An aluminum film (containing 2% of silicon) of 0Å, for example, 6000Å was deposited. In addition, it is desirable that the steps of forming the silicon oxide film and the aluminum film are continuously performed. Then, the aluminum film was patterned to form wirings 35a and 35b. Each of these wirings functions as a gate electrode. Further, the surface of this aluminum wiring is anodized to form oxide layers 36a, 3 on the surface.
6b was formed. Before the anodization, a mask 37 was selectively formed by a photosensitive polyimide (photonice) at a portion where a contact was to be formed later. During anodic oxidation, no anodic oxide was formed in this part due to this mask.

The anodization was carried out in a 1-5% ethylene glycol solution of tartaric acid. The thickness of the obtained oxide layer was 2000Å. Next, the wiring 35a and the oxide 36a are formed in the silicon region by plasma doping.
Impurities (phosphorus) were implanted using the as a mask. Phosphine (PH ₃ ) was used as a doping gas, and the acceleration voltage was set to 60 to 90 kV, for example, 80 kV. Dose is 1
× 10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 , for example, 5 × 10 ¹⁵ cm
^-2 . Thus, the N-type impurity regions 37a, 3
7b was formed. (Fig. 3 (B))

After that, the impurities were activated by the laser annealing method. As a laser, a KrF excimer laser (wavelength 248 nm, pulse width 20 nse
Although c) is used, other lasers such as XeF excimer laser (wavelength 353 nm), XeCl excimer laser (wavelength 308 nm), ArF excimer laser (wavelength 193 nm) and the like may be used. The energy density of the laser was 200 to 350 mJ / cm ² , for example, 250 mJ / cm ^2, and the irradiation was performed for 2 to 10 shots, for example, 2 shots per location. The substrate may be heated to about 200 to 450 ° C. during laser irradiation. It should be noted that the optimum laser energy density changes when the substrate is heated. The polyimide mask 37 was left during the laser irradiation. This is because the exposed aluminum is damaged by laser irradiation. After laser irradiation, this polyimide mask can be easily removed by exposure to oxygen plasma.

In this embodiment, unlike the case of the first embodiment, the nitrogen-implanted region 34c under the gate electrode,
No. 34d has a low crystallization rate because no laser light is incident, but since the crystallinity is destroyed during ion implantation, it functions as an extremely large resistance and is effective for reducing the leak current. (Fig. 3 (C))

Then, a silicon oxide film 38 having a thickness of 3000 Å is formed.
Is formed by plasma CVD as an interlayer insulator,
A contact hole is formed in this, and the wiring 3 is made of a metal material, for example, a multilayer film of titanium nitride and aluminum.
9a and 39b were formed. The wiring 39a is connected to the wiring 35b and T
One of the impurity regions 37b of the FT is connected. The semiconductor circuit is completed through the above steps. (Fig. 3 (D))

[Embodiment 3] FIG. 4 shows a cross-sectional view of a manufacturing process of this embodiment. An underlayer film 41 of silicon oxide having a thickness of 2000 Å was formed on a substrate (Corning 7059) 40 by sputtering. Further, an amorphous silicon film having a thickness of 500 to 1500 Å, for example 1500 Å, was deposited by the plasma CVD method. Then, the obtained amorphous silicon film was patterned to form island-shaped silicon regions 42a and 42b.

Next, a photoresist is applied on the entire surface and the resist 43 is formed by a known photolithography method.
Patterning was carried out leaving a and 43b. Then, nitrogen was introduced using this resist as a mask. A plasma doping method was used to introduce nitrogen. As a result, nitrogen-doped regions 44a, 44b, 44c and 44d were formed. (Fig. 4 (A))

Next, with the photoresist remaining, a silicon oxide film 45a having a thickness of 1000 liters was deposited by the sputtering method. (FIG. 4B) Then, the photoresist was peeled off to remove the silicon oxide film formed thereon. The silicon oxide film remains as it is in the portion where the photoresist was not present. This was crystallized by annealing at 600 ° C. for 48 hours in a reducing atmosphere. The crystallization step may be a method using strong light such as a laser.

Next, a thickness of 10 is obtained by the sputtering method.
A silicon oxide film 45b of 00Å is deposited as a gate insulating film, and subsequently, a thickness of 6000 is obtained by a low pressure CVD method.
~ 8000Å, eg 6000Å silicon film (0.1
˜2% phosphorus) was deposited. It is desirable that the steps of forming the silicon oxide and the silicon film are continuously performed. Then, the silicon film is patterned to form the wiring 46.
a and 46b were formed. Each of these wirings functions as a gate electrode. Also, paying attention to the peripheral portion of the silicon-on-island region (the region where boron was previously implanted), the thickness of the insulating film is approximately doubled here by the silicon oxides 45a and 45b. Therefore, it is effective for preventing the breakdown of the gate insulating film. (Fig. 4 (C))

Next, impurities (phosphorus) were implanted into the silicon region by plasma doping using the wiring 46a as a mask. As doping gas, phosphine (PH
₃ ) was used. Then, in a reducing atmosphere, at 48 ° C at 48
The impurities were activated by annealing for a period of time. Thus, the impurity regions 47a and 47b were formed. Then, a silicon oxide film 48 having a thickness of 3000 Å is formed as an interlayer insulator by a plasma CVD method, a contact hole is formed in the film, and wirings 49a and 49 are made of a metal material, for example, a multilayer film of titanium nitride and aluminum.
b was formed. The wiring 49a connects the wiring 46b and one of the impurity regions 47b of the TFT. The semiconductor circuit is completed through the above steps. (FIG. 4 (D)) The present embodiment improved the yield more than double that of the conventional one. Further, the deterioration of the TFT characteristics was not particularly recognized. On the contrary, since the maximum voltage that can be used has increased 1.5 to 2 times that of the conventional one, the maximum operating speed has increased 2 to 4 times.

[Embodiment 4] In this embodiment, in a TFT provided on a glass substrate, an active layer (a semiconductor layer composed of a source / drain region and a channel forming region) is formed in a crystalline silicon film. Thus, the gate insulating film and the gate electrode formed above the active layer are flatly provided. FIG. 6 shows the structure of the manufacturing process of this example. FIG. 6 shows a P-channel type TFT and an N-channel type T
In this example, FT and FT are provided in a complementary manner. Note that a known TFT manufacturing method can be used as a manufacturing method other than the active layer.

First, in FIG. 6A, the glass substrate 10
A base film (silicon oxide film) 99 having a thickness of 2000 Å was formed on 1 by sputtering. Next, the amorphous silicon film 100 is formed by a known plasma CVD method.
Was deposited to a thickness of 1000Å. In the past, it was not possible to increase the thickness of the amorphous silicon film (which constitutes the active layer) due to the problem of the step coverage of the gate insulating film, but in the present embodiment, the problem of the step coverage of the gate insulating film is considered. Since it need not be taken into consideration, the amorphous silicon film 100 can be formed with a thickness as necessary. After this step, the amorphous silicon 100 may be crystallized by heat annealing or laser light irradiation. Further, instead of the amorphous silicon film, a crystalline silicon film may be formed directly.

Next, the silicon oxide film 102 is formed as a protective film 20
Form a film with a thickness of 0Å. Further, an aluminum layer serving as a mask is formed to a thickness of 8000Å, and patterning is performed to determine the active layer region. That is, in FIG. 6B, 10
2 is a silicon oxide film as a protective film, and 103 and 104 are aluminum masks for defining the active layer region. The silicon oxide film 102 protects the surface of the amorphous silicon film 100 from being damaged when nitrogen ions are subsequently implanted. A resist may be used instead of the aluminum masks 103 and 104.

Next, nitrogen ions are implanted into the entire surface by the ion implantation method, and the nitrogen ions are implanted in the region where the masks 103 and 104 are not present. The ion implantation condition is that the acceleration voltage is 40k.
V, the dose amount is 6 × 10 ¹⁷ / cm ² . The accelerating voltage can be in the range of about 20 to 80 kV, but if it is too large, the damage to the film is large, and if it is too small, the lower layer portion of the film cannot be completely insulated when the amorphous silicon film 201 is thick. The dose of nitrogen ions is preferably 4 × 10 ¹⁷ cm ^-2 or more.
This is because the conductivity (Scm ⁻¹ ) of the film was investigated after implanting nitrogen ions under the above conditions and then annealing the film at 600 ° C. for 48 hours by annealing.
Based on the data shown in 0. In this case, the conductivity of the active layer regions where nitrogen ions were not implanted, that is, the regions of 106 and 108, by thermal annealing at 600 ° C. for 48 hours,
This is because it is about 10 ⁻⁵ Scm ⁻¹ , and as compared with this, it is preferably 10 ⁻¹¹ Scm ⁻¹ or less to form an insulating region.

By implanting the nitrogen ions into regions other than the active layer region, the active layers 106 and 1 of the two TFTs are formed.
08 is formed so as to be embedded in the silicon nitride film.
Then, the region which is insulated and becomes silicon nitride is shown in FIG.
It is shown by 105 of (B).

Next, the masks 103 and 104 are removed, and 6
The active layer regions 106 and 108 are crystallized by a thermal annealing process at 00 ° C. for 48 hours. This crystallization may be performed by irradiation with laser light, and the method is not particularly limited. At the same time, this annealing step activates the implanted nitrogen ions,
Insulation of the area 05 is promoted. That is, annealing after implantation of nitrogen ions is also performed at the same time.

Next, the silicon oxide film 102, which is a protective film, is removed, and a silicon oxide film to be the gate insulating film 107 is removed by one step.
A film is formed to a thickness of 000Å by a sputtering method.
Since the gate insulating film 107 is formed in a flat area without steps, the problem relating to step coverage can be greatly reduced. Next, an aluminum film (containing 2% of silicon) is formed to a thickness of 6000Å, and the gate electrodes 110 and 111 are formed by patterning.
The gate electrode may be a known silicon gate.
Next, the surface of this gate electrode is anodized to form oxide layers 112 and 113 on the surface. The thickness of the oxide layer determines the length of the offset gate region in the subsequent source / drain region formation step.

Next, B and N
P is ion-implanted into the area to be the TFT,
Mold regions 114 and 116 and N-type regions 117 and 119 are formed. In this ion implantation, necessary regions were implanted by protecting one region with a resist. Furthermore, activation is performed by irradiation with laser light. In this way, the source / which constitutes the active layer of the PTFT
The drain regions 114 and 116, the channel forming region 115 of the PTFT, the source / drain regions 117 and 119 forming the active layer of the NTFT, and the channel forming region 118 of the NTFT are formed in a self-aligned manner.

Next, the interlayer insulating film 12 made of silicon oxide.
0, and further electrodes 121 and 12
By forming as shown by 2 and 123, PTFT and N
A TFT circuit having a complementary structure with the TFT was completed. This circuit can be used for an integrated circuit provided on a substrate, particularly a glass substrate, a peripheral circuit of a liquid crystal display device, and a switching portion provided in a pixel portion of the liquid crystal display device.

In the structure of this embodiment, since the gate insulating film 107, the gate electrodes 110 and 111, and the wiring from the gate electrodes can be formed on a flat substrate, the electric field concentration at the end of the active layer can be prevented. It can fundamentally solve problems and problems of dielectric breakdown.

[Embodiment 5] In this embodiment, a TF provided in a pixel portion of an active matrix type liquid crystal display device.
Regarding T. FIG. 7 shows a manufacturing process diagram of this example. First, a base film (silicon oxide film) 202 is formed on the glass substrate 201 by 2
A film with a thickness of 000 Å is formed, and an amorphous silicon film 203 is formed with a thickness of 1000 Å by the plasma CVD method. The method for forming this amorphous silicon film is not particularly limited, and it may be a sputtering method or a reduced pressure heat CV.
It may be appropriately selected from known methods such as method D and photo CVD.

Next, the silicon oxide film 204 serving as a protective film has a thickness of 200 Å and the aluminum layer serving as a mask has a thickness of 8000 Å.
To form a film. Then, only the aluminum layer is patterned to form a mask 205. This mask 205 defines the active layer region of the TFT. Next, nitrogen ions are implanted under the same conditions as in Example 4. Then, after removing the mask 205, crystallization of the active layer region 2007 and annealing of the insulating region 206 by activation of implanted nitrogen ions (promotion of crystallization) are performed by the same thermal annealing process as in the fourth embodiment. I went at the same time.

Next, as in the case of Example 4, a gate electrode 208 whose periphery is anodized (indicated by 209) is formed. The gate electrode may be made of known silicon. Further, P (phosphorus), which is an impurity imparting N-type conductivity, is ion-implanted at an acceleration voltage of 60 kV to self-align the source / drain regions 210 and 212 and the channel forming region 211 in self-alignment. Form. further,
The source / drain regions 21 are irradiated with the laser light.
Activation of 0 and 212 is performed. Then, the interlayer insulator 212 is formed of silicon oxide, and the ITO electrode 21 serving as a pixel electrode is formed.
6 and metal electrodes 215 and 214 to form an N-channel type T
Complete the FT.

FIG. 8 shows a drawing of the structure shown in FIG. 7D taken along the line AA '. Further, FIG. 9 shows an outline of a configuration when FIG. 7D is viewed from above the substrate. In FIG. 9, the cross section indicated by BB ′ corresponds to FIG. 7. Further, in FIG. 9, the cross section indicated by AA ′ corresponds to FIG. 8. The reference numerals correspond to those in FIG. 7, FIG. 8 and FIG. 9, respectively. Here, as is apparent from FIG. 8, since the gate insulating film 207 and the extended gate electrode 208 are formed in the flat region, the problem shown by 56 in FIG. 5 does not occur. . That is, there is basically no local strong electric field applied from the gate electrode 208 to the channel forming region 208 of the active layer at the end thereof. This means that the active layer (the channel forming region 211 of the cross section is visible in FIG. 8) is not patterned into an island shape, but the semiconductor in the region other than the active layer is insulated. This is due to the basic inventive idea of performing (indicated by 206).

FIG. 11 shows data obtained by examining the transmittance of a region insulated by implantation of nitrogen ions (region 105 in FIG. 6; region 206 in FIGS. 7 and 8).
The implantation condition of nitrogen ions is that the acceleration voltage is 40 kV,
After implantation, thermal annealing was performed at 600 ° C. for 48 hours. As is apparent from FIG. 11, it is understood that visible light (380 nm to 800 nm) is sufficiently transmitted when the dose amount of nitrogen ions is 3 × 10 ¹⁷ cm ⁻² or more.

That is, even when the structure shown in FIG. 7 is applied to the pixel portion of the active matrix type liquid crystal display device, the optical region of the liquid crystal display device is left while the region insulated by nitrogen ion implantation remains. It has no effect on the characteristics. Such usefulness is considered to be obtained even when oxygen ions are implanted instead of nitrogen ions. (As is well known, silicon oxide is transparent)

As described above, in this embodiment, the active layer is formed by injecting the material for insulating the semiconductor into the region other than the region to be the active layer region by the ion implantation method and insulating the region. It is possible to fundamentally solve various problems resulting from the defect of the step coverage (step coverage) of the gate insulating film, the gate electrode and the wiring electrode formed on the active layer by defining the region. . Further, since the insulated semiconductor region has a light-transmitting property with respect to visible light, it can be used in a region such as a pixel portion of an active matrix liquid crystal display device where light-transmitting property is required. it can.

[0055]

EFFECTS OF THE INVENTION The insulating layer is provided on the active layer by insulating the edges of the active layer, and by defining the active layer region by insulating the periphery of the active layer, rather than by patterning the active layer. TF can solve the problem of step coverage of the gate insulating film and gate electrode
The yield of T and its reliability can be improved.

[Brief description of drawings]

FIG. 1 shows a structural example of a TFT of the present invention.

2A to 2C show cross-sectional views of a manufacturing process of the TFT of Example 1.

3A to 3C show cross-sectional views of a manufacturing process of a TFT of Example 2.

4A to 4C show cross-sectional views of a manufacturing process of a TFT of Example 3.

FIG. 5 shows a configuration example of a conventional TFT.

FIG. 6 shows a cross section of a manufacturing process of a TFT.

7A to 7C show cross-sectional views of a manufacturing process of a TFT.

FIG. 8 shows a cross-sectional view of a TFT.

FIG. 9 shows a top view of a TFT.

FIG. 10 shows the relationship between nitrogen ion dose and conductivity.

FIG. 11 shows the relationship between nitrogen ion dose and transmittance.

[Explanation of symbols]

11 ... Substrate 12 ... Channel formation region (substantially intrinsic) 13 ... Impurity region (source, drain) 14 ... Doping region (including at least one of nitrogen, carbon, and oxygen) 15. ..Gate insulating film 16 ... Ends of island-shaped semiconductor region 17 ... Gate electrode 18 ... Source and drain electrodes 101 ... Glass substrate 99 ... Base film (silicon oxide film) 100 ... Amorphous silicon film 105 ... Insulated region 106 ... Active layer region 108 ... Active layer region 102 ... Silicon oxide film 104 ... Mask 107 ... Gate insulating film 110 ... Gate electrode 111 ... Gate electrode 112 ... Anodized layer 113 ... Anodized layer 114 ... Source / drain region 115 ... Channel formation region 116 ... Drain Source / drain region 117 ... source / drain region 118 ... channel forming region 119 ... drain / source region 120 ... interlayer insulator 121 ... electrode 122 ... electrode 123 ... electrode 201・ ・ ・ Glass substrate 202 ・ ・ ・ Base film (silicon oxide film) 203 ・ ・ ・ Amorphous silicon film 204 ・ ・ ・ Silicon oxide film 205 ・ ・ ・ Mask 206 ・ ・ ・ Insulated region 207 ・ ・ ・ Gate insulation Film 208 ... Gate electrode 209 ... Anodized layer 210 ... Source / drain region 211 ... Channel formation region 212 ... Drain / source region 213 ... Interlayer insulator 214 ... Electrode 215 ... Electrodes 216 ... ITO (pixel electrodes) 217 ... Electrodes

Claims (8)

[Claims] 1. A thin film transistor having an island-shaped thin film semiconductor region and a gate electrode crossing the semiconductor region, wherein the concentration of at least one element of oxygen, carbon, and nitrogen is at the periphery of the semiconductor region. A thin film transistor characterized in that there is a region larger than the average concentration of the semiconductor region and a gate electrode crosses the region. 2. A step of forming an island-shaped thin film semiconductor region, and at least one element of oxygen, carbon and nitrogen is selectively applied to at least a portion of the peripheral portion of the thin film semiconductor region which the gate electrode crosses. Introducing, forming a gate electrode across the thin film semiconductor region, and introducing impurities into the thin film semiconductor region in a self-aligned manner using the gate electrode as a mask to form source and drain regions. A method for manufacturing a thin film transistor having characteristics. 3. A step of forming an island-shaped thin film semiconductor region using a semiconductor material in a substantially amorphous state, and at least one element selected from oxygen, carbon and nitrogen is provided in a peripheral portion of the thin film semiconductor region. An impurity is characterized by having a step of introducing, a step of irradiating the thin film semiconductor region with a laser or strong light equivalent thereto to crystallize, and a step of forming a gate electrode across the thin film semiconductor region. Method for manufacturing thin film transistor. 4. A thin film transistor using a semiconductor film provided on a substrate having an insulating surface, wherein at least a periphery of an active layer region of the thin film transistor is insulated. 5. A thin film transistor using a semiconductor film provided on a substrate having an insulating surface, wherein a region other than an active region of the thin film transistor is insulated. 6. The silicon semiconductor film is used as the semiconductor film according to claim 3 or 4, wherein the insulated region is silicon oxide or silicon nitride, and the insulated region is exposed to visible light. A thin film transistor having a light-transmitting property. 7. A thin film transistor comprising: a step of forming a semiconductor film on a substrate having an insulating surface; and a step of adding a material for insulating the semiconductor film to a region at least around an active layer region to insulate the semiconductor film. Of manufacturing. 8. The method for manufacturing a thin film transistor according to claim 7, wherein at least one element selected from oxygen, carbon, and nitrogen is used as a material for insulating the semiconductor film.