JP2890037B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type electro-optical device, particularly to an active matrix type liquid crystal electro-optical device and the like, and shows a structure of a field effect transistor having clear switching characteristics and a method of manufacturing the same. It is.

[0002]

2. Description of the Related Art A thin film insulating gate type field effect transistor used in a conventional active matrix type liquid crystal electro-optical device has a structure as shown in FIG. Insulating substrate 2
09, a blocking layer 208, a source 204,
A gate insulating film 202 and a gate electrode 201 are provided over a semiconductor layer having a drain 205 and a channel region 203. An interlayer insulating film 211 and a source electrode 20
6, having a drain electrode 207;

[0003] In this conventional insulated gate field effect transistor, a blocking layer is formed on a glass substrate 209 by sputtering using SiO ₂ as a target, and then a semiconductor layer is formed by plasma CVD. ,
After forming a semiconductor layer to be a source, a drain and a channel region by patterning it, a gate insulating film 202 made of silicon oxide is formed by a sputtering method,
Thereafter, a gate electrode 201 is formed by patterning after forming a gate electrode conductive layer doped with P (phosphorus) at a high concentration using a low pressure CVD method. Thereafter, impurity ions are implanted using the gate electrode as a mask, and the source 20 is implanted.
5 and the drain 204, and then heat-treated to activate.

In the insulated gate type field effect transistor thus manufactured, the length of the gate electrode 201 in the channel length direction is substantially equal to the channel length 210.

[0005]

The current-voltage characteristic of the insulated gate field effect transistor having such a structure is n
In the case of a channel, as shown in FIG.
Has a disadvantage that the leak current increases as the applied voltage between the source and the drain increases.

When such a leak current is increased, when this element is used in an active matrix type liquid crystal electro-optical device, a write current 300 as shown in FIG.
The electric charge stored in the liquid crystal 302 through the leak current 301 was discharged through the leak portion of the element during the non-writing period, and a good contrast could not be obtained.

Therefore, in such a case, it is necessary to install a capacitor 303 for holding electric charges as shown in FIG. 5B as a conventional example. However, in order to form these capacitors, a capacitance electrode formed of metal wiring is required, which has been a factor of reducing the aperture ratio. In addition, there has been reported an example in which this is formed with a transparent electrode such as ITO to improve the aperture ratio, but it has not been welcomed since an extra process is required.

Further, when only one of the source and the drain of such an insulated gate field effect transistor is connected to a capacitor element (capacitor) and the transistor is used as a switching element, for example, a known one transistor / cell type transistor is used. Dynamic random
In an access memory (DRAM) device or an active liquid crystal display device having a circuit as shown in FIG. 5 in each pixel, the voltage of the capacitor element fluctuates due to the presence of the parasitic capacitance between the gate electrode and the drain (or source). Was known to do so.

[0009] variation ΔV of the voltage, since the proportion to the gate voltage V _G and the parasitic capacitance is inversely proportional to the sum of the capacitance and the parasitic capacitance of the capacitor element, in general in order to suppress the variation of the voltage, by a self-alignment manner A transistor has been manufactured to reduce the parasitic capacitance. However, as device design rules shrink,
No matter how the self-alignment method is used, the parasitic capacitance ratio has become so large that it cannot be ignored.

Therefore, in order to reduce ΔV, FIG.
As shown in (B), besides the original capacitor element,
It has been proposed to connect capacitors in parallel to increase the capacitance of the capacitor element apparently.
In a RAM, the problem of an increase in the capacitor area, and in a liquid crystal display device, as described above, a problem such as a decrease in the aperture ratio cannot be ignored. The present invention solves the above problems.

[0011]

Means for Solving the Problem As one solution to this problem, the present inventors have found that in an insulated gate field effect transistor, the channel length (the distance between the source region and the drain region) is determined by the channel length of the gate electrode. By making the gate electrode longer than the length in the direction, an offset region where no electric field is applied by the gate electrode or a very weak offset region is formed in a portion of the channel region which is in contact with the source region or the drain region. It was found that characteristics were taken.

FIG. 1 shows a basic configuration of the present invention. A blocking layer 104 is provided on an insulating substrate 105, and a source region 100 and a drain region 10 are formed thereon as semiconductor layers.
1 and a channel region 109 are provided. On the channel region 109, a gate insulating film 110 and a gate electrode 111 on which an oxide layer 112 as an insulating layer is formed by anodizing a material capable of being anodized are formed. A source electrode 102 in contact with the source region and the drain region,
A drain electrode 103 is provided. FIG. 1 shows a state in which no interlayer insulator is provided. However, if a parasitic capacitance between the gate electrode / wiring and the source / drain electrode / wiring becomes a problem, the interlayer insulator is provided as before. It may be provided, examples of which are described below in Examples 1-3.

As shown in FIG. 1, a material capable of anodic oxidation is selected for a gate electrode portion serving as a gate electrode 111 and an oxide layer 112, and the surface portion thereof is anodized to form an oxide layer 112. The distance between the source region 100 and the drain region 101, which is an ion-implanted region, that is, the channel length 108 is approximately twice as long as the thickness of the oxide layer 112 than the substantial length of the gate electrode 111 in the channel length direction. Become. The material of the gate electrode portion is mainly titanium (Ti), aluminum (Al), tantalum (T
a), chromium (Cr), silicon (Si) alone, or an alloy thereof is suitable.

As a result, in the portions 106 and 107 in the channel region 109 which face the oxide layer 112 formed on both side surfaces of the gate electrode via the gate insulating film 110, no electric field is applied by the gate electrode or the gate electrode is Very weak compared to the vertically lower part. Hereinafter, such regions 106 and 107 are referred to as offset regions, particularly when they have the same degree of crystallinity and impurity concentration as the channel region.

The regions 106 and 107 may be made of an amorphous material doped with impurities. Strictly speaking, the regions 106 and 107 only need to have lower crystallinity than the source region 100 and the drain region 101 adjacent thereto. For example, if the regions 100 and 101 are made of polycrystalline silicon having large crystal grains, the regions 106 and 107 may be amorphous silicon or so-called semi-amorphous silicon having slightly better crystallinity than amorphous silicon. Region 100, 1
If 01 is semi-amorphous silicon, region 10
6 and 107 may be amorphous silicon. Of course, it is necessary to take sufficient measures for such amorphous materials to exhibit semiconductor electrical characteristics.For example, these dangling bonds should be sufficiently hydrogen or halogen so as to minimize the number of dangling bonds. Need to be terminated.

By providing such an amorphous region, as shown in FIG. 9A, good TFT characteristics could be exhibited. FIG. 9B shows a thin film transistor (TFT) having a conventional insulated gate transistor structure. As is clear from the drawing, a remarkable reverse leakage current was observed in the conventional method, but the present invention is not limited thereto. like,
By providing a region that is substantially amorphous,
The properties have been improved. That is, providing the impurity region in the amorphous state has the same effect as providing the offset region described above.

The reason why the characteristics are improved by providing the amorphous region as described above has not yet been well understood. For one thing, in the non-crystalline region, the ionization rate of the added impurity element is lower than that in the crystalline region, so that even if the same amount of impurity is added, the amorphous region has a lower impurity concentration. It is presumed that, because of the behavior as if, a region substantially the same as a so-called lightly-doped-drain (LDD) was formed. For example,
In the amorphous state, silicon has an ionization rate of 0.1 to 10% at room temperature, which is significantly smaller than that of a single crystal or polycrystalline semiconductor (almost 100%).

Alternatively, the band gap is larger in the non-crystalline state than in the crystalline state, which may be the cause. For example, it can be explained from the energy band diagrams as shown in FIGS. 9 (e) and 9 (f). In an ordinary LDD transistor, the energy band diagrams of the source / channel / drain are as shown in FIGS. 9C and 9D. The bulge in the center is the channel region. The step-like portion is an LDD region. When no voltage is applied to the gate electrode, as shown in FIG. 9C, when a large negative voltage is applied to the gate electrode,
The result is as shown in FIG. At this time, there are forbidden bands between the source and the channel region and between the channel region and the drain, and carriers such as electrons and holes cannot move. However, hopping occurs due to tunneling or trap levels in the band gap. The carrier jumps over the gap. In the case of a normal TFT having no LDD structure, the current flows more easily because the width of the gap is smaller. This is considered a reverse leak. This decrease is particularly remarkable in TFTs. This is presumed to be because TFT is an inhomogeneous material such as polycrystal and has many trap levels due to grain boundaries and the like.

On the other hand, when the band gap of the LDD region is increased, such reverse leakage is reduced. FIGS. 9E and 9F show examples in which the LDD has a large band gap.
Is shown in FIG. 9E shows a state where no voltage is applied to the gate, and FIG. 9F shows a state where a large negative voltage is applied to the gate. As apparent from (f), the source and channel regions when a negative voltage is applied as compared with (d),
Alternatively, the width of the gap between the channel region and the drain is large. Tunneling is significantly affected by the width of the tunnel barrier (in this case the width of the gap), with a small increase in the width of the gap significantly reducing its probability. In addition, hopping via a local level is also a complex tunnel effect, so that the probability decreases dramatically as the gap width increases. For the above reasons, it is considered significant to form an LDD region having a large band gap. The band gap of polycrystalline silicon is 1.1 eV, whereas the band gap of amorphous silicon is 1.5 to 1.8 eV. It is extremely difficult to use a material having such a wide band gap for LDD. Ideal.

According to the present invention, in order to manufacture a semiconductor device having the above-mentioned offset region, in particular, a semiconductor layer serving as a source, a drain and a channel region and a gate insulating film layer 110 are formed, and then a gate electrode portion is formed of a material which can be anodized. Is formed, a source region 100 and a drain region 101 are formed by implanting impurity ions for making the semiconductor layer p-type or n-type, and then the surface of the gate electrode portion is anodized to oxidize with the gate electrode 111. Material layer 1
12 may be formed and a heat treatment step or the like may be performed.

Alternatively, after the formation of the semiconductor layer and the gate insulating film layer 110, a gate electrode portion is formed of an anodic oxidizable material, and then the surface portion of the gate electrode portion is anodized to form the gate electrode 111 and the oxide layer 112. Forming
Thereafter, a heat treatment process may be performed after the source region 100 and the drain region 101 are formed by implanting impurity ions to make the semiconductor layer p-type or n-type.

By performing the above-described steps, an insulated gate field effect transistor having a channel length longer than the length of the gate electrode in the channel length direction can be easily and reliably formed without causing a variation in performance due to a mask shift or the like. Can be manufactured.

Alternatively, in order to manufacture a semiconductor device of the present invention having an amorphous region, a semiconductor layer serving as a source, a drain, and a channel region and a gate insulating film layer 110 are formed.
After forming the gate electrode portion with a material that can be anodized after formation, impurity ions for making the semiconductor layer p-type or n-type are implanted into the semiconductor layer to cause the semiconductor layer to be non-crystallized. The region 101 and the non-crystalline regions 106 and 107 adjacent to the region 101 are formed, and then the surface of the gate electrode portion is anodized to form the gate electrode 111 and the oxide layer 112. At this time, the surface of the gate electrode recedes due to oxidation. Thereafter, only the source region 100 and the drain region 101 may be recrystallized in a self-aligned manner by using, for example, a laser annealing method or a flash lamp annealing method using the gate electrode portion as a mask. Here, the term "self-aligned" means that since the gate electrode portion is shaded, the impurity region existing thereunder cannot be recrystallized.

For example, when the ion implantation method is used, the spread of the impurity region due to the secondary scattering of ions is as follows.
It can be calculated by the ion acceleration energy, etc.
Since the retreat of the gate electrode is determined by the thickness of the oxide layer, this is also included as a design item. Therefore, in the present invention, the positional relationship between the gate electrode and the impurity region can be optimized by a precise design.
That is, the thickness of the oxide layer can be controlled with an accuracy of 10 nm or less, and the secondary scattering at the time of ion implantation can be controlled to the same degree. Therefore, this positional relationship can be manufactured with an accuracy of 10 nm or less. .

As described above, in the present invention, precise mask alignment is not newly required, and the present invention rarely lowers the yield. Furthermore, the improvement in the characteristics of the transistor obtained by the present invention is significant. Conversely, by using the anodic oxidation technique, defects could be significantly reduced. Especially the maximum process temperature is 1000 ° C or less, usually 500 ~
T at 850 ° C., a so-called low-temperature process
In the FT, leak defects between the gate electrode and the source / drain (hereinafter, referred to as gate leak) were significantly reduced. On the other hand, in a high-temperature process in which a gate oxide film is formed by a thermal oxidation method (the maximum process temperature is 1000 ° C. or higher), no remarkable improvement was observed. This is understood as follows.

That is, since a thermal oxide film cannot be used as a gate insulating film in a low-temperature process, the gate insulating film is usually formed by various CVD methods or sputtering methods. However, the insulating film deposited by such a method (gas phase method) has many pinholes. This was not the case with the thermal oxide film. That is, the thermal oxidation could completely cover the semiconductor surface with the oxide film.

Therefore, if a gate electrode is formed on an insulating film deposited by a vapor phase method, the channel region comes into contact with the gate electrode via these pinholes, and leakage occurs.

To avoid such difficulties, it is conceivable to increase the thickness of the gate oxide film. However, in that case, a new problem such as an increase in the threshold voltage or an increase in the S value is caused. .

However, such difficulty is naturally solved by the anodic oxidation method. FIG. 15 shows the process. That is, as shown in FIG. 15A, in a normal low-temperature process, a semiconductor layer 152 is formed on a substrate 151, and an insulating layer 153 serving as a gate insulating film is formed to cover the semiconductor layer 152. Since this insulating film is formed by the vapor phase method, there are many pinholes 154.

Then, the gate electrode 155 is formed on such an imperfect insulating film. In the present invention, thereafter, a voltage is applied to the gate electrode in an electrolytic solution to perform anodic oxidation. However, in this process, a current flows through various paths as shown in FIG. 15B, in addition to the current flowing directly to the gate electrode, without care. A part of the semiconductor layer 15 is removed from the insulating film 153 and the pinhole 154.
2, and further reaches the gate electrode 155 through an insulating film below the gate electrode 155 and its pinhole. In particular, it is known that when a current flows through a semiconductor layer, various defects existing in the semiconductor layer are cured. (For example, Japanese Patent Publication No. 3-19694 filed by the present inventors)

The gate electrode material (aluminum or the like) in the portion of the pinhole was in contact with the semiconductor layer, but is considered to be oxidized in this process. Although the origin of the oxygen is not clear, it is presumed that it is an oxygen atom contained in the semiconductor layer. Certainly, the concentration of oxygen in the semiconductor layer was lower than that at the time of film formation, and it was apparent that oxygen atoms were moved by anodic oxidation. For these reasons, when the gate electrode was made of aluminum, the pinholes were actually completely filled with aluminum oxide and disappeared. In addition, even though not as much as a pinhole, current flows intensively in a thin part of the insulating film, and as a result, more oxygen atoms are attracted to that part and the thickness of the insulating film may be leveled. did it. That is, the gate insulating film below the gate electrode is made of silicon oxide and aluminum oxide.

FIG. 15C shows this state. That is, the pinhole is filled with the anodic oxide 157. Here, it should be noted that the anodic oxide varies from place to place. That is, the lower part of the gate electrode is mainly aluminum oxide, and the other part is mainly silicon oxide.

The characteristics of the interface between the oxide and the semiconductor formed in such an anode are generally poor.
That is, various fixed charges exist in such an anodic oxide, and the localized level density at the interface between the anodic oxide and the insulating film is extremely high. Therefore, as shown in FIG. 15C, a region 158 where the conductivity type of the semiconductor cannot be controlled exists in the semiconductor layer below such an anodic oxide.

However, in the present invention, the place where the anodic oxide exists in the insulating film (that is, the place where the pinhole exists) does not necessarily exist continuously from the source to the drain. When viewed as a TFT as a whole, there is no problem.

By this effect, the thickness of the gate insulating film can be made as thin as 20 to 50 nm, and a higher yield than before can be obtained. This effect will be apparent when considering that the conventional method absolutely requires 100 nm or more to prevent gate leak.

This effect further inhibits the gate leak positively, and prevents aluminum ions (chemical formula) between the gate insulating film and the gate electrode so that foreign elements such as mobile ions do not enter the semiconductor layer from the gate electrode. AlO _x (1 <
x ≦ 1.5, preferably 1.2 <x ≦ 1.5) or silicon nitride (chemical formula SiN _x (1 <x ≦ 4/3, preferably 1.
The same was observed when a barrier layer made of a film such as 2 <x ≦ 4/3) was provided. Since such an aluminum oxide or silicon nitride film is usually formed by a gas phase method,
I had the above problem. Therefore, if
If a pinhole is present in the barrier layer, it is feared that mobile ions as well as gate leaks may penetrate through the pinhole. However, according to the present invention, the pinhole can be filled with an oxide of these materials, particularly by forming the gate electrode from a material such as aluminum, titanium, and tantalum and anodizing the material, and Oxide showed excellent barrier properties and did not cause any problems.

Such an effect of reducing pinholes is not immediately visible and can be observed only in the form of a reduction in defects due to gate leak. Moreover, it is difficult to simply compare with a conventional process. Because, in the present invention, the offset region and the LDD region are formed by a technique called anodic oxidation,
This is because the effect of improving the yield due to the effect must be considered. Examples are shown below,
It does not emphasize such effects on pinholes. It is noteworthy, however, that the pinhole defect can be unknowingly solved by employing the technique of anodic oxidation.

[0038]

【Example】

Example 1 In this example, a viewfinder for a video camera using a liquid crystal electro-optical device having a diagonal of 1 inch was manufactured, and the present invention was implemented.

In this embodiment, a viewfinder was formed by forming a device having a structure of the present invention using a high mobility TFT (thin film transistor) having a structure of 387 × 128 and a low-temperature process having the structure of the present invention. FIG. 7 shows an arrangement of active elements on a substrate of a liquid crystal display device used in this embodiment, and FIG. 6 shows a circuit diagram of this embodiment. FIG. 8 illustrates a manufacturing process showing the AA ′ cross section and the BB ′ cross section of FIG. AA 'section shows NTFT, and BB'
The cross section shows the PTFT.

In FIG. 8A, an inexpensive glass substrate 4 that can withstand heat treatment at 700 ° C. or less, for example, about 600 ° C.
A silicon oxide film as a blocking layer 401 is formed on the metal oxide film 1000 by using a magnetron RF (high frequency) sputtering method.
It is made to a thickness of 3000 mm. Process condition is oxygen 1
00% atmosphere, deposition temperature 150 ° C, output 400-800
W, pressure 0.5 Pa. The film formation rate using quartz or single crystal silicon as a target was 30 to 100 ° / min.

A silicon film was formed thereon by an LPCVD (low pressure gas phase) method, a sputtering method, or a plasma CVD method. When formed by the reduced pressure gas phase method, the temperature is 1
450-550 ° C lower by 00-200 ° C, for example 530 ° C
CVD of disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ )
The film was supplied to the apparatus to form a film. Reactor pressure is 30 ~ 300
Pa. The deposition rate was 50-250 ° / min.
Threshold voltage (Vt) between PTFT and NTFT
In order to control substantially the same as in h), boron may be added at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ during film formation using diborane.

In the case of performing the sputtering method, the back pressure before the sputtering was set to 1 × 10 ⁻⁵ Pa or less, single-crystal silicon was used as a target, and an atmosphere in which 20 to 80% of hydrogen was mixed with argon was used. For example, argon was 20% and hydrogen was 80%.
The film formation temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

When a silicon film is formed by the plasma CVD method, the temperature is, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used. These were introduced into a PCVD apparatus, and a high-frequency power of 13.56 MHz was applied to form a film.

The coatings formed by these methods are:
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. If the oxygen concentration is high, it is difficult to crystallize, and the heat annealing temperature must be increased or the heat annealing time must be increased.
If the amount is too small, the lamp is turned off by the backlight.
Current increases. Therefore, 4 × 10 ¹⁹ to 4 × 10 ²¹
The range was cm ⁻³ . Hydrogen is 4 × 10 ²⁰ cm ^-3 and silicon 4
It was 1 atomic% when compared with × 10 ²² cm ⁻³ .

After the amorphous silicon film is formed to a thickness of 500 to 5000 °, for example, 1500 ° by the above method, a heat treatment at a temperature of 450 to 700 ° C. for 12 to 70 hours in a non-oxide atmosphere at a medium temperature is performed. For example, it was kept at a temperature of 600 ° C. in a hydrogen atmosphere. Since a silicon oxide film having an amorphous structure is formed on the surface of the substrate under the silicon film, no specific nucleus is present in this heat treatment, and the whole is annealed uniformly. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein.

By the annealing, the silicon film shifts from an amorphous structure to a highly ordered state, and a part of the silicon film exhibits a crystalline state. In particular, a region having a relatively high order in a state after the formation of silicon is particularly likely to be crystallized to be in a crystalline state. However, since the silicon existing between these regions is bonded to each other, silicon mutually pulls each other. When measured by laser Raman spectroscopy, a single crystal silicon peak 522 is obtained.
A peak shifted to a lower frequency side than cm ⁻¹ is observed. Its apparent particle size is 50 to 5 when calculated from the half width.
Although it is a microcrystal with a size of 00Å, there are actually a large number of regions with high crystallinity and a cluster structure, and a semi-amorphous structure film in which each cluster is bonded to each other by silicon (anchoring). Could be formed.

As a result, the coating exhibits a state substantially free of grain boundaries (hereinafter referred to as GB). Carriers can easily move from one cluster to another through anchored locations, resulting in higher carrier mobility than so-called GB polycrystalline silicon. That is, hole mobility (μh) = 10 to ²⁰⁰ cm ² /
VSec, electron mobility (μe) = 15 to 300 cm ² / V
Sec is obtained.

On the other hand, the coating may be polycrystallized by high-temperature annealing at 900 to 1200 ° C. instead of annealing at the above-mentioned medium temperature. However, in this case, the coating in the coating is formed by solid phase growth from nuclei. Impurity segregation occurs, GB has oxygen,
Impurities such as carbon and nitrogen increase, and the mobility in the crystal is high. However, a barrier is formed in GB to hinder the movement of carriers there. As a result, 10 cm ² / Vsec
It is a fact that the above mobility is not easily obtained. For this purpose, the concentration of impurities such as oxygen, carbon, nitrogen, etc., needs to be reduced from several tenths to several tenths than semi-amorphous ones. In such a case, 50-100 cm ² / Vse
c was obtained.

The silicon film formed as described above was subjected to photoetching to produce a semiconductor layer 402 for NTFT (channel width 20 μm) and a semiconductor layer 404 for PTFT.

On this, a silicon oxide film 4 serving as a gate insulating film is formed.
03 was formed to a thickness of 500 to 2000 {for example, 1000}. This was made under the same conditions as those for forming the silicon oxide film as the blocking layer. A small amount of fluorine may be added during film formation to fix sodium ions.

Thereafter, a tantalum film was formed on the upper side. This was patterned using a photomask, and FIG.
(B) was obtained. A gate insulating film 405 for NTFT and a gate electrode portion 406 were formed, and the length in the channel length direction was 10 μm, that is, the channel length was 10 μm. Similarly, a gate insulating film 407 for PTFT and a gate electrode portion 4
08 were formed, and the length in the channel length direction was 7 μm, that is, the channel length was 7 μm. The thickness of both the gate electrode portions 406 and 408 was set to 0.8 μm. In FIG. 8C, boron (B) was added to the PTFT source 409 and the drain 410 at a dose of 1 to 5 × 10 ¹⁵ cm ⁻² by ion implantation. Next, FIG.
As shown in (D), a photoresist 411 was formed using a photomask. Phosphorus (P) was added by ion implantation at a dose of 1 to 5 × 10 ¹⁵ cm ^{−2 as} a source 412 and a drain 413 for the NTFT.

Thereafter, the gate electrode was anodized. L-tartaric acid was diluted in ethylene glycol at a concentration of 5%, and the pH was adjusted to 7.0 ± 0.2 with ammonia. The substrate was immersed in the solution, the positive side of the constant current source was connected, the platinum electrode was connected to the negative side, a voltage was applied at a constant current of 20 mA, and the oxidation was continued until the voltage reached 150V. Further, 0.1 mA is applied at a constant voltage at 150 V.
The oxidation was continued until: Thus, the tantalum oxide layer 414 is formed on the surfaces of the gate electrode portions 406 and 408.
Was formed to obtain a gate electrode 415 for NTFT and a gate electrode 416 for PTFT. The tantalum oxide layer 414 was formed to a thickness of 0.3 μm.

Next, annealing was performed again at 600 ° C. for 10 to 50 hours. The source 412 and the drain 413 of the NTFT and the source 409 and the drain 410 of the PTFT were formed as N ⁺ and P ⁺ by activating impurities. The channel formation region 41 is formed under the gate insulating films 405 and 407.
7, 418 are formed as semi-amorphous semiconductors.

In this manufacturing method, the order of ion implantation of impurities and anodic oxidation around the gate electrode may be changed. Since the insulating layer made of metal oxide is formed around the gate electrode in this way, the substantial length of the gate electrode is twice the thickness of the insulating film than the channel length.
The length was shortened by 6 μm, and by providing an offset region where an electric field was not applied, it was possible to reduce the leak current at the time of reverse bias.

In this embodiment, the thermal annealing is performed as shown in FIG.
(E) was performed twice. However, the annealing in FIG. 8A may be omitted depending on the desired characteristics, and both may be replaced by the annealing in FIG. 8E to shorten the manufacturing time. In FIG. 8E, the interlayer insulator 419 is formed as a silicon oxide film by the above-described sputtering method. This silicon oxide film may be formed by an LPCVD method, a photo CVD method, or a normal pressure CVD method. The interlayer insulator is 0.2 to 0.6 μm, for example, 0.3
Then, a window 420 for an electrode was formed using a photomask. Further, as shown in FIG. 8F, aluminum is formed on the entire surface by sputtering, and the leads 421 and 423 and the contacts 422 are formed using a photomask. Coating and forming a functional polyimide resin,
The electrode drilling was performed again using a photomask.

An ITO (indium tin oxide film) was formed by a sputtering method so that the two TFTs had a complementary structure and their output terminals were connected to an electrode of one pixel of the liquid crystal device as a transparent electrode. It was etched using a photomask to form an electrode 425. This IT
O was deposited at room temperature to 150 ° C., and was achieved by oxygen at 200 to 400 ° C. or annealing in air. Thus, the NTFT 426, PTFT 427, and transparent conductive electrode 425 were formed on the same glass substrate 401. The electrical characteristics of the obtained TFT are PTFT and the mobility is 20.
(Cm ² / Vs), Vth was −5.9 (V), and the mobility of NTFT was 40 (cm ² / Vs) and Vth was 5.0 (V).

One substrate for a liquid crystal device was manufactured according to the method described above. The arrangement of the electrodes and the like of this liquid crystal display device is shown in FIG. NTFT 426 and PTFT 42
7 is provided at the intersection of the first signal line 428 and the second signal line 429. A matrix configuration using such a C / TFT is provided. The NTFT 426 has a drain 413
The gate 406 is connected to a signal line 428 on which a multi-layer wiring is formed. The output terminal of the source 412 is connected to the electrode 425 of the pixel via the contact 422.

On the other hand, the PTFT 427 has the input terminal of the drain 410 connected to the second signal line 429 via the lead 423, the gate 408 connected to the signal line 428, and the source 409.
Is connected to the pixel electrode 425 through the contact 422 in the same manner as the NTFT. The present embodiment is configured by repeating such a structure left, right, up and down.

Next, as a second substrate, ITO (injection) was formed on a substrate having a silicon oxide film laminated thereon by 2,000 .ANG.
Tin oxide film). This ITO is between room temperature and 15
Films were formed at 0 ° C. and achieved with oxygen at 200-400 ° C. or in air. In addition, a color filter was formed on this substrate to form a second substrate.

Thereafter, a 6: 4 mixture of an ultraviolet curable acrylic resin and a nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. The pitch of the leads on the substrate is 46 μm
Therefore, the connection was performed using the COG method. In this embodiment, a method is used in which gold bumps provided on an IC chip are connected with an epoxy-based silver-palladium resin, and the IC chip and the substrate are filled and fixed with an epoxy-modified acrylic resin for fixing and sealing. Was. Thereafter, a polarizing plate was attached on the outside to obtain a transmission type liquid crystal display device.

[Embodiment 2] FIG. 10 is a sectional view of this embodiment. First, as a substrate 501, Corning 7059
Glass was used. Then, the underlying silicon oxide film 502
Was formed with a thickness of 100 nm by a sputtering method.
Further, the amorphous silicon film 503 is plasma-C
Only 50 nm was formed by the VD method. On top of that, a silicon oxide film 504 was formed to a thickness of 20 nm also by the sputtering method for the purpose of protecting the amorphous silicon film. This was annealed at 600 ° C. for 72 hours in a nitrogen atmosphere and recrystallized. Further, this was patterned by a photolithography method and a reactive ion etching (RIE) method to form an island-shaped semiconductor region as shown in FIG. After forming the island-shaped semiconductor region, the protective silicon oxide film 504 was removed. For the removal, wet etching was performed using buffered hydrofluoric acid (a solution in which hydrogen fluoride and ammonium fluoride were mixed). Examples of the buffer hydrofluoric acid include high-purity hydrofluoric acid (50 wt%) for semiconductor production and an ammonium fluoride solution (40 wt%).
%) In a ratio of 1:10. In addition,
The etching rate of this buffer hydrofluoric acid with respect to silicon oxide is 70 nm / min.
nm / min, and 15 nm / min for aluminum.

Further, a gate oxide film 505 is formed by a sputtering method in an oxygen atmosphere targeting silicon oxide.
Was deposited to a thickness of 115 nm. In this state, phosphorus ions were doped into the gate oxide film 505 by a plasma doping method. This is to getter mobile ions such as sodium existing in the gate oxide film and need not be performed when the concentration of sodium is low enough not to hinder the operation of the device. In this example, the plasma acceleration voltage was 10 keV and the dose was 2 × 10 ¹⁴ cm ⁻² . Then, annealing was performed at 600 ° C. for 24 hours, and an oxide film generated by the impact of plasma doping,
The damage of the silicon film was recovered.

Next, an aluminum film was formed by a sputtering method, and this was patterned with a mixed acid (a phosphoric acid solution to which 5% nitric acid was added) to form a gate electrode / wiring 506. The etching rate was 225 nm / min when the etching temperature was 40 ° C.
Thus, the outer shape of the TFT was adjusted. At this time, the channel had a length of 8 μm and a width of 20 μm.

Next, an N-type impurity region (source, drain) 507 was formed in the semiconductor region by ion implantation. Phosphorus ions are used as the dopant, the ion energy is 80 keV, and the dose is 5 × 10 ¹⁵ cm ^−2.
And As shown in the figure, the doping was performed by a through-implant in which an impurity was implanted through the oxide film. The advantages of using such a through implant are:
This means that the surface of the impurity region is kept smooth during recrystallization by laser annealing. If the substrate is not through-implanted, a large number of crystal nuclei are generated on the surface of the impurity region during recrystallization, and irregularities are generated on the surface.
Thus, a structure as shown in FIG. 10B was obtained. Naturally, the crystallinity of the portion into which the impurities are implanted is remarkably degraded by such ion implantation, and is substantially in an amorphous state (amorphous state or a polycrystalline state close thereto).

Further, electricity was passed through the wiring 506, and an aluminum oxide film 508 was formed around the gate electrode and the wiring (upper surface and side surfaces) by anodic oxidation. Anodization is performed by adding 3% tartaric acid solution in ethylene glycol to 5%.
This was performed using a solution that was neutralized with ammonia to a pH of 7.0 ± 0.2. First, platinum is immersed in a solution as a cathode, and further, the TFT is immersed in the substrate together with the wiring 506.
Was connected to the anode of the power supply. The temperature was kept at 25 ± 2 ° C.

In this state, a current of 0.5 mA / cm ^{2 was} first passed, and when the voltage reached 200 V, current was supplied while the voltage was kept constant. When the current reached 0.005 mA / cm ² , Was stopped, and the anodic oxidation was terminated. The thickness of the anodic oxide film thus obtained was about 250 nm. This is shown in FIG.

Thereafter, laser annealing was performed.
As a laser, a KrF excimer laser is used.
A laser pulse with a power density of 50 mJ / cm ²
Shot irradiation was performed. It has been confirmed that the crystallinity of amorphous silicon can be restored to withstand TFT operation by at least one laser irradiation, but the probability of occurrence of defects due to fluctuations in laser power has been sufficiently reduced. For this purpose, a sufficient number of laser irradiations is desirable. However, too many laser irradiations will reduce productivity,
It became clear that about ten times used in this example is most desirable.

The laser annealing was performed under atmospheric pressure in order to enhance mass productivity. Since a silicon oxide film has already been formed on the impurity region, there has been no particular problem. If laser annealing is performed in a state where the impurity region is exposed, oxygen enters the impurity region from the air at the same time as crystallization, and the crystallinity is not good, so that a TFT having sufficient characteristics cannot be obtained. Was. For this reason, it is necessary to perform laser annealing in a vacuum on the substrate where the impurity region is exposed.

Further, in the present embodiment, as shown in FIG. 10D, the laser light was made to enter obliquely. For example, in the present embodiment, the laser light was irradiated at an angle of 10 ° with respect to the normal to the substrate. The angle is determined according to the design specifications of the element to be manufactured. By doing this,
The region to be crystallized among the impurity regions can be made asymmetric by the laser. That is, region 5 in the figure
09 and 510 are impurity regions that have been sufficiently crystallized.
The region 511 is not an impurity region but is a region crystallized by a laser beam. The region 512 is an impurity region but is not crystallized. For example, on the drain side where hot electrons are likely to be generated, FIG.
The impurity region on the right side of 0 (D) may be used.

Thus, the shape of the element was adjusted. Thereafter, as usual, an interlayer insulator is formed by sputter deposition of silicon oxide, an electrode hole is formed by a known photolithography technique, and the surface of the semiconductor region or the gate electrode / wiring is exposed. Then, a metal film was selectively formed to complete the device.

Example 3 T obtained by the present invention
In the FT, not only the off-state current but also the withstand voltage between the source and the drain and the operation speed change depending on the width of the amorphous semiconductor region or the offset region. Therefore, for example, by optimizing parameters such as the thickness of the anodic oxide film and the ion implantation energy, it is possible to manufacture a TFT suitable for the purpose. However, these parameters are generally not adjustable for individual TFTs formed on a single substrate. For example, in an actual circuit, low-speed operation may be performed on one substrate,
FT and TFT requiring low breakdown voltage but requiring high-speed operation
May be desired to be formed simultaneously. In general, in the present invention, as the width of the offset region or the width of the amorphous impurity semiconductor region is larger, the off-state current is smaller and the breakdown voltage is improved, but there is a disadvantage that the operation speed is reduced.

This embodiment shows an example for solving such a problem. This embodiment is shown in FIG. 11 (top view) and FIG. 12 (cross-sectional view). In this embodiment, Japanese Patent Application No. 3-29633
The present invention relates to the fabrication of a circuit used in an image display method in which a P-channel TFT and an N-channel TFT are used to drive one pixel (such as a liquid crystal pixel) as described in No. 1. Here, the N-channel TFT is required to have a high speed, and the withstand voltage does not matter much. On the other hand, the operation speed of the P-channel TFT does not matter so much, but the P-channel TFT needs to have a low off-current and, in some cases, a good withstand voltage. Therefore, N channel T
FT has a thin anodic oxide film (20 to 100 nm), and P-channel TFT has a thick anodic oxide film (250 to 400 nm).
It is desired. Hereinafter, the manufacturing process will be described.

As in the case of Embodiment 2, Corning 705
9 was used as a substrate 601, an N-type impurity region 602, a P-type impurity region 603, a gate insulating film 604, and gate electrodes / wirings 606 and 607 were formed. Both the gate electrode and the wiring are connected to the wiring 650. (FIG. 11A, FIG. 1
2 (A))

Further, gate electrodes and wirings 606 and 607
Then, aluminum oxide films 613 and 614 were formed around the gate electrodes / wirings 606 and 607 (upper and side surfaces) by anodizing. Anodization was performed under the same conditions as in Example 2. However, the maximum voltage is 5
It was set to 0V. Therefore, the thickness of the anodic oxide film manufactured in this step is about 60 nm. (FIG. 12 (B))

Next, as shown by 651 in FIG. 11B, the gate electrode / wiring 606 was separated from the wiring 650 by laser etching. Then, in this state, anodic oxidation was started again. The conditions were the same as before, but at this time the maximum voltage was increased to 250V. As a result, no current flowed through the wiring 606, so that no change occurred. However, since the current flowed through the wiring 607, an aluminum oxide film having a thickness of about 300 nm was formed around the gate wiring 607. (FIG. 12 (c))

Thereafter, laser annealing was performed.
The conditions were the same as in Example 2. In this case, in the N-channel TFT (left side in FIG. 12), the width a ₁ of the amorphous region and the offset region is so small that it can be ignored.
If the surface of the aluminum wiring was not covered with the anodic oxide film, the laser light irradiation would cause significant damage. Therefore, even if it was thin, it was necessary to form the anodic oxide film. On the other hand, a P-channel TFT (right side in FIG. 12)
Has a thickness of the anodic oxide film of 300 nm and an amorphous region of 150 to 200 nm. Further, it is estimated that the width a ₂ of the offset region was 100 to 150 nm.
(FIG. 12 (D))

As in the case of the second embodiment, a necessary portion of the aluminum wiring is etched by laser irradiation in the air, and the gate electrode of the P-channel TFT is connected to the wiring 60.
7 and the wiring 650 was cut. further,
An interlayer insulating film was formed, a contact hole was formed, and wirings 624 and 611 were formed. Thus, a circuit was formed.

In the circuit fabricated in this manner, the N-channel TFT had a small width of the offset region and the non-crystalline region and a slightly large off-state current, but was excellent in high-speed operation. On the other hand, the P-channel TFT has difficulty in high-speed operation, but has a small off-current and has an excellent ability to hold the electric charge accumulated in the pixel capacitor.

As described above, T with different functions is provided on one substrate.
There are other cases where the FT must be integrated. For example, in a liquid crystal display driver, a high-speed TFT is used for a logic circuit such as a shift register, and a high-voltage TFT is used for an output circuit.
FT is required. T corresponding to such conflicting objectives
The method described in this embodiment is effective for manufacturing an FT.

Example 4 Using the manufacturing method used in Example 1 of the present invention, an active matrix circuit composed of N-channel TFTs as shown in FIG. 13 was manufactured. In other words, this active matrix has a gate line 7
01 and a matrix of data lines 702, each of which is made of low-resistance aluminum.
m of aluminum oxide. These line widths were 2 μm. The thickness was 0.5 μm. Further, the gate line is provided with a gate electrode 703 of the TFT of each pixel. This is likewise coated with aluminum oxide. A semiconductor layer 704 is formed under the gate electrode, and the N-channel TF of the first embodiment is formed.
Like T, there is an N-type polycrystalline impurity region doped with phosphorus, and the offset region, which is a feature of the present invention, is designed to have a width of about 200 to 400 nm. The source of this semiconductor layer is the data line 70
2 while the drain is connected to the display pixel electrode (made of ITO) 70 through the aluminum electrode 705.
6 is connected.

FIG. 14 shows a circuit diagram of the active matrix element manufactured in this embodiment, the operation of the element of this embodiment, and the operation of an element using a TFT manufactured by a conventional method for comparison. Things. As mentioned earlier,
In the matrix of such a structure, ends the charging of the capacitor C _LC, when the gate voltage becomes OFF state, capacitor C _LC via the parasitic capacitance C _GD of the gate and the drain, the gate line and the capacitance It is known that the voltage is coupled and the voltage drops by ΔV from the charging voltage. This phenomenon is the same even in a circuit in which an N-channel TFT and a P-channel TFT are connected in parallel as in the first embodiment. For details, refer to Japanese Patent Application No.
-208648.

[0082] In the circuit including only N-channel or P-channel either TFT as shown in FIG. 14, the voltage drop [Delta] V is represented by _{ΔV = C GD · V G /} (C LC + C GD). Here, the V _G, ON of the gate voltage
This is the fluctuation range from the voltage to the OFF voltage. For example, in a TFT manufactured without using self-alignment, the parasitic capacitance C _GD is remarkably large, so that ΔV becomes large. To overcome this, a storage capacitance _CAD is formed in parallel with the pixel capacitor as shown in FIG. Then, apparently, the capacitance of the pixel capacitor was increased. However, such measures have not essentially solved the problem, and have caused new problems such as a decrease in aperture ratio, as described above.

Even if the device is manufactured by the self-alignment method,
This voltage drop becomes a serious problem when the size of the pixel becomes small and the parasitic capacitance of the TFT cannot be ignored compared to the pixel capacitor. For example, in a 3-inch diagonal high-vision compatible panel (for projection), the pixel capacitance is as small as 13 fF. On the other hand, when the TFT is manufactured by adopting the 2 μm rule in the process, the aspect ratio of the wiring is large, and parasitic capacitance is generated in a three-dimensional geometry even if there is no longer a planar overlap. fF. That is, it reaches 10% or more of the capacity of the pixel capacitor.

FIG. 14 (A) shows an example of an active matrix using a conventional TFT. Obviously, ΔV makes it impossible to display as originally expected. That is,
In order to operate a TFT at high speed, the gate voltage is required to be higher than the drain voltage. Usually, a voltage about twice the drain voltage is adopted as the gate voltage. Therefore, if the drain voltage is 5V, the gate voltage is 10V or more. Further, when the gate voltage is made negative in the OFF state for the purpose of perfecting the operation of the TFT, the change in the gate voltage becomes larger. For example, in the case of FIG. 14, although the drain voltage is an alternating current of ± 6 V, the gate voltage is +12 V in the ON state and −4 V in the OFF state, so that V _G = 1 in the above equation.
6V. If the parasitic capacitance is 2 fF, FIG.
ΔV is 2 V, which is 1/3 of the drain charging voltage as shown in FIG. Of course, the electric charge stored in the pixel is discharged by the natural discharge, so that it is actually difficult to ideally perform the display. In order to avoid such a problem, it is necessary to provide a storage capacitor at the expense of the aperture ratio.

On the other hand, when the present invention is applied, the parasitic capacitance can be significantly reduced. Specifically, it can be 0.1 fF or less. Therefore, ΔV can be almost ignored as shown in FIG. Furthermore, in the present invention, O
Since the FF current is smaller by about one digit than that of a TFT manufactured by a conventional method, spontaneous discharge is much slower, and extremely ideal display can be performed.

[Embodiment 5] FIG. 16 is a sectional view showing a manufacturing process of this embodiment. Note that detailed conditions of the present embodiment are almost the same as those of the first or second embodiment, and thus will not be described in detail. First, N-0 glass manufactured by NEC Corporation was used as the substrate 1601. Although this glass has a high strain temperature, it is rich in lithium and also contains significant amounts of sodium. Therefore, in order to prevent invasion of these mobile ions from the substrate, plasma CVD is performed.
The silicon nitride film 1602 to a thickness of 1
It is formed only from 0 to 50 nm. Further, a silicon oxide film 1603 as a base was formed with a thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed thereon by plasma CVD to a thickness of 20 to 100 nm, and annealed at 600 ° C. for 12 to 72 hours in a nitrogen atmosphere to crystallize. Further, this is patterned by a photolithography method and a reactive ion etching (RIE) method to form island-shaped semiconductor regions 1604 (for N-channel TFT) and 1605 as shown in FIG.
(For a P-channel TFT).

Further, a gate oxide film 160 is formed by a sputtering method in an oxygen atmosphere targeting silicon oxide.
6 was deposited with a thickness of 50-200 nm. Further, the silicon nitride film 1607 is formed by plasma CVD or low pressure CVD.
Depending on the method, a thickness of 2 to 20 nm, preferably 8 to 11 n
m.

Next, an aluminum film was formed by a sputtering method or an electron beam evaporation method, and this was patterned with a mixed acid (a phosphoric acid solution to which 5% nitric acid was added) to form gate electrodes and wirings 1608 to 1611. Thus, the outer shape of the TFT was adjusted.

Further, in the electrolytic solution, the gate electrode / wiring 1
The current is passed through 608 to 1611 and by anodization method,
Aluminum oxide films 1612 to 1615 were formed. As the conditions of the anodic oxidation, the method described in Example 1 was employed. The state so far is shown in FIG.

Next, the semiconductor region 1604 is doped with an N-type impurity by a well-known ion implantation method.
5 was implanted with a P-type impurity to form an N-type impurity region (source and drain) 1616 and a P-type impurity region 1617. This process used a known CMOS technology. In addition, the gate electrode and reactive ion etching method
Silicon nitride 1607 other than the one existing under the wiring portion was removed. This step can be replaced by wet etching. At this time, the etching can be performed in a self-aligned manner using aluminum oxide as a mask by utilizing the difference in etching rate between aluminum oxide and silicon nitride, which are anodized films.

Thus, a structure as shown in FIG. 16D was obtained. Needless to say, the crystallinity of the portion into which the impurities are implanted by the previous ion implantation is remarkably deteriorated, and is substantially in an amorphous state (amorphous state or a polycrystalline state close thereto). Therefore, the crystallinity was recovered by laser annealing.
This step may be performed by thermal annealing at 600 to 850 ° C. The conditions for the laser annealing used were those described in Example 2. 250-4 after laser annealing
Annealing was performed in a hydrogen atmosphere at 50 ° C. (1 to 700 torr, preferably 500 to 700 torr) for 30 minutes to 3 hours, and hydrogen was added to the semiconductor region to reduce lattice defects (dangling bonds and the like).

Thus, the shape of the element was adjusted. Thereafter, as usual, an interlayer insulator 1618 is formed by sputter deposition of silicon oxide, an electrode hole is formed by a known photolithography technique, and the surface of the semiconductor region or the gate electrode / wiring is exposed, Lastly, a second metal film (aluminum or chromium) was selectively formed and used as electrodes / wirings 1619 to 1621. Here, the second metal wirings 1619 and 1621 cross over the first metal wirings 1608 and 1611. As described above, NTFT 1622 and PTFT 1623 were formed.

[Embodiment 6] FIG. 17 is a sectional view showing a manufacturing process of this embodiment. Note that detailed conditions of the present embodiment are almost the same as those of the first embodiment or the second embodiment, and thus will not be described in detail. First, N-0 glass manufactured by NEC Corporation was used as the substrate 1701, and a silicon nitride film 1702 having a thickness of 10 to 10 was formed by a plasma CVD method or a low pressure CVD method.
Only 50 nm was formed. Furthermore, the underlying silicon oxide film 1
703 was formed in a thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film is formed thereon by plasma CVD to a thickness of 20 to 100 nm,
Anneal in a nitrogen atmosphere at 600 ° C. for 12 to 72 hours to crystallize. Furthermore, pattern this,
As shown in FIG. 17A, an island-shaped semiconductor region 1704 is provided.
(For N-channel TFT) and 1705 (for P-channel TFT)
And).

Further, a gate oxide film 1706 having a thickness of 50 to 200 nm was deposited by a sputtering method. Further, an aluminum oxide film 1707 was deposited by a plasma CVD method or a sputtering method to a thickness of 2 to 20 nm, preferably 8 to 11 nm. The constituent elements of the aluminum oxide film are mainly oxygen and aluminum, and the ratio of oxygen: aluminum is approximately 1: 1.5.

Next, an aluminum film is formed by a sputtering method or an electron beam evaporation method, and the aluminum film is patterned, and gate electrodes and wirings 1708 to 1711 are formed.
Was formed. In this way, as shown in FIG.
The outer shape of the FT was adjusted.

Further, in the electrolytic solution, the gate electrode / wiring 1
The current is passed through 708 to 1711 and by anodizing method,
Aluminum oxide films 1712 to 1715 were formed. As the conditions of the anodic oxidation, the method described in Example 1 was employed. The state so far is shown in FIG.

Next, as shown in FIG. 17C, aluminum oxide 1707 and silicon oxide 1706 other than those existing under the gate electrode / wiring portion are removed by a reactive ion etching method, and the semiconductor region 1704 is removed. 170
5 was exposed. Further, the semiconductor region 1704 is doped with an N-type impurity and the semiconductor region 1705 is doped with a P-type impurity by the laser doping technique (Japanese Patent Application No. 3-283981) of the present inventors, and the N-type impurity is doped. Region (source, drain) 216 and P-type impurity region 2
17 was formed. This process used CMOS technology as described in Japanese Patent Application No. 3-283981.

Thus, a structure as shown in FIG. 17D was obtained. In the laser doping method, the implantation of the impurity and the annealing are performed at the same time, so that the steps of laser annealing and thermal annealing as in the first, second, and fifth embodiments are unnecessary. After laser doping,
250-450 ° C hydrogen atmosphere (1-700 torr,
Annealing is preferably performed at 500 to 700 torr for 30 minutes to 3 hours, and hydrogen is added to the semiconductor region.
Lattice defects (such as dangling bonds) have been reduced.

Thus, the shape of the element was adjusted. Thereafter, as usual, an interlayer insulator 1718 is formed by sputter deposition of silicon oxide, an electrode hole is formed by a known photolithography technique, and the surface of the semiconductor region or the gate electrode / wiring is exposed, Finally, a second metal film (aluminum or chromium) was selectively formed, and this was used as electrodes / wirings 1719 to 1721. As described above, NTFT 1722 and PTFT 1
723 could be formed.

[Embodiment 7] FIG. 18 is a sectional view showing a manufacturing process of this embodiment. Note that the detailed conditions of this embodiment are almost the same as those of the fifth and sixth embodiments, and therefore will not be described in detail. First, as the substrate 1801, Nippon Electric Glass N
-0 glass, plasma CVD or reduced pressure C
A silicon nitride film 1802 having a thickness of 10 to 50 nm was formed by the VD method. Further, an underlying silicon oxide film 1803 was formed by a sputtering method to a thickness of 100 to 800 nm. An amorphous silicon film is coated on the plasma CV
It was formed to a thickness of 20 to 100 nm by Method D, and was annealed at 600 ° C. for 12 to 72 hours in a nitrogen atmosphere for crystallization. Further, this is patterned, and FIG.
As shown in FIG. 12, an island-shaped semiconductor region 1804 (N-channel T
FT) and 1805 (for P-channel TFT).

Further, a gate oxide film 1806 having a thickness of 50 to 200 nm was deposited by a sputtering method. Further, the silicon nitride film 1807 is formed with a thickness of 2 to 20 nm, preferably 8 nm by a plasma CVD method or a low pressure CVD method.
Only １１11 nm was deposited.

Next, an aluminum film is formed by a sputtering method or an electron beam evaporation method, and the aluminum film is patterned, and gate electrodes and wirings 1808 to 1811 are formed.
Was formed. In this way, as shown in FIG.
The outer shape of the FT was adjusted.

Further, the gate electrode / wiring 1
Pass current through 808-1811 and anodize
Aluminum oxide films 1812 to 1815 were formed. As the conditions of the anodic oxidation, the method described in Example 1 was employed. The state so far is shown in FIG.

Next, an N-type impurity is implanted into the semiconductor region 1804 and a P-type impurity is implanted into the semiconductor region 1805 by a known plasma ion doping method. A type impurity region 1817 was formed. This process used a known CMOS technology. From the plasma, in addition to the impurity elements, hydrogen used as a diluent for the gas source is also ionized,
Implanted into the semiconductor region. Although this step can be performed by a known ion implantation method, it is required to separately implant hydrogen ions for the reason described later.

Thus, a structure as shown in FIG. 18D was obtained. Needless to say, the crystallinity of the portion into which the impurities are implanted by the previous ion implantation is remarkably deteriorated, and is substantially in an amorphous state (amorphous state or a polycrystalline state close thereto). Therefore, the crystallinity was recovered by laser annealing.
This step may be performed by thermal annealing at 600 to 850 ° C. The conditions for the laser annealing used were those described in Example 2. However, since the silicon nitride film 1807 does not transmit short wavelength ultraviolet light having a wavelength of 250 nm or less, X
An eCl laser (wavelength 308 nm) or a XeF laser (wavelength 351 nm) was used.

After laser annealing, 250-450 ° C.
Hydrogen atmosphere (1-700 torr, preferably 50
Annealing is performed at 0 to 700 torr) for 30 minutes to 3 hours, and lattice defects (dangling bonds, etc.) in the semiconductor are performed.
Was reduced. Actually, since the silicon nitride film 1807 exists, there is almost no exchange of hydrogen inside and outside the semiconductor region. Therefore, for example, in the plasma doping method, a large amount of hydrogen atoms are implanted into the semiconductor region, but in the ion implantation method, a separate hydrogen ion implantation step is required. In the plasma doping method, if the amount of hydrogen is insufficient, hydrogen must be separately doped.

Thus, the shape of the element was adjusted. Thereafter, as usual, an interlayer insulator 1818 is formed by sputter deposition of silicon oxide, an electrode hole is formed by a known photolithography technique, and the surface of the semiconductor region or the gate electrode / wiring is exposed, Lastly, a second metal film (aluminum or chromium) was selectively formed and used as electrodes / wirings 1819 to 1821. As described above, NTFT 1822 and PTFT 1
823 could be formed.

[Embodiment 8] Japanese Patent Application Nos. 4-73313, 4-73314, 4-733 which are the inventions of the present inventors.
19 to 21 show examples in which the present invention is applied to a TFT having a two-layer channel described in FIG.

That is, in FIGS. 19, 20 and 21, reference numerals 1901, 2001 and 2101 denote N channel TFs.
T, 1902, 2002, 2102 are P-channel TFTs
In each figure, the first layer 19 of the channel region is
08, 1910, 2008, 2010, 2108, 21
10 is substantially made of amorphous silicon. Its thickness was between 20 and 200 nm.

Further, 1907, 1909, 2007, 2
009, 2107 and 2109 are substantially polycrystalline or semi-amorphous silicon, and have a thickness of 20 to
200 nm. Further, 1904, 1906, 20
Reference numerals 04, 2006, 2104, and 2106 denote gate insulating films made of silicon oxide and have a thickness of 50 to 300 nm. And 1903, 1905, 2003, 200
Reference numerals 5, 2103, and 2105 denote silicon nitride films (or aluminum oxide films) having a thickness of 2 to 20 nm formed in the same manner as in Examples 5 to 7. These structures were produced based on the description of the above patent application or Examples 5 to 7.

[0111]

As described above, in the present invention, by providing an insulating film layer made of anodic oxidation on the surface of the gate electrode, the channel length becomes longer than the length of the gate electrode in the channel length direction. It is possible to provide an offset region in which an electric field is not applied or a very weak electric field is applied by the gate electrode, or a non-crystalline impurity semiconductor region having a similar effect can be provided by a similar method, and a leakage current at the time of reverse bias can be provided. Was able to be reduced. As a result, the charge holding capacity, which is indispensable in the past, becomes unnecessary, and the aperture ratio, which was about 20% in the past, is reduced to 35%.
Or higher, and a better display quality could be obtained.

In the present invention, since the offset region or the amorphous impurity region is determined by the thickness of the anodic oxide film of the gate electrode, the width of these regions is 10 to 100.
It can be controlled very precisely between nm. In addition, the yield was not significantly reduced by adding this step, and there was no factor considered as a cause of the yield reduction.

Furthermore, although not appearing on the surface, the pinhole was repaired by the anodic oxidation step, as described in the text. As a result, the yield was significantly improved. In particular, the gate leak was significantly reduced.

Although the present invention has been described mainly with respect to a silicon-based semiconductor device, it is apparent that the present invention can be applied to a semiconductor device using other materials such as germanium, silicon carbide, and gallium arsenide.

[Brief description of the drawings]

FIG. 1 shows a structure of a semiconductor device according to the present invention.

FIG. 2 shows a structure of a semiconductor device according to a conventional example.

FIG. 3 shows current-voltage characteristics of a conventional semiconductor device.

FIG. 4 shows current-voltage characteristics of a semiconductor device according to the present invention.

FIG. 5 shows a circuit configuration of a conventional active matrix type liquid crystal electro-optical device.

FIG. 6 is a circuit diagram of an active matrix liquid crystal electro-optical device according to the first embodiment.

FIG. 7 shows a structure of an active matrix liquid crystal electro-optical device according to the first embodiment.

FIG. 8 shows a manufacturing process of the active matrix liquid crystal electro-optical device in Example 1.

FIG. 9 shows an example of characteristics of a TFT according to the present invention and its operation principle.

FIG. 10 is a sectional view of an example of a manufacturing process of a TFT according to Example 2.

11 shows a top view of an example of a manufacturing process of a TFT according to Embodiment 3. FIG.

FIG. 12 is a sectional view of an example of a manufacturing process of a TFT according to a third embodiment.

FIG. 13 shows a structure of an active matrix liquid crystal electro-optical device according to a fourth embodiment.

FIG. 14 shows a circuit diagram and operation of an active matrix electro-optical device according to a fourth embodiment.

FIG. 15 shows a process of anodic oxidation in the present invention.

FIG. 16 shows a manufacturing process view (cross section) of a semiconductor device according to Example 5.

FIG. 17 shows a manufacturing process view (cross section) of a semiconductor device according to Example 6.

FIG. 18 shows a manufacturing process view (cross section) of a semiconductor device according to Example 7.

FIG. 19 shows a structural example of a semiconductor device according to an eighth embodiment.

FIG. 20 shows a structural example of a semiconductor device according to an eighth embodiment.

FIG. 21 shows a structural example of a semiconductor device according to an eighth embodiment.

[Explanation of symbols]

 105, 209 Insulating substrate 104, 208 Blocking layer 109, 203 Channel region 108, 210 Channel length 100, 204 Source region 101, 205 Drain region 110, 202 Gate insulating film 111, 201 Gate electrode 112 Oxide layer 211 Interlayer insulating film 102 , 206 Source electrode 103, 207 Drain electrode

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 627G (72) Inventor Hiroyuki Zhang 398 Hase, Atsugi-shi, Kanagawa Pref. References JP-A-60-245173 (JP, A) JP-A-58-23479 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 29/786 H01L 21/336 G02F 1/136 500

Claims (4)

(57) [Claims] A semiconductor layer including a pair of impurity regions; a channel forming region provided between the pair of impurity regions; a gate insulating film provided on the channel forming region; in an insulated gate semiconductor device having a gate electrode provided on the insulating film, an offset region between said pair of impurity regions a channel formation region, wherein the pair of impurity area, the offset region A first region in contact with the first region and a second region in contact with the first region, wherein the crystal grains in the second region are smaller than the crystal grains in the first region.
A semiconductor device characterized by having a large size. 2. The semiconductor device according to claim 1, wherein an anodic oxide layer is formed on a surface of said gate electrode. 3. The semiconductor device according to claim 1, wherein the first region is a substantially non-crystalline region. 4. A step of forming a gate insulating film on a semiconductor layer, a step of forming a conductive layer on the gate insulating film with an anodizable material and patterning, and using the patterned conductive layer as a mask to form the semiconductor. layer
To adding an impurity, and forming a gate electrode and the anodic oxide layer using the patterned surface of the conductive layer by anodizing, as a mask the gate electrode and the anodic oxide layer, the semiconductor layer laser Ma other irradiation child a flash lamp
And crystallizing the irradiated semiconductor layer by the above method.