KR960008133B1 - Semiconductor device and manufacturing method thereof - Google Patents

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Description

Semiconductor device and manufacturing method

1 is a structural diagram of a semiconductor device according to the present invention.

2 is a structural diagram of a semiconductor device according to the prior art.

3 is a current voltage characteristic diagram of a semiconductor device according to the prior art.

4 is a current voltage characteristic diagram of a semiconductor device according to the present invention.

5 is a circuit configuration of an active matrix liquid crystal electro-optical device according to the prior art.

6 is a circuit diagram of an active matrix liquid crystal electro-optical device in Example 1. FIG.

7 is a structural diagram of an active matrix liquid crystal electro-optical device in Example 1. FIG.

8 is a manufacturing process chart of the active matrix liquid crystal electro-optical device of Example 1. FIG.

9 is a diagram showing a characteristic example of a TFT according to the present invention and its operation principle.

10 is a cross sectional view of an example of the manufacturing process of the TFT according to the second embodiment;

11 is a plan view of a process example of manufacturing a TFT according to the third embodiment.

12 is a sectional view of an example of the process of manufacturing a TFT according to the third embodiment.

FIG. 13 is a structural diagram of an active matrix liquid crystal electro-optical device in Example 4. FIG.

FIG. 14 is a diagram showing the circuit diagram and operation of the active matrix electro-optical device in Example 4. FIG.

15 is a diagram showing an embodiment (production process) of the present invention.

16 is a diagram showing an embodiment (production process) of the present invention.

17 is a diagram showing an embodiment (production process) of the present invention.

18 is a diagram showing an application example of the present invention.

19 is a view showing an example of the manufacturing process relating to the method for forming a contact in the present invention.

20 is a view showing an example of the manufacturing process excessive to the method for forming a contact in the present invention.

21 is a diagram showing an example of a fabrication process that is excessive for the method for forming a contact in the present invention.

22 is a diagram showing an embodiment (production process) of the present invention.

23 is a diagram showing an embodiment (production process) of the present invention.

The present invention relates to a semiconductor device such as an insulated gate field effect transistor, a semiconductor integrated circuit, and a manufacturing method thereof.

The present invention is particularly applicable to an active matrix liquid crystal electro-optical device, in particular an active matrix liquid crystal electro-optical device, and the like, and shows a structure of a precursor effect transistor having a clear switching characteristic and a manufacturing method thereof.

The thin film insulated gate field effect transistor used in the conventional active matrix liquid crystal electro-optical device has a structure as shown in FIG. A gate insulating film 202 and a gate electrode 201 are provided on the insulating substrate 209 and on the semiconductor layer having the blocking layer 208 and the source 204, the drain 205, and the channel region 203. The interlayer insulating film 211, the source electrode 206, and the drain electrode 207 are provided thereon.

The manufacturing procedure of this conventional insulated gate field effect transistor is after forming a blocking layer on the glass substrate 209 by sputtering with SiO ₂ as a target, and then fabricating a semiconductor layer using the plasma CVD method. After patterning to form a semiconductor layer consisting of a source, a drain, and a channel region, a gate insulating film 202 made of silicon oxide is formed using a sputtering method, and then phosphorus (element symbol P) is formed using a reduced pressure CVD method. After forming a highly doped gate electrode conductive layer, patterning is performed to fabricate the gate electrode 201. After that, impurity ions are implanted using the gate electrode as a mask, a source 205 and a drain 204 are fabricated, and heat treatment is then performed to activate.

The insulated gate field effect transistor fabricated as described above is used for the gate electrode 201

The length of the channel long direction and the channel length 210 are almost the same.

The characteristics of the current voltage of the insulated gate field effect transistor having such a structure are the leakage current in the reverse bias region 250 as the applied voltage between the source and the drain increases in the reverse bias region 250 as shown in FIG. Had the drawback to increase.

When the leakage current increases as described above, when the element is used in an active matrix liquid crystal electro-optical device, as shown in FIG. 5A, charges accumulated in the liquid crystal 302 through the recording current 300 are not recorded. During the period, the leak current 301 was discharged through the leak portion of the element, and a good contrast could not be obtained. Therefore, in such a case, as shown in FIG. 5B as a conventional example, it was necessary to provide a capacitor 303 for charge holding. However, in order to form these capacitors, an electrode for capacitance by metal wiring is required, which is a factor of lowering the aperture ratio. Moreover, although the example which forms this by transparent electrodes, such as ITO, and improves an aperture ratio is reported, since it requires an extra process, it was not preferable.

When only one source or drain of such an insulated-gate field effect transistor is connected to a capacitor element (capacitor) and the transistor is used as a switching element, for example, a known one transistor / cell type dynamic random In an active liquid crystal display device having an access memory (DRAM) device or a circuit as shown in FIG. 5 in each pixel, the presence of the parasitic capacitance between the gate electrode and the drain (or source) causes the It is known that the voltage fluctuates

This voltage fluctuation ΔV is proportional to the gate voltage _VG and the parasitic capacitance, and is inversely proportional to the sum of the capacitor element capacitance and the parasitic capacitance. Transistors were fabricated to reduce parasitic capacitance. However, with the reduction of the device's design configuration, the parasitic capacity ratio has become so large that it cannot be neglected even by the self-aligning method.

For this reason, as shown in FIG. 5B for the purpose of reducing ΔV, it is proposed to increase the capacitance of the capacitor element by connecting the capacitors in parallel in addition to the original capacitor element. In the liquid crystal display, as described above, problems such as a decrease in the aperture ratio cannot be ignored.

Background Art Conventionally, semiconductor devices (semiconductor elements) such as insulated gate field effect transistors and semiconductor integrated circuits using a large number of them use single or multiple conductor materials as the wiring material or electrode material. The wiring can be formed relatively freely by stacking such wiring with an insulating coating therebetween.

In the conventional method, since the insulation between wirings was made by the insulation film (in most cases, a single layer) of only 11 m in thickness, the short circuit between the upper and lower wirings was a problem. In the semiconductor integrated circuit formed on the insulating film, the insulating film is formed of a material such as in glass, and made into a semi-melt state at a high temperature of about 1000 ° C. to remove these bubbles and pin holes, thereby improving the insulation between the wirings. . In addition, this step is such that a sudden step difference generated on the substrate by each thin film processor (film formation, etching, etc.) is gentle, and the effect is particularly remarkable in preventing the disconnection of the metal wiring formed on the insulating film.

However, this method is not applicable to any semiconductor device or integrated circuit. As a matter of course, the above-described method cannot be employed in semiconductor devices and integrated circuits using materials that cannot withstand such high temperatures. For example, inexpensive glass substrates used in place of expensive substrates such as quartz or silicon wafers generally have a strain point of 750 ° C. or less, and the above technique cannot be used. The same applies to the case of using a material such as aluminum to reduce the resistance as the wiring material.

In general, increasing the process temperature requires heat resistance of the apparatus in the process, so that the facility investment increases, and in particular, the larger the object to be treated, such as this functional substrate, increases exponentially.

For example, when manufacturing a thin film transistor (TFT) for use in a large liquid crystal display, the size of the substrate is 300mm or more diagonally, and it was impossible to employ a high temperature process of 1000 ° C.

This invention is made | formed in view of the said trouble, and makes it a subject to acquire a larger effect by the totally original method which was not thought of conventionally.

The present invention solves the above problems.

As one solution to this problem, the present inventors have made the channel length (distance between the source region and drain region) in the insulated gate field effect transistor longer than the length in the channel long direction of the gate electrode. It was found that the current voltage characteristics as shown in FIG. 4 can be obtained by forming an offset region in which the electric field by the gate electrode is not applied or a very weak offset region is formed in the portion in contact with the source region or the drain region.

The basic structure of this invention is shown in FIG. A blocking layer 104 is provided on the insulating substrate 105, and a source region 100, a drain region 101 and a channel region 109 are provided thereon as a semiconductor layer. A gate electrode 111 is formed on the channel region 109 by forming an oxide layer 112 as an insulating layer by anodizing the gate insulating layer 110 and a material capable of anodizing thereon. The source electrode 102 and the drain electrode 103 which contact the source region and the drain region, respectively, are provided. In Fig. 1, a state in which the interlayer insulator is not particularly provided is expressed. However, when the parasitic capacitance between the gate electrode and the wiring and the source / drain electrode and the wiring becomes a problem, the interlayer insulator may be provided as usual. Examples thereof are described in Examples 1 to 3 below.

As shown in FIG. 1, by selecting a material capable of anodizing the gate electrode 111 and the gate electrode that becomes the oxide layer 112, anodizing the surface portion thereof to form the oxide layer 112. The distance between the source region 100 and the drain region 101, that is, the input region, that is, the channel length 108, is approximately twice as long as the thickness of the oxide layer 112 than the length of the channel longitudinal direction of the gate electrode 111. do. As a material of the gate electrode portion, titanium (Ti), aluminum (Al), tantalum (Ta), chromium (Cr), silicon (Si) alone, or alloys thereof are suitable.

As a result, the portions 106 and 107 of the channel region 109 facing the oxide layers 112 formed on both sides of the gate electrode through the gate insulating film 9110 do not receive an electric field by the gate electrode at all or are vertically below the gate electrode. Very weak compared to Such regions 106 and 107 are hereinafter referred to as offset regions especially when they have the same crystallinity and impurity concentration as the channel region.

The regions 106 and 107 may be materials in an amorphous state doped with impurities. Strictly speaking, the regions 106 and 107 may be inferior in crystallinity to the source region 100 or the drain region 101 adjacent thereto. For example, if the regions 100 and 101 are made of large crystal grains of polycrystalline silicon, the regions 106 and 107 may be so-called semi-amorphous silicon, which is slightly more crystalline than amorphous silicon and amorphous silicon. If the areas 100 and 101 are semi-amorphous silicon, the areas 106 and 107 may be amorphous silicon. Of course, such amorphous materials need to take sufficient measures to exhibit semiconductor electrical properties, for example, terminate these unsaturated bonds sufficiently with hydrogen or halogen so that they are as dangling bonds as possible. Needs to be.

By providing such an amorphous region, good TFT characteristics could be exhibited as shown in Fig. 9A. 9 (b) is a thin film transistor (TFT) having a conventional insulated gate transistor structure, and as is clear from the drawing, a significant reverse leakage current has been observed in the conventional method, but it is substantially in an amorphous state as in the present invention. The characteristics have been improved by setting up the zone. In other words, providing an impurity region in an amorphous state has the same effect as providing an offset region as described above.

Although it is not yet clear what causes the characteristics to be improved by providing an amorphous region as described above, one of them has a lower ionization rate of the impurity element participated in the amorphous region than in the crystal region, and therefore, the same amount of anhydrous is added. Even if it is, even if it has a lower impurity concentration, it is thought that it is because the area | region substantially same as what is called a lightly doped drain (LDD) was formed. For example, in silicon, in the amorphous state, the ionization rate is 0.1 to 10% at room temperature, which is significantly smaller than that of a single crystal or polycrystalline semiconductor (almost 100%). Or, in the amorphous state, because the band gap is larger than the crystalline state, it is also considered to be the cause. For example, it can be explained by the energy band as shown in FIG. 9 (e) and (f). In the transistor of the normal LDD structure, the energy band diagram of the source / channel / drain is as shown in Figs. 9 (c) and (d). The center bulge is the channel region. The stepped portion is an LDD region. When no voltage is applied to the gate electrode, it is shown in FIG. 9 (c). When a large negative voltage is applied to the gate electrode, it is as shown in FIG. 9 (d). At this time, there is a forbidden band between the source and the channel region, and the channel region and the drain, and carriers such as electrons and holes cannot move, but the carrier jumps over the gap by hopping a trap effect in the tunnel effect or band gap. . In the case of ordinary TFTs, which are not LDD structures, the current flows more easily because the gap width is smaller. It is thought that this is a reverse leak. This reduction is especially noticeable in the TFT. It is presumed that this is because TFTs have a lot of trap levels due to unevenness such as polycrystals.

On the other hand, when the band gap of the LDD region is enlarged, such reverse leakage is reduced. An example of a large band gap of the LDD is shown in FIGS. 9E and 9F. 9 (e) shows a state where no voltage is applied to the gate, and (f) shows a state where a negative large voltage is applied to the gate. As apparent from (f), the width of the gap between the source and channel region or the channel region and drain when the negative voltage is applied is larger than that of (d).

The tunnel effect is markedly influenced by the width of the tunnel barrier (in this case, the width of the gap), and the probability decreases significantly with a slight increase in the gap width. In addition, the hopping via the local level is also a complex tunnel effect, so as the gap width increases, the probability decreases dramatically. It is considered to be meaningful to form an LDD region having a large band gap for the above reasons. The band gap of polycrystalline silicon is 1.1 eV, whereas the band gap of amorphous silicon is 1.5 to 1.8 eV, and it is extremely ideal to use a material having such a wide band gap for LDD.

In order to fabricate the semiconductor device having the above-described offset region in particular, according to the present invention, after forming the source layer, the drain layer, the semiconductor layer serving as the channel region, and the gate insulating layer 110, the gate electrode portion is formed of an anodizable material. The source region 100 and the drain region 101 are formed by implanting p-type or n-type impurity ions into the semiconductor layer, and then anodizing the surface portion of the gate electrode portion to form the gate electrode 111 and the oxide layer 112. And a heat treatment step may be performed.

Alternatively, after the semiconductor layer and the gate insulating layer layer 9110 are formed, the gate electrode portion is formed of an anodizable material, and then the surface portion of the gate electrode portion is anodized to form the gate electrode 111 and the oxide layer 112. Thereafter, the semiconductor layer may be implanted with p-type or n-type impurity ions to form the source region 100 and the drain region 101 and then subjected to heat treatment.

By taking the above steps, it is possible to easily and reliably produce an insulated gate field effect transistor whose channel length is longer than the channel longitudinal length of the gate electrode without causing any variation in performance due to mask misalignment or the like. Become.

Alternatively, in fabricating a semiconductor device of the present invention having an amorphous region, after forming a gate electrode portion with a material capable of anodizing after forming the source, drain, and channel regions, the semiconductor layer and the gate insulating layer 110 are formed. The semiconductor layer is implanted with p-type or n-type impurity ions, and the semiconductor layer is amorphous to form the source region 100 and the drain region 101 and the amorphous regions 106 and 107 adjacent thereto, and then the gate electrode portion. The surface portion is anodized to form the gate electrode 9111 and the oxide layer 112. At this time, the surface of the gate electrode retreats by oxidation. Thereafter, for example, only the source region 100 and the drain region 101 may be recrystallized by the laser annealing method or the flash lamp annealing method as a gate electrode and as a mask. The self-alignment is because the impurity region existing underneath is not recrystallized because the gate electrode portion is shaded.

For example, in the case of using the ion implantation method, the enlargement of the impurity region due to secondary scattering of ions can be calculated by the acceleration energy of ions, and the retreat of the gate electrode is determined by the thickness of the oxide layer. It is included as a design matter. Therefore, in the present invention, the positional relationship between the gate electrode and the impurity region can be made most suitable by the precise design. That is, since the thickness of the oxide layer can be controlled with a precision of 10 mm or less and can be controlled to the same degree with respect to the secondary scattering at the time of ion implantation, this positional relationship can be produced with a precision of 10 mm or less.

As described above, in the present invention, precise mask fitting is not newly required, and the yield is rarely reduced by the present invention. Nevertheless, the improvement of the characteristics of the transistor obtained by the present invention is large.

In addition, the present invention is characterized by providing an insulating coating formed of the wiring material around at least one wiring. Such an insulating coating is preferably formed by oxidizing the wiring material so that bubbles and pinholes do not occur. As the oxidation method, anodization, plasma oxidation, thermal oxidation and the like are preferable. As a preferable wiring material for obtaining such a structure, a single metal such as silicon, aluminum, tantalum, titanium, tungsten, molybdenum, semiconductor, or an alloy thereof, or tantalum nitride, titanium nitride, tungsten silicide, or molybdenum silicide And non-oxidizing metal compounds.

For example, nitrides such as tantalum nitride are converted to tantalum oxide by anodization.

Since such an oxide is excellent in insulating property, it is natural that the insulating film is further improved when the insulating film is formed again by means of a chemical vapor deposition (CVD) method or the like. However, a feature of the present invention is that the thickness of the oxide insulating film formed around the wiring material is not the same over the entire surface of the substrate, but is varied depending on the location to suit the purpose.

FIG. 1 of the present invention relates to a MIS (metal-insulator-semiconductor structure) type transistor using such a wiring oxide as a mask and a technique of manufacturing the same. In the case of fabricating impurity regions (sources and drains) of MIS transistors by a known self-alignment (self-alignment) method, impurities are introduced using the gate electrode as a mask. Some overlap occurred. In this case, the electric field is concentrated in the approaching portions of the drain and the gate electrode, resulting in the destruction of the gate insulating film in the vicinity.

The present inventors have found that when the drain region and the gate electrode are separated from each other by about 500 to 5000 Å at this time, such an electric field concentration can be alleviated, and thus the destruction of the gate insulating film can be prevented. By the way, it is difficult by the conventional method to obtain such a fine offset state reproducibly. Therefore, the inventors of the present invention can achieve the above object by using an oxide around the gate electrode as a mask at the time of impurity introduction and strictly controlling the thickness of the oxide to the desired offset size. Found.

It has also been found that the characteristics of the MIS transistors change depending on the magnitude of the offset realized at this time. In general, when the offset is large, the withstand voltage of the transistor obtained is high, and when the leakage current between the source and the drain is small, the mobility is low. On the contrary, when the offset is small, the mobility is high, but the withstand voltage is low.

For example, in one substrate, a transistor having a high breakdown voltage and a transistor capable of operating at high speed may be required. In the past, such a case has not been made separately.

The first aspect of the present invention is characterized by forming transistors according to the purpose on the same substrate by controlling transistors of such different characteristics by the magnitude of the offset (that is, the thickness of the oxide of the wiring = gate electrode).

For example, in a TFT active matrix type liquid crystal display, a transistor having a large offset is formed on the same substrate, and this is used as an active matrix TFT, while a transistor having a small offset is also formed, which requires high speed operation. TFTs for peripheral circuits are used.

Furthermore, in the peripheral circuit, a logic circuit can be formed by using a transistor having a small offset, and the transistor at the output stage can be configured to have a large offset.

The second aspect of the present invention relates to a MIS transistor and a wiring connected thereto, wherein in the wiring in the same layer as the gate electrode of the MIS transistor, the oxide of the wiring, especially the portion intersecting the upper wiring, is thickened, On the other hand, the oxide film of the gate electrode wiring is made thin or not provided at all. In this case, since the transistor has a small offset, high-speed operation is possible. On the other hand, since the oxide is thick at the intersection of the wiring, the effect of excellent insulation is obtained.

The third aspect of the present invention relates to a capacitor provided in a semiconductor circuit or an integrated circuit having such a capacitor, wherein a part of the wiring is used as an electrode of the capacitor and the periphery of the electrode is covered with the oxide. In other portions of the wiring, the portion that intersects the wiring at the top has a structure in which the periphery of the wiring is covered with oxide.

By increasing the capacitance of the capacitor by making the oxide of the portion constituting the electrode of the capacitor thinner, by thickening the oxide of the portion where the wiring intersects, and depositing another oxide film in addition to the oxide. This improves the insulation between the wirings and reduces the capacitive coupling between the wirings.

The fourth aspect of the present invention relates to a method for oxidizing wiring in forming such an oxide, and there are three methods. The first method is outlined in FIG. First, as shown in FIG. 19A, a base oxide film 51 is deposited directly on the substrate 50 or, if necessary, the wiring 52 is formed, and a mask is formed on a portion where upper wiring and contacts are formed. Install the ash 53. As the mask material, it is important to have a function of inhibiting oxidation, and it is selected by the oxidation method. For example, in a thermal oxidation method requiring a high temperature of several 100 ° C., heat resistance is required. In this case, for example, a material that is easy to form, such as silicon nitride, having excellent heat resistance and oxidation resistance is preferable. If it is oxidized at a lower temperature than that, the selection becomes wider. For example, if the process is 400 ° C. or less, organic materials such as polyimide can be used.

Since polyimide does not require a vacuum device for film formation, film formation can be carried out at an extremely low cost, and also excellent in mass productivity. In particular, since photosensitive polyimide can be patterned by the normal photolithography method, it is easy to handle.

Oxidation is performed in this state, and a thin oxide film is formed around the wiring as shown in Fig. 19B. Next, the mask material 55 is similarly formed around the region where the mask material 53 is formed previously, and similarly oxidized to form a thick oxide 56 as shown in FIG. 19C. In this manner, oxides having different thicknesses, which are the characteristics of the present invention, are obtained.

If the mask material is removed, the contact hole 57 is formed as shown in Fig. 19D, but it is noted that the thickness of the oxide is gradually changed until the contact hole is reached. As a result, the step to a contact hole can be alleviated. 19 (E) and (F) show a case where the upper wiring 59 is connected to such a contact hole 57. If the etching selectivity between the interlayer insulator 58 and the wiring oxides 54 and 56 is sufficient and there is room in the area of the contact formation region, the baggage shown in Fig. 19E is formed again smoothly. can do.

The interlayer insulator 58 is not necessarily required. Since the thickness of the oxide under the upper wiring 59 is gradually reduced toward the contact hole, the step difference between the upper wiring and the contact portion is gradually reduced, and therefore disconnection of the upper wiring is unlikely to occur. This method is effective when the oxide of the wiring is difficult to etch or cannot be etched substantially due to reasons such as insufficient selection ratio with other materials.

The second method is shown in FIG. As shown in FIG. 20A, a base oxide film 61 is deposited directly or if necessary on the substrate 60, and then the wiring 62 is formed, and the surface is oxidized to form a thin oxide 63. . Then, as shown in FIG. 20 (B), a mask 64 is provided in the portion forming the contact hole. Oxidation is carried out in this state, and as shown in FIG. 20C, the thin oxide 66 covered with the mask material remains as it is, but a thick oxide film 65 is formed in other portions. In this manner, oxides having different thicknesses, which are the features of the present invention, are obtained.

Next, as shown in FIG. 20D, the region 66 covered with the thin oxide is etched to form the contact hole 67. Also in this case, the thickness of the oxide is changed in stages until it reaches the contact hole. As a result, the step to the contact hole can be alleviated. 20E and 20F show the case where the upper wiring 69 is connected through such a contact hole 67. As shown in FIG. Interlayer insulator 68 is not necessary.

The third method is shown in FIG. As shown in FIG. 21A, after depositing the base oxide film 71 directly on the substrate 70 or, if necessary, the wiring 72 is formed and the surface is oxidized to form a thick oxide 73. Form. Then, as shown in Fig. 21B, a thick oxide is etched by the photolithography method to form a thin oxide 75.

In this manner, oxides having different thicknesses, which are features of the present invention, are obtained.

It is possible to alleviate the step in the contact hole in the portion where the thin oxide is formed again. 21D and 21E show the case where the wiring 78 is connected to such a contact hole 76. The interlayer insulator 77 is not necessarily required. In this method, when the thick oxide 73 is etched to form the thin oxide 75, if the etching rate is not uniform, a deviation occurs in the thickness. Therefore, the oxide etching technique is important for practical use. In contrast, in the first and second methods, the thickness of the oxide is determined by selective oxidation of the wiring. For example, in the case of thermal oxidation, the thickness of the oxide is absolutely determined by its temperature and time, and in the case of anodization, by the voltage applied, and the thickness of the oxide is constant when these parameters are constant. Therefore, it is a stable method compared with the 3rd method, and its reliability is high. An example is shown below.

Example 1

In this embodiment, a viewfinder for a video camera using a liquid crystal electro-optical device having a diagonal of 1 inch is manufactured, and the present invention is described.

In this embodiment, the number of pixels was 387x128, the element using the high mobility TFT (thin film transistor) by the low temperature process which has the structure of this invention was formed, and the viewfinder was comprised. The arrangement of the active elements on the substrate of the liquid crystal display device used in this embodiment is shown in FIG. 7, and the circuit diagram of this embodiment is shown in FIG.

The manufacturing process which shows A-A 'cross section and B-B' cross section of FIG. 7 is shown in FIG. A-A 'cross section shows NTFT and B-B' cross section shows PTFT.

In FIG. 8A, a blocking layer 401 using a magnetron RF (high frequency) sputtering method on a glass substrate 400 that can withstand heat treatment at low cost of 700 ° C or less, for example, about 600 ° C. The silicon oxide film as) is produced to a thickness of 100 to 3000 mm 3. Process conditions were 100% oxygen atmosphere, the film forming temperature 150 ° C, output 400 ~ 800W, pressure 0.5Pa. The film formation rate using quartz or single crystal silicon as a target was 30 to 100 mW / min. On this, a silicon film was formed by LPCVD (decompression phase), sputtering or plasma CVD. When formed by the reduced pressure gas phase method, disilane (Si ₂ H ₆ ) or trisilane (Si ₂ H ₆ ) is supplied to the CVD apparatus at 450 to 550 ° C, for example, 530 ° C, which is 100 to 200 ° C lower than the crystallization temperature. By the tabernacle. The pressure in the reactor was 30 to 300 Pa. The film formation speed was 50 to 250 mW / min. Boron may be added to the film formation at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ^-3 using diborane in order to control the PTFT's threshold voltage (Vth) in the same manner.

When carrying out by the sputtering method, it carried out in the atmosphere which mixed 20-80% of hydrogen to argon with the back pressure before sputtering to 1 S10 <^-5> Pa or less, single-crystal silicon as a target. For example, argon 20% hydrogen 80%. The film forming temperature is 150 ℃, frequency 13.56MH _Z, sputtering output was 400 ~ 800W pressure of 0.5Pa.

When manufacturing silicon film by a plasma CVD method, the temperature for example to 300 ℃, followed by using monosilane (SiH ₄₎ or disilane (Si ₂ H _6). They were introduced into a PCVD apparatus and formed into a film by applying a high frequency power of 13.56 MH _Z.

It is preferable that the film formed by these methods has oxygen of 5 S10 ²¹ cm ^-3 or less. If the oxygen concentration is high, it is difficult to crystallize, and the thermal annealing temperature must be high or the thermal annealing time must be extended. If too small, the leakage current in the off state increases due to the backlight. Therefore, it was set as the range of 4 * 10 <^19> -4 * 10 <^21> cm <^-3> . Hydrogen was ^{4x10 22} cm ^-3 and 1 atomic% as compared with silicon 4x10 ²² cm ^-3 .

After the silicon film in the amorphous state is produced by the above method to a thickness of 500 ~ 5000Å, for example 1500Å, medium heat treatment in a non-oxide atmosphere for 12 to 70 hours at a temperature of 450 ~ 700 ° C, for example hydrogen It was kept at a temperature of 600 ° C. under the atmosphere. Since an amorphous silicon oxide film is formed on the substrate surface under the silicon film, a specific nucleus does not exist by this heat treatment, and the whole is not uniformly heated. That is, it has an amorphous structure at the time of film formation, and also hydrogen is simply mixed.

By annealing, the silicon film is pulled out of the amorphous structure in a highly ordered state, and partly shows a crystal state. In the state after the film formation of silicon, the region of relatively high order is particularly crystallized and tries to be in the crystalline state. However, the silicon is attracted to each other because the mutual bonding is made by the silicon existing between these regions. When measured by laser Raman spectroscopy, the peak shifted to the low frequency side is observed at the peak of 522 cm ^-1 of the silicon of the single crystal. Its grain size is 50 ~ 500Å when it is calculated as half-width, and it is like a microcrystal, but in reality, there are many clusters with high crystallinity, and each cluster has silicon structure. A film of a semi-amorphous structure bonded (anchored) could be formed.

As a result, the film may be in a state where the film may be substantially free of grain boundaries (hereinafter referred to as GB). Since the carriers can easily move between each cluster through the anchored places, the carrier mobility is higher than that of polycrystalline silicon in which so-called GB is clearly present. That is, hole mobility 1h = 10-200 cm <2> / VSec and electron mobility 1e = 15-300 cm <2> / VSec are obtained.

On the other hand, the film may be polycrystalline by a high temperature annealing of 900 ~ 1200 ° C, but not in the above-described medium temperature.

However, in this case, segregation of impurities in the film occurs due to the solid phase growth from the nucleus, and impurities such as oxygen, carbon, and nitrogen are increased in the GB, and the barrier is formed in GB even though the mobility in the crystal is large. Hinders carrier movement. As a result, 50-100 cm 2 / VSec is obtained.

The silicon film thus formed was photoetched to produce a semiconductor layer 402 (channel width 201 m) for NTFT and a semiconductor layer 404 for PTFT.

A silicon oxide film 403 serving as a gate insulating film was formed thereon at a thickness of 500 to 2000 GPa, for example, 1000 GPa. This was carried out under the same conditions as the production of the silicon oxide film as the blocking layer. A small amount of fluorine may be added during the film formation to fix the sodium ions.

Thereafter, an aluminum film was formed above this. This was patterned with a photomask to obtain FIG. 8B. The gate insulating film 405 and the gate electrode part 406 for NTFT were formed, and the length of both channel long directions was 101 m, ie, the channel length was 101 m. Similarly, the gate insulating film 407 and the gate electrode part 408 for PTFT were formed, and the length of both channel length directions was 71 m, ie, the channel length was 71 m. In addition, the thickness of both gate electrode parts 406 and 408 was 0.81 m. In Fig. 8C, boron (B) was added to the source 409 and drain 410 for PTFT by ion implantation at a dose of 1 to 5 x 10 ¹⁵ cm ^-2 . Next, as shown in FIG. 8D, a photoresist 411 was formed using a photomask. Phosphorus (P) as a source 412 and a drain 413 for NTFT was added by ion implantation in the dose amount of 1-5 * 10 <^15> cm <^-2> .

Thereafter, anodization was performed on the gate electrode portion. L-Tartaric acid was diluted in ethylene glycol at a concentration of 5% and the pH was adjusted to 7.0 ± 0.2 with ammonia. The board | substrate was immersed in the solution, the anode side of the constant current source was connected, the platinum electrode was connected to the cathode side, the voltage was applied in the constant current state of 20 mA, and oxidation was continued until it reached 150V. Oxidation was continued until it became 0.1 mA or less in a constant voltage state at 150V again. Thus, the aluminum oxide layer 414 was formed in the surface of the gate electrode parts 406 and 408, and the gate electrode 415 for NTFT and the gate electrode 416 for PTFT were obtained. The aluminum oxide layer 414 was formed to a thickness of 0.31 m.

Then heat annealing was again performed at 600 ° C. for 10-50 hours. The NTFT source 412, drain 413, PTFT source 409, and drain 410 were made of N ⁺ and P ⁺ by activating impurities. Channel formation regions 417 and 418 are formed under the gate insulating films 405 and 407 as semi-amorphous semiconductors.

In this production method, the order of ion implantation of impurities and anodization around the gate electrode may be changed.

In this way, an insulating layer made of metal oxide is formed around the gate electrode. The actual length of the gate electrode is about twice the thickness of the insulating film than the channel length, and in this case, it is shorter by 0.61 m, and an offset region is provided which does not apply an electric field. The leakage current in reverse bias could be reduced.

In this embodiment, thermal annealing was performed twice in FIGS. 8A and 8E. However, the annealing of FIG. 8A may be omitted depending on desired characteristics, and the annealing of FIG. 8A may be combined with the annealing of FIG. 8E to shorten the manufacturing time. In Fig. 8E, the interlayer insulator 419 was formed by forming a silicon oxide film by the sputtering method described above. The silicon oxide film may be formed by an LPCVD method, an optical CVD method, or an atmospheric pressure CVD method. The interlayer insulator was formed to a thickness of 0.2 to 0.61 m, for example 0.31 m, and then a window 420 for electrodes was formed using a photomask. In addition, as shown in FIG. 8F, aluminum is formed on all of them by the sputtering method, and the leads 421 and 423 and the contacts 422 are fabricated using a photomask, and then the surface is planarized. For example, a light-transmissive polyamide resin was applied and formed, and the electrode hole was again subjected to a photomask.

ITO (indium tin oxide film) was formed by the sputtering method in order to make two TFTs a complementary structure, and to connect the output terminal to the electrode of one pixel of a liquid crystal device as a transparent electrode to it. It was etched by a photomask to construct an electrode 425. This ITO was formed at room temperature to 150 ° C. and achieved by oxygen at 200 to 400 ° C. or by annealing in the atmosphere. Thus, the NTFT 426, PTFT 427, and the electrode 425 of the transparent conductive film were produced on the same glass substrate 401. The electrical characteristics of the obtained TFT were 20 cm 2 / Vs and Vth was -5.9 V in the PTFT, and 40 cm 2 / Vs and 5.0 V in the NTFT.

One board | substrate for liquid crystal devices was produced in accordance with the above-mentioned method. The arrangement of the electrodes and the like of this liquid crystal display device is shown in FIG. NTFT 426 and PTFT 427 were provided at the intersection of the first signal line 428 and the second signal line 429. Such a matrix configuration using C / TFT was provided. The NTFT 426 is connected to the second signal line 429 through the lead 421 of the input terminal of the drain 413, and the gate 406 is connected to the signal line 428 formed with multi-layered wiring. The output terminal of the source 412 is connected to the electrode 425 of the pixel through the contact 422.

In the PTFT 427, the input terminal of the drain 410 is connected to the second signal line 429 through the lead 423, the gate 408 is connected to the signal line 428, and the output terminal of the source 409 is contacted. It is connected to the pixel electrode 425 in the same manner as NTFT through 422. This structure is comprised by repeating this structure left and right, and up and down.

Next, as a 2nd board | substrate, ITO (indium tin oxide film) was also formed by the sputtering method on the board | substrate which laminated | stacked 2000 microseconds of the silicon oxide film using the sputtering method on the blue plate glass. This ITO was formed at room temperature to 150 ° C. and achieved by oxygen at 200 to 400 ° C. or by annealing in the atmosphere. Furthermore, the color filter was formed on this board | substrate and it was set as the 2nd board | substrate.

Thereafter, the mixture of the UV-curable acrylic resin and the nematic liquid crystal composition of 6 to 4 was sandwiched by the first substrate and the second substrate, and the surroundings were fixed with an epoxy adhesive. Since the pitch on the board | substrate was fine at 461m, it connected using the COG method. In this embodiment, a gold bump provided on an IC chip is connected with an epoxy-based silver palladium resin, and a method of filling and fixing an epoxy modified acrylic resin between the IC chip and the substrate for fixing and sealing is used. . Thereafter, a polarizing plate was attached to the outside to obtain a transmissive liquid crystal display device.

Example 2

10 shows a sectional view of this embodiment. First, Corning 7059 glass was used as the substrate 501. Then, the underlying silicon oxide film 502 was formed by a sputtering method having a thickness of only 100 nm. Again, the amorphous silicon film 503 was formed by 50 nm by the plasma CVD method. On top of that, a silicon oxide film 504 was also formed by the sputtering method by 20 nm for the purpose of protecting the amorphous silicon film. It was recrystallized, but not in nitrogen atmosphere for 72 hours at 600 ° C. This was again patterned by photolithography and reactive ion etching (RIE) to form island-like semiconductor regions as shown in Fig. 10A. After forming the island-like semiconductor region, the protective silicon oxide film 504 was removed. For removal, wet etching was performed using buffered hydrofluoric acid (a solution in which hydrogen fluoride and ammonium fluoride were mixed). As buffer acid, it was set as the solution which mixed the high purity hydrofluoric acid (50 wt%) and copper ammonium fluoride solution (40%) in the ratio of 1:10 for semiconductor manufacture, for example. In addition, the etching rate of this buffer hydrofluoric acid with respect to silicon oxide was 70 nm / min, similarly 60 nm / min in aluminum oxide, and 15 nm / min in aluminum.

Again, the gate oxide film 505 was deposited by 115 nm in thickness by sputtering in an oxygen atmosphere where silicon oxide was targeted. In this state, phosphorus ions were doped in the gate oxide film 505 by the plasma dope method. This is for gettering movable ions such as sodium present in the gate oxide film, and it is not necessary to do it when the concentration of sodium is low enough that it does not interfere with the operation of the device. In this embodiment, the plasma acceleration voltage was 10 KeV and the dope amount was 2 x 10 ¹⁴ cm ^-2 . Subsequently, annealing was performed at 600 ° C. for 24 hours to recover the damage of the oxide film and the silicon film caused by the impact of plasma dope.

Next, an aluminum film was formed by the sputtering method, and this was patterned with a mixed acid (phosphate solution containing 5% acetic acid) to form a gate electrode wiring 506. The etching rate was 225 nm / min when the etching temperature was 40 ° C. In this way, the appearance of the TFT was maintained. The channel size at this time was 81 m in length and 201 m in width.

Next, an N-type impurity region (source, drain) 507 was formed in the semiconductor region by ion implantation. Phosphorus ion was used as an impurity, ion energy was 80 KeV, and the dope amount was 5 S10 ¹⁵ cm <^-2> . As shown in the figure, the doping was performed by a droop impeller penetrating an oxide film and introducing impurities. The advantage of using such a droop impeller is that the smoothness of the surface of the impurity region is maintained in the subsequent recrystallization process by laser annealing. In the case of not a dru impeller, a large number of crystal nuclei are generated on the surface of the impurity region in the recrystallization, and irregularities are formed on the surface. Thus, the structure as shown in FIG. 10 (B) was obtained. As a matter of course, the crystallinity of the portion into which the impurity is implanted by such ion implantation is remarkably deteriorated to become a substantially amorphous state (amorphous state or a polycrystalline state close thereto).

Again, an aluminum oxide film 508 was formed around the gate electrode and the wiring (top and side surfaces) by anodizing through the wiring 506. Anodization was carried out using a solution in which the ethylene glycol solution of 3% tartaric acid was neutralized in 5% ammonia and the pH was 7.0 ± 0.2. First, platinum was immersed in the solution as the cathode, the TFT was immersed in the substrate again, and the wiring 506 was connected to the anode of the power supply. The temperature was maintained at 25 ± 2 ° C.

In this state, a current of 0.5 mA / cm ² was first flowed, and when the voltage reached 200 V, the current was kept constant while the current was stopped at the time when the current became 0.005 mA / cm ² , and the anodization was terminated. The thickness of the anodic oxide film thus obtained was about 250 nm. The shape is shown in FIG.

Thereafter, laser annealing was performed. The laser irradiated 10 shots of the laser pulse of the power density of 350 mA / cm <^2> , for example using KrF excimer laser. Although it has been confirmed that at least one laser irradiation can recover the amorphous silicon crystallinity until it can withstand the operation of the TFT, a sufficient number of laser irradiations are required to sufficiently reduce the probability of occurrence of defects caused by the shaking of the laser power. Is preferred. However, since too many laser irradiations lower productivity, it is clear that about 10 times used in this embodiment are preferable.

Razer annealing was performed under atmospheric pressure in order to improve mass productivity. Since the silicon oxide film is already formed on the impurity region, there is no particular problem. Even if laser annealing was performed in the state where the impurity region was exposed, TFTs having sufficient characteristics could not be obtained because crystallization and oxygen infiltrated into the impurity region from the atmosphere at the same time resulted in poor crystallinity. Therefore, it was necessary to perform laser annealing in the vacuum that the impurity region was exposed.

In addition, in the present embodiment, as shown in FIG. 10 (D), the laser beam is obliquely incident. For example, in the present Example, the laser beam was irradiated at an angle of 10 degrees with respect to the vertical of the substrate. The angle is determined according to the design specifications of the device to be manufactured. By doing in this way, the area | region determined by the laser can be made asymmetric. That is, the regions 509 and 510 in the figure are impurity regions sufficiently crystallized. The region 511 is not an impurity region, but is a region crystallized by laser light. Region 512 is an impurity region but is not crystallized. For example, an impurity region on the right side of FIG. 10D may be used on the drain side where hot electrons are easily generated.

In this way, the shape of the element was maintained. Thereafter, an interlayer insulator is formed by sputter film deposition of silicon oxide as usual, holes for electrodes are formed by known photolithography techniques, and the surface of the semiconductor region or the gate electrode / wiring is exposed, and the metal film is finally formed. It was formed selectively to complete the device.

Example 3

In the TFT obtained by the present invention, not only the off current but also the breakdown voltage and operating speed between the source and the drain vary depending on the width of the non-binding semiconductor region or the offset region. Therefore, for example, the desired TFT can be manufactured by optimizing parameters such as the thickness of the anodic oxide film and ion implantation energy. However, these parameters are generally not adjustable for individual TFTs formed on a single substrate. For example, in an actual circuit, it may be preferable that a low-speed operation may be performed on a single substrate, but a TFT with a high breakdown voltage and a TFT requiring a high-speed operation may be formed simultaneously. In general, in the present invention, the larger the width of the offset region or the width of the amorphous impurity semiconductor region, the smaller the off current and the higher the breakdown voltage, but the lower the operating speed.

This embodiment shows an example of solving such a problem. 11 shows the present embodiment (top view) and 12 (sectional view).

In this embodiment, a circuit used in an image display method using a P-channel TFT and an N-channel TFT as described in Japanese Patent Application No. 3-296331 (Japanese Patent Application) for driving one pixel (liquid crystal pixel, etc.) It's about making. Here, the N-channel TFT requires high speed and breakdown voltage is not a problem. On the other hand, the P-channel TFT does not have a problem of operation speed, but requires a low off-current and, in some cases, also requires good breakdown voltage. Therefore, it is preferable that the N-channel TFT anodization film is thin (20-100 nm) and the P-channel TFT is thick (250-400 nm). Below, the manufacturing process is demonstrated.

As in the case of the second embodiment, Corning 7059 is used as the substrate 601, and the N-type impurity region 602, the P-type impurity region 603, the gate insulating film 604, the gate electrodes and the wirings 606 and 607 are made. Formed. Both the gate electrode and the wiring are connected to the wiring 650. (FIGS. 11A and 12A)

Again, aluminum oxide films 613 and 614 were formed in the periphery (top and side surfaces) of the gate electrodes and wirings 606 and 607 through the anodic oxidation method through electricity to the gate electrodes and wirings 606 and 607.

Anodization was carried out under the same conditions as in Example 2. However, the maximum voltage was 50V. Therefore, the thickness of the anodic oxide film produced in this process was about 60 nm (Fig. 12 (B)).

Next, in FIG. 11B, as shown at 651, the gate electrode wiring 606 is separated from the wiring 650 by laser etching. In this state, anodization started again. The conditions were the same as before, but the maximum voltage was raised to 250V. As a result, since no current flowed through the wiring 606, no change occurred, but an electric current flowed through the wiring 607, so that an aluminum oxide film having a thickness of about 300 nm was formed around the gate wiring 607. Degrees (C))

Thereafter, laser annealing was performed. The conditions were the same as in Example 2. In this case, the N-channel TFT (left of FIG. 12) is narrow enough that the width a ₁ of the amorphous region and the offset region is negligible, but the laser beam is irradiated unless the surface of the aluminum wiring is covered by the anodization film. Because of this, there was a significant damage, and although thin, it was necessary to form an anodized film. On the other hand, in the P-channel TFT (right side of FIG. 12), the thickness of the anodic oxide film was 300 nm, and the amorphous region also existed 150 to 200 nm. In addition, it is estimated that the width a ₂ of the offset region was also 100 to 150 nm. (Fig. 12 (D))

As in the case of Example 2, the necessary portions of the aluminum wirings were etched by laser irradiation in the air, the gate electrodes of the P-channel TFTs were separated from the wirings 607, and the wirings 650 were cut. Again, an interlayer insulating film was formed, contact holes were formed, and wirings 624 and 611 were formed. In this way, a circuit was formed.

In the circuit fabricated as described above, the N-channel TFT has a small width of an offset region and an amorphous region and a slightly larger off current, but has excellent speed. On the other hand, the P-channel TFTs were difficult to operate at high speeds, but had low off-current and excellent ability to hold charge accumulated in the pixel capacitors.

Thus, there are other cases in which TFTs having different functions must be integrated on one substrate. For example, in a liquid crystal display driver, a high speed TFT is required for a logic circuit such as a shift register, and a high breakdown voltage TFT is required for an output circuit. In the case of manufacturing a TFT according to such an opposite purpose, the method shown in this embodiment is effective.

Example 4

Using the fabrication method used in Example 1 of the present invention, an active matrix circuit composed of N-channel TFTs as shown in FIG. 13 was fabricated. In other words, the active matrix is a matrix of the gate line 701 and the data line 702, all of which are made of low-resistance aluminum, but are covered with aluminum oxide having a thickness of 200 to 400 nm because of the anodization process in the present invention. . Their line width was 21 m. In addition, the thickness was 0.51 m. In addition, a gate electrode 703 of each pixel TFT is provided on the gate line. This is similarly covered with aluminum oxide. A semiconductor layer 704 is formed under the gate electrode, and there is an N-type polycrystalline impurity region doped with phosphorus in the same way as the N-channel TFT of the first embodiment. The width is designed to be about 200 ~ 400nm. The source of this semiconductor layer is connected to the data line 702, while the drain is connected to the display pixel electrode (made of ITO) 706 through the aluminum electrode 705.

Fig. 14 shows a circuit diagram of the active matrix device fabricated in this embodiment, and the operation of the device using TFTs fabricated by conventional methods for device operation and comparison in this embodiment. As described above, in the matrix having such a structure, when the charging of the capacitor C _LC is terminated and the gate voltage is turned off, the capacitor C _LC is capacitively coupled with the gate line through the parasitic capacitance C _GD of the gate and the drain, It is known that the voltage drops by ΔV from the charging voltage. This phenomenon is the same as in the first embodiment, even if the N-channel TFT and the P-channel TFT are connected in parallel. The details are described in Japanese Patent Application No. 3-208648 filed by the present inventors.

As shown in Fig. 14, in a circuit composed of only one TFT of either the N channel or the P channel, the voltage drop ΔV is

ΔV = C _{GDV G} / (C _LC + C _GD )

It is represented by V _G is a variation range from the ON voltage of the gate voltage to the OFF voltage here. For example, in a TFT manufactured without using a self-arrangement, the parasitic capacitance C _GD is remarkably large, so that the _ΔV becomes large, and to overcome this, the storage capacitance C is parallel to the pixel capacitor as shown in FIG. _AD was formed and the capacity of the pixel capacitor was apparently enlarged. However, since such a problem does not solve the problem inherently, it is as described above that a new problem such as a decrease in aperture ratio is caused.

Even in a device manufactured by the self-aligned method, when the size of the pixel becomes small and parasitic capacitance of the TFT cannot be ignored as compared with the pixel capacitor, this voltage drop becomes a serious problem. For example, in a diagonal 3-inch high-vision-compatible panel (for projection), the pixel capacity is as small as 13 fF. On the other hand, when the TFT is manufactured using the 21m method in the process, the aspect ratio of the wiring is large, and even if there is no planar overlap, parasitic capacitance is generated in three-dimensional geometry and the size is several fF. . That is, it may be 10% or more of the pixel capacitor capacity.

In Fig. 14A, an example of an active matrix using a conventional TFT is shown, but it is clearly impossible to display the original image by? V. That is, in order to operate the TFT at high speed, the gate voltage is required to be higher than the drain voltage. Usually, a voltage about twice the drain voltage is employed as the gate voltage. Therefore, if the drain voltage is 5V, the gate voltage is 10V or more. In addition, the gate voltage becomes larger when the gate voltage is negative in the off state for the purpose of perfecting the operation of the TFT. For example, if 14 degrees is the drain voltage of ± 6V AC but, since the gate voltage is ± 12V, -4V in the OFF state from ON state, in the above formula, it is a V _G = 16V. If the parasitic capacitance is 2fF, ΔV is 2V and 1/3 of the drain charging voltage, as shown in Fig. 14A. Of course, since the electric charges accumulated in the pixels by natural discharge are discharged, it is difficult to actually perform further display in reality. And in order to avoid such a problem, the storage capacity had to be installed at the expense of the aperture ratio.

On the other hand, when the present invention is applied, the parasitic capacity can be significantly reduced. Specifically, it can be 0.1fF or less. Therefore, DELTA V can be almost ignored as shown in Fig. 14B. In addition, in the present invention, since the OFF current is about one digit less than that of the TFT manufactured by the conventional method, the natural discharge is much slower and the display is extremely ideal.

Example 5

15 shows one embodiment of the present invention. As the substrate, an alkali free glass substrate made of Corning 7059 and quartz copper was used. Alternatively, other substrate materials may be used. It is also preferable to coat the surface of the substrate with a material having good thermal conductivity such as aluminum nitride. In other words, in the present embodiment, anodization is performed in a later step, but at this time, only the anodization occurs, and since the ordinary glass substrate is not high in thermal conductivity, it causes other adverse effects such as exfoliation as a result of heat storage. If a material having high thermal conductivity such as aluminum nitride or aluminum oxide is used for the substrate, such a thing does not occur.

On the substrate 1101, a basic silicon oxide film 1102 was formed at a thickness of 200 to 2000 micrometers, and island-like crystalline silicon films 1103 and 1104 were formed again. The thickness of this silicon film was 300-1500 kPa. Here, 1103 is for the high speed operation TFT, and 1104 is for the low leakage current TFT. The former is preferable for the purpose of an arithmetic circuit, an image information processing circuit, a shift register, etc., and the latter is preferable for the active matrix element of a liquid crystal display device.

The fabrication method of the island-like crystalline silicon is only outlined here. An amorphous silicon film was formed to a desired thickness by a film forming method such as plasma CVD method or reduced pressure CVD method. There are two ways to crystallize. One method is 2 to 48 hours at a temperature of 500 to 650 ° C. In this case, the amorphous silicon film requires a thickness of 750 kPa or more, and a silicon oxide film having a thickness of 100 to 1000 kPa is superimposed thereon. This was not in the furnace. After annealing, this was patterned to obtain a target island silicon film.

Another method is to crystallize a silicon film in an instant by irradiating a strong light energy such as a laser or a flash lamp. In this case, the thickness of the amorphous silicon film is preferably 750 kPa or less, and in order to avoid stress due to the difference in thermal expansion, a strong light energy such as a laser or a flash lamp is irradiated while patterning in an island shape without forming a cap film. Crystallize.

After the island-forming silicon film was obtained in this manner, a silicon oxide film 105 having a thickness of 500 to 1500 Å was formed on the entire surface as the gate insulating film. As the method for forming the silicon oxide film, a sputtering method or a plasma CVD method was suitable. Alternatively, when the heat resistance of the substrate is allowed, the silicon oxide film obtained by the thermal oxidation method of the molded silicon exhibited extremely excellent characteristics and was preferable. When the silicon oxide film was formed by the plasma CVD method, using tetraethoxy silane (TEOS) yielded a film having excellent step coverage. In order to form the characteristic again, annealing at 450 to 550 ° C. may be performed in an inert gas atmosphere such as oxygen or argon.

Then, the 1st wiring, ie, the wiring used as the gate wiring of TFT was formed by the sputtering method. Aluminum was used as the wiring material. Aluminum may contain not only pure aluminum but also 0.5-2% of silicon.

The aluminum was patterned to form gate electrodes 1106 and 1107. In addition, all the wirings of aluminum formed at this time are connected (FIG. 15A).

Subsequently, the substrate is immersed in 1-5% ethylene glycol solution of tartaric acid (pH 7.0), the aluminum wiring is connected to the anode, the platinum electrode is used as the cathode, and current is applied to the aluminum wiring. Anodization was formed. At this time, at first, a constant current was applied and oxidation proceeded, and when the voltage increased to a predetermined voltage, the voltage was maintained and maintained until the current became 1001 mA / cm 2 or less. In the first constant current state, the surface state of the oxide film was greatly affected by the rate of rise of the voltage. In general, the higher the rate of rise, the rougher the surface. In addition, the amount of silicon contained also affected the surface state. From the findings of the inventors, it has been clarified that 2 V / min or less is preferable in pure aluminum and 1.5 V / min or less is preferable in aluminum containing 2% of silicon. In this example, the voltage was raised to 100V at a rate of 1.2V / min. As a result, anodic oxides (aluminum oxide) 1108 and 1109 having a thickness of 100 Å were formed (FIG. 15B).

Next, a photo varnish was applied to the entire surface of the substrate by a spin coater. The rotation speed was 2500 rpm. And after drying for 1 hour in a nitrogen atmosphere of 80 ° C., this photo varnish was patterned by the usual exposure method. In this case, only the high speed TFT portion (left side of the drawing) was left. Finally, the remaining photo varnish 1110 was polyimide by heating and drying at 300 ° C. for 0.5 to 2 hours. Thereafter, anodization was again performed using the above anodization means. In this case, anodization does not proceed in the portion covered with the polyimide 1110. Therefore, as shown in FIG. 15C, anodization occurred only in the wiring 1107. In this case, the applied voltage was raised to 220V. Therefore, a thick anode oxide 1111 having a thickness of 2500 kV was formed around the wiring 1107 (FIG. 15C).

Subsequently, impurities (phosphorus or boron) were introduced into the silicon film by self-alignment with the gate electrode and the oxides around the mask by ion implantation or plasma doping, and the impurity regions 91112 and 1113 were formed. At this time, the size of the offset between the impurity region and the gate electrode is determined by the thickness of the anode oxide as shown in FIG. That is, the offset a is small because the anode oxide 1108 is known in the TFT (high-speed action) on the left side of the drawing, while the offset (b) is thick because the anode oxide 1111 is thick in the TFT (low leakage current) on the right side. ) Is great. That is, there is a relationship of a <b (FIG. 15D).

Subsequently, in order to improve the conductivity of the impurity region, the crystallinity of the impurity region was improved by irradiating strong light energy such as a laser or a flash lamp, and again, the second layer wiring was formed using a known multi-wiring technique. That is, as the interlayer insulator 91114, a silicon oxide film having a thickness of 2000 to 6000 GPa was deposited by plasma CVD method, contact holes were formed thereon, and a metal film such as titanium nitride (thickness 200 to 1000 GPa) and aluminum (5010) were formed. This film was deposited by a sputtering method or the like, and then patterned to form electrodes and wirings 1115, 1116, 1117, and 1118 (FIG. 15E).

In the circuit fabricated as described above, a shift register was fabricated using a high-speed TFT. As a result, the operation of 6.2 MHz at a drain voltage of 10 V and 11.5 MHz at 20 V was confirmed. On the other hand, the mobility of the low leakage current TFT was 50 to 110 cm 2 / Vs in the NMOS, but the leakage current was 10 fA or less under the conditions of a gate voltage of 0 V and a drain voltage of 1 V in the NMOS.

Example 6

16 shows one embodiment of the present invention. As a substrate, an alkali free glass substrate such as coating 7059 or quartz was used. Or other substrate materials. In addition, as described in Example 1, the surface of the substrate is preferably coated with a material having good thermal conductivity such as aluminum nitride. On the substrate 1201, a basic silicon oxide film 1202 was formed to have a thickness of 200 to 2000 microseconds, and a molded crystalline silicon film 1204 was formed again. The thickness of this silicon film was 300 to 1500 ° C. After the molded silicon film was obtained, a silicon oxide film 1203 having a thickness of 500 to 1500 에 was formed on the entire surface as a gate insulating film.

Then, the 1st wiring, ie, the wiring used as the gate wiring of TFT was formed by the sputtering method. Aluminum was used as the wiring material. Aluminum may contain not only pure aluminum but also 0.5-2% of silicon. This aluminum was patterned to form the gate electrode 1205 and the wiring 1206 in the same layer (FIG. 16A).

Subsequently, the substrate was immersed in 1-5% ethylene glycol solution of tartaric acid (pH 7.0), the aluminum wiring was connected to the anode, and the platinum electrode was used as the cathode to apply a current to the anode wiring. Formed. Here, anodic oxides (aluminum oxide) 1207 and 1208 having a thickness of 1000 Å were formed (FIG. 16B).

Subsequently, the photo varnish was applied to the entire surface of the substrate by a spin coater and dried, and then the photo varnish was patterned. In this case, only a part of the TFT (left side of the drawing) was left. Finally, the remaining photo varnish (1209) in this way was polyimide by heating and drying at 300 ° C., 0.5-2 hours. Thereafter, anodization was again performed using the above anodization means. In this case, anodization does not proceed in the part covered with the polyimide 1209. Therefore, as shown in FIG. 16C, anodization occurred only in the wiring 1206. Here, the applied voltage was raised to 220V, and a thick anode oxide 1210 having a thickness of 2500 kV was formed around the wiring 1206 (FIG. 16C).

Thereafter, an impurity region 1211 was formed by introducing impurities (phosphorus or boron) into the silicon film in a self-aligned manner by using the ion implantation method or the plasma doping method with the gate electrode and the oxides around it as a mask. At this time, the magnitude of the offset between the impurity region and the gate reference electrode is determined by the thickness of the anode oxide as shown in FIG. In this case, an offset of about 1000 ms was formed (16 (D)).

Then, in order to improve the conductivity of the impurity region, the crystallinity of the impurity region is improved by irradiating strong light energy such as a laser or a flash lamp, and again, the second layer wiring is formed using a known multilayer wiring technique. did. That is, as the interlayer insulator 1212, a silicon oxide film having a thickness of 2000 to 6000 kPa is deposited by plasma CVD to form a contact hole therein, and a metal film such as titanium nitride (thickness 200 to 1000) and aluminum ( A multilayer film of 500 to 5000 mV was deposited by a sputtering method or the like, and then patterned to form electrodes and wirings 1213 and 1214 (FIG. 16E).

As shown in the figure, the wiring 1214 intersects with the wiring 1206 but at the intersection there is not only an interlayer insulator 1212 but also an anodic oxide 1210 having high insulation. This anode oxide is expected to exhibit sufficient insulation even at an applied voltage of 200V in its fabrication process. On the other hand, in the TFT, there was also an anode oxide 1210 around the gate electrode. This anode oxide is expected to exhibit sufficient insulation even at an applied voltage of 200V in its fabrication process. On the other hand, in the TFT, since the thickness of the anode oxide 1207 around the gate electrode is about 1000 GPa, there is no problem in the high-speed operation of the TFT, and the mobility of the TFT was actually 80 to 150 cm 2 / Vs in the NMOS.

Example 7

17 shows one embodiment of the present invention. As a substrate, an alkali free glass substrate such as coating 7059 or quartz was used.

Example 8

1403 and 1404 are gate electrodes, and the thickness of the anode oxide is thin (~ 1000 kPa) so as to be suitable for high-speed TFT. In addition, in order to contact the wiring 1406 with the second layer wiring 1407, the anode oxide of the portion is thin (~ 1000 kPa) similarly to the gate electrode portion, and contact holes are formed. In forming the contact hole, any of the methods shown in Figs. 19 to 21 may be employed, but the method of Fig. 19 or 20 was easy to implement.

On the other hand, since the wiring 1405 intersects with the second layer wiring 1407, the anode oxide was thick (˜2500 kPa), and sufficient insulation was obtained.

Example 9

18B shows an embodiment of the present invention. This embodiment is implemented using the techniques shown in Examples 5 to 7, and is an example of a circuit around a signal output terminal used in a driving circuit of a liquid crystal display or an image sensor.

The TFT 1411 on the left side of the figure is a large current control TFT, and typically has a large channel width of 500 to 1 mm. On the other hand, the TFT 1412 on the right side is a TFT for logic circuits, and typically has a relatively small channel width of 5 to 501 m.

The wirings of the first layer are 1413, 1414, and 1415, of which 1413 and 1414 are gate electrodes, and 1414 is thin (~ 1000 kV) in its thickness to suit high-speed TFTs. The anodic oxide is thick (~ 3000 kV) because the TFT 1414 is a high breakdown voltage and high power TFT. In addition, in order to connect the wiring 1415 to the second layer wiring 1416, the anode oxide of the portion thereof is the same as that of the gate electrode portion, and is thin (~ 1000 kV), and contact holes are formed.

In forming the contact hole, any of the methods shown in Figs. 19 to 21 may be employed, but the method of Fig. 19 or 20 was easy to implement. The wiring 1415 is continuous with the gate wiring 1413.

Example 10

18C shows one embodiment of the present invention. This embodiment is implemented using the technique shown in Embodiments 5 to 7 and is an example of a TFT peripheral circuit for liquid crystal display pixel control. The TFT 1412 in the figure is a TFT of low leakage current. The wirings of the first layer are 1422, 1423, and 1424, of which 1423 is a gate electrode, and the anode oxide is thick (˜2000 kV) because the TFT 1421 requires a low leakage current. In addition, since the wiring 1422 also intersects the second layer wiring 1425, the anode oxide is made thick (˜2000 kV) because of increasing insulation. On the other hand, the wiring 1424 constitutes a transparent conductive film and a capacitor extending from the drain of the TFT. In order to increase the capacitance, the dielectric was made of only anodized oxide (aluminum oxide) without interlayer insulation provided therebetween.

Example 11

22 shows the present embodiment. This embodiment particularly relates to a technique for connecting an anodized wiring and an upper wiring. The underlying silicon oxide film 802 is deposited on a substrate 801, such as quartz or Corning 7059, and the silicon oxide film 804 is deposited as a crystalline shaped silicon film 803 and a gate insulating film, and again made of aluminum. The gate electrode wiring 805 and the other wirings 806 and 807 of the TFT were formed. Since the wiring 807 needs to form contact holes with the upper wiring, a mask material 808 is formed by photoness (FIG. 22A).

An electric current was flowed through the wirings 805 to 807 in the electrolytic solution, and a thin (thickness 1000 kPa) anodized oxide (aluminum oxide) film 809 was formed on the surface other than the portion covered with the mask material (Fig. 22 ( B)).

Thereafter, the gate electrode 805 of the TFT and the mask 808 of the previously formed photoness were covered, and the masks 810 and 811 were newly formed by the photoness (Fig. 22 (C)).

Then, anodization was performed again to form a thick (2500 GPa) anode oxide 812 except for the portion covered with the mask material. At this time, the thickness of the anode oxide is gradually reduced toward the contact hole in the vicinity where the contact hole of the wiring 807 is formed (Fig. 22 (D)).

Thereafter, an impurity region 813 was formed, and an interlayer insulator 814 was deposited. In general, the thickness of the interlayer insulator is preferably 5000 GPa or more in order to increase the insulation. However, in the present embodiment, the thickness of the interlayer insulator was sufficient even in the range of 1000 to 3000 GPa because a thick anodic oxide was formed at the intersection portion of the wiring. This interlayer insulator was patterned to form contact holes in the source, drain, and wiring 807 of the TFT. Then, a metal film was deposited again and patterned to form metal wirings 815, 816, and 817. At this time, although the wiring 817 is connected to the lower wiring 807, a step is formed gently around the contact hole, and since the thickness of the interlayer insulator is also thinner than usual, disconnection of the upper wiring 817 occurs. it's difficult. On the other hand, although the wiring 816 intersects the wiring 806, since a thick anode oxide 812 is formed at the portion where the wiring crosses, sufficient insulation is obtained by this and the interlayer insulator.

Example 12

23 shows the present embodiment. This embodiment particularly relates to a technique for connecting an anodized wiring and an upper wiring. An underlying silicon oxide film 902 is deposited on a substrate 901 such as quartz or Corning 7059, and a silicon oxide film 904 is deposited as a crystalline shaped silicon film 903 and a gate insulating film, and again by aluminum. The gate electrode wiring 905 of the TFT and the other wirings 906 and 907 are formed, and these wirings are made to flow through the current in the electrolytic solution to form a thin (thickness 1000 kPa) anodized oxide (aluminum oxide) film 908 on the surface. Formation (Fig. 23 (A)).

Subsequently, masks 909 and 910 were formed by photo varnish, covering portions where the contact electrodes of the gate electrode 905 and the wiring 907 of the TFT were to be covered (Fig. 23 (B)).

Then, anodization was again performed to form a thick (2500 Å) anodic oxide 911 in addition to the portion covered with the mask material (Fig. 23 (C)).

Thereafter, the masks 909 and 910 were removed to form the impurity regions 912, and contact holes of the thin anodic oxide film 908 on the upper surface of the wiring 907 were formed again (Fig. 23D).

An interlayer insulator 914 was deposited, and the interlayer insulator was patterned to form contact holes in the source, drain, and wiring 907 of the TFT. Then, metal films were deposited again and patterned to form metal wirings (915, 916, 917). At this time, although the wiring 917 is connected to the lower wiring 907, a step is formed gently around the contact hole, so that disconnection of the upper wiring 917 is unlikely to occur. On the other hand, since the wiring 916 crosses the wiring 906 but a thick anode oxide 911 is formed at the portion where the wiring intersects, sufficient insulation is obtained by this and the interlayer insulator.

The effect of the present invention is that first, MIS transistors having different characteristics on the same substrate can be formed in substantially the same process. As is apparent from Example 5, in order to form two types of TFTs,

① Application and patterning of photo varnish

② second anodization

There are only two additional processes, and since there is only one photolithography process that determines manufacturing efficiency, there is no decrease in manufacturing efficiency.

The second effect of the present invention is that, as can be seen in the sixth embodiment, the short circuit at the intersection of the wiring is significantly reduced, and the characteristics of the MIS transistor (e.g., high speed operation) are maintained. This also substantially consists only of adding the steps (1) and (2) above, and rather contributed to the improvement of manufacturing efficiency.

The third effect of the present invention is that the first layer wiring and the second layer wiring simply change the thickness of the anodic oxide in the vicinity of the contact as shown in FIGS. 19 to 21 and the description corresponding thereto. The step difference caused by the contact hole is alleviated and the disconnection of the second layer wiring and the like are prevented.

In this way, in the present invention, by providing an insulating layer of anodization on the surface of the gate electrode, the channel length becomes longer than the length of the channel electrode in the channel direction so that an electric field by the gate electrode is not applied to both sides of the channel region. Alternatively, by providing an offset region in which a very weak electric field is applied, or an amorphous impurity semiconductor region having the same effect can be provided by the same method, thereby reducing the reverse current-like leakage current. As a result, the charge holding capacity required by the prior art was not necessary, and the aperture ratio, which was about 20% in the past, could be set to 35% or more, or more, and better display quality could be obtained.

In the present invention, since the offset region or the amorphous impurity region is determined by the thickness of the anodic oxide film of the gate electrode, the width of these regions can be controlled very precisely between 10 and 100 nm. Moreover, the addition of this step significantly reduced manufacturing efficiency, and there was no factor that could be considered as a cause of the reduction in manufacturing efficiency.

Although the present invention has been mainly described with respect to silicon-based semiconductor devices, it is clear that the present invention can be applied to semiconductor devices using other materials such as germanium, silicon carbide, potassium arsenide and the like.

Claims (15)

A semiconductor device having an insulated gate field effect transistor having at least a semiconductor layer, an insulating film layer, and a conductor layer on an insulating substrate, wherein the channel length is longer than the length of the channel electrode in the channel direction. 2. The semiconductor device according to claim 1, wherein the channel length is approximately twice as long as the oxide layer thickness formed on the gate electrode surface than the length in the channel longitudinal direction of the gate electrode. In the manufacturing method of an insulated gate type transistor effect transistor having at least a semiconductor layer, an insulating film layer, and a conductor layer on an insulating substrate, after forming the semiconductor layer and the gate insulating film layer, after forming the gate electrode portion with an anodizable material, A method of fabricating a semiconductor device, comprising implanting p-type or n-type impurity ions into the semiconductor layer to form a source or drain region, and then anodizing the surface of the gate electrode, followed by a heat treatment process. . A metal oxide and an anode oxide layer formed around the gate electrode, a thin film channel region, a pair of first impurity regions formed by sandwiching the channel regions, and a second impurity adjacent to each of the first impurity regions A thin film type insulated gate semiconductor device having a region. The insulated gate semiconductor device according to claim 4, wherein the first impurity region is in an amorphous state. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed on the semiconductor device insulating substrate, and either one of its source or drain is connected to a capacitor element. 7. The semiconductor device according to claim 6, wherein the semiconductor device is used for driving a liquid crystal display pixel. The semiconductor device according to claim 4, wherein the semiconductor device is formed on an insulating substrate, and either one of its source or drain is connected to a capacitor element. In a semiconductor device having first and second MIS type transistors formed on a single substrate, an oxide of a material constituting a gate electrode present on the side and / or top surface of the gate electrode of the first MIS type transistor. A semiconductor device characterized in that the thickness of the object is different from that of the second MIS transistor. 10. The semiconductor device according to claim 9, wherein the semiconductor device is an active matrix liquid crystal display device. At least one MIS transistor formed on one substrate, at least one first wiring in a gun, such as a gate electrode of the MIS transistor, and a second existing in a different layer from the first wiring In a semiconductor device in which the first wiring and the second wiring intersect at the intersection A, the material constituting the gate electrode existing on the side and / or top of the gate electrode of the MIS transistor. A semiconductor device characterized in that the thickness of an object made of oxide is different from that present at the side and / or the top surface of the first wiring at the intersection point A. At least one capacitor formed on one substrate, a first wiring in the same layer as the first electrode of the capacitor, and a second wiring in which the capacitor is present in the same layer as the second electrode, In a semiconductor device in which the first and second wirings intersect at intersection B other than the capacitor, an object made of an oxide of a material present on the upper surface of the first electrode of the capacitor and constituting the first electrode. The thickness of the semiconductor device is different from that existing at the side surface and / or the upper surface of the said 1st wiring in the said intersection B. The semiconductor device characterized by the above-mentioned. Forming a first mask material selectively on the first wiring formed on the substrate, and then oxidizing the first wiring; and applying a second mask material to a region including at least a part of the first mask material. After forming, there is a process of coral etching the first wiring, and after removing the first and second mask materials, a process of forming the second wiring in at least a part of the region where the first mask material is formed. A method of manufacturing a semiconductor device. After forming a mask material selectively on the 1st wiring formed on the board | substrate and whose surface was oxidized, and then oxidizing a 1st wiring, and removing the said mask material, at least a part of the area | region in which the mask material was formed. And a step of forming a contact hole and a step of forming a second wiring in at least a part of the contact hole. Selectively etching the first wiring formed on the substrate and whose surface is oxidized, forming an interlayer insulator, and forming a contact hole in the interlayer insulator, and then forming a second wiring. A semiconductor device manufacturing method characterized by having a point.