KR960011185B1 - Electric optical device - Google Patents

Abstract

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Description

Electro-optical device

1 is a structural diagram of a semiconductor device according to the present invention.

2 is a structural diagram of a semiconductor device according to a conventional example.

3 is a current voltage characteristic diagram of a semiconductor device according to the prior art.

4 is a current voltage characteristic diagram of a semiconductor device according to the present invention.

5 is a circuit diagram of an active matrix liquid crystal electro-optical device according to a conventional example.

6 is a circuit diagram of an active matrix liquid crystal electro-optical device according to the present embodiment.

7 is a structural diagram of an active matrix liquid crystal electro-optical device according to the present embodiment.

8 is a manufacturing process diagram of an active matrix liquid crystal electro-optical device according to the present embodiment.

9 is a graph showing the current-voltage characteristics of the P-channel TFT according to the second embodiment.

10 is a current voltage characteristic diagram of an N-channel TFT according to the second embodiment.

11 is a graph showing the dependence of the anode oxide film thickness on the drain current according to Example 2. FIG.

12 is a graph showing the dependence of the anodic oxide thickness on the threshold voltage according to Example 2. FIG.

FIG. 13 is a graph showing the dependence of the anodization thickness on the field mobility according to Example 2. FIG.

14 is a cross-sectional view of the TFT fabrication process in Example 2. FIG.

15 is a plan view of a TFT fabrication process in Example 2. FIG.

16 is a manufacturing process diagram of an active matrix liquid crystal electro-optical device according to Example 1. FIG.

Fig. 17 is a diagram showing a characteristic example of a TFT according to the present invention and its operation principle.

18 is a sectional view of an example of the manufacturing process of TFTs according to Example 5. FIG.

19 is a sectional view of an example of the process of manufacturing a TFT according to the sixth embodiment.

20 is a structural diagram of an active matrix liquid crystal electro-optical device according to Example 7. FIG.

FIG. 21 shows a circuit diagram and an operation of an active matrix electro-optical device according to Example 7. FIG.

22 is a plan view of an example of the process for manufacturing a TFT according to the sixth embodiment.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a field effect transistor that can be used in an active matrix type electro-optical device, in particular, an active matrix type liquid crystal electro-optic device, etc., having a clear switching characteristic, and a manufacturing method thereof.

The thin film insulated gate field effect transistor used in the conventional active matrix liquid crystal electro-optical device has a structure as shown in FIG. A blocking layer 8 on the insulating substrate 9 and a gate insulating film 2 and a gate electrode 1 thereon on a semiconductor layer having a source 4, a drain 5, and a channel region 3. The interlayer insulating film 12, the source electrode 6, and the drain electrode 7 are provided.

A conventional fabrication procedure of this insulated gate field effect transistor is formed by forming a blocking layer on the glass substrate 9 by sputtering with SiO ₂ as a target, then fabricating a semiconductor layer using plasma CVD and patterning it. By forming a semiconductor layer serving as a source, a drain, and a channel region, and then forming a gate insulating film 2 made of silicon oxide using a putter method, and then using phosphorous (element symbol P) at a high concentration using a reduced pressure CVD method. After forming the added conductive layer for gate electrodes, patterning is performed and the gate electrode 1 is produced. Thereafter, impurity ions using the gate electrode as a mask were implanted, the source 5 and the drain 4 were fabricated, and then heat-treated to activate them.

In the insulated gate field effect transistor produced in this way, the length of the gate electrode 1 in the channel length direction and the channel length 10 are substantially the same.

As shown in FIG. 3 in the case of an n-channel, the current voltage characteristic of the insulated gate type field effect transistor having such a structure leaks as the applied voltage between the source and the drain increases in the reverse bias region 13. It had the drawback of increasing current.

When the leakage current increases as described above, when the element is used in an active matrix liquid crystal electro-optical device, as shown in FIG. 5A, charges accumulated in the liquid crystal 29 through the recording current 30 are not recorded. During the period, the leak current 31 was discharged through the leak portion of the element, and a good contrast could not be obtained.

Therefore, in such a case, it is necessary to provide the capacitor | condenser 32 for charge holding as shown in FIG. 5 (b) as a conventional example. However, in order to form these capacitor | condensers, since the electrode for capacitance by metal wiring is needed, it became a factor which reduces aperture ratio. Moreover, although the example which ITO etc. form an transparent electrode and improves an aperture ratio was reported, it was not preferable because it requires an extra process.

In addition, when only one of the source or the drain of such an insulated gate field effect transistor is connected to a capacitor element (capacitor) and the transistor is used as a switching element, for example, a known one transistor / cell type dynamic In an active liquid crystal display device having a circuit in each pixel as shown in FIG. 5 or a random access memory (DRAM) device, the presence of a parasitic capacitance between the gate electrode and the drain (or source) It is known that the voltage of an element fluctuates.

Since the variation ΔV of the voltage is proportional to the gate voltage V and the parasitic capacitance, and inversely proportional to the capacities of the capacitor elements and the parasitic capacitance, in order to suppress the variation of the voltage, self alignment is generally required. The parasitic capacitance is reduced by fabricating the transistor by -align method. However, even with the self-aligning method, with the reduction of the design method of the device, the ratio of the parasitic capacitance became so large that it could not be ignored.

For this reason, in order to reduce ΔV, as shown in Fig. 5B, in addition to the original capacitor element, it is proposed to connect the capacitors in parallel and to increase the capacitance of the capacitor element. Therefore, problems such as an increase in the capacitor area and a decrease in the aperture ratio cannot be ignored in the liquid crystal display device as described above.

The present invention solves the above problems.

As one solution to this problem, the present inventors and the like in the insulated gate field effect transistor, the channel length (distance between the source region and the drain region) is increased by making the gate electrode longer than the length in the channel length direction. It has been found that the current voltage characteristics as shown in FIG. 4 can be obtained by forming an offset region that is free from an electric field by the gate electrode or is formed at a portion in contact with the source region or the drain region. The basic structure of this invention is shown in FIG. A blocking layer 104 is provided on the insulating substrate 105, and a source region 100, a drain region 101 and a channel region 109 are provided thereon as a semiconductor layer. A gate electrode 111 is formed on the channel region 109 by forming an oxide layer 112 as an insulating layer by anodizing the gate insulating layer 110 and a material capable of anodizing thereon. The source electrode 102 and the drain electrode 103 are provided in contact with the source region and the drain region, respectively. In FIG. 1, the interlayer insulation is not particularly provided. However, when the parasitic capacitance between the gate electrode and the wiring and the source / drain electrode and the wiring becomes parasitic, the interlayer insulation may be provided as usual. It describes below.

As shown in FIG. 1, a material capable of anodizing is selected in the gate electrode portion formed of the gate electrode 111 and the oxide layer 112, and the surface portion is anodized to form the oxide layer 112. The distance between the source region 100 and the drain region 101, that is, the ion implantation region, that is, the channel length 108 is approximately two times the thickness of the oxide layer 112 than the length in the channel length direction of the gate electrode 11. It is about twice as long. As the material of the gate electrode portion, titanium (Ti), aluminum (Al), tantalum (Ta), chromium (Cr), silicon (Si) elements, or alloys thereof are suitable.

As a result, the electric field by the gate electrode is not applied to the parts 106 and 107 of the channel region 109 which oppose the oxide layer 112 formed on both sides of the gate electrode via the gate insulating film 110, or the gate electrode It is very weak compared to the part immediately below. Such regions 106 and 107 are hereinafter referred to as offset regions especially when they have the same crystallinity and impurity concentration as the channel region. The regions 106 and 107 may be materials in an amorphous state to which impurities are added. Strictly speaking, the regions 106 and 107 may be inferior in crystallinity to the source region 100 or the drain region 01 adjacent thereto. For example, as long as the regions 100 and 101 are polycrystalline silicon of large crystals, the regions 106 and 107 may be so-called semi-amorphous silicon, which is slightly more crystalline than amorphous silicon or amorphous silicon. As long as area | region 100,101 is semi-amorphous silicon, area | region 106 and 107 should just be amorphous silicon. Of course, it is necessary to take sufficient measures to exhibit semiconductor electrical properties in such amorphous materials, for example, to terminate these unsaturated bonds sufficiently with hydrogen or halogen so that dangling bonds are as small as possible. have.

By providing such a non-crystalline region, good TFT characteristics can be exhibited as shown in Fig. 17A. Fig. 17B shows a thin film transistor (TFT) having a conventional insulated gate transistor structure. As is clear from the drawing, in the conventional method, the reverse leakage current was remarkably observed. However, as in the present invention, the characteristics were improved by providing a substantially amorphous region. In other words, providing an impurity region in an amorphous state has the same effect as providing an offset region as described above.

The reason why the characteristics are improved by providing the amorphous region in this manner is not yet known with certainty. However, in the amorphous region, the ionization rate of the added impurity element is lower than that in the crystal region, and therefore, even when the same amount of impurity is added, the impurity concentration appears to have a lower impurity concentration. It is thought that this is because a region substantially identical to the Doped-Drain (LDD) is formed. For example, in silicon, in the amorphous state, the ionization rate is 0.1 to 10% at room temperature, which is significantly less than in the case of single crystal or polycrystalline semiconductor (almost 100%), or in the amorphous state, the band gap is less. It is considered to be the cause because it is larger than the crystal state. For example, the energy band can be described as shown in FIG. 17 (e) and (f). In the transistor of the normal LDD structure, the energy band of the source / channel / drain is as shown in Figs. 17C and 17D.

The raised part of the center is the channel region. The stepped portion is an LDD region. When no voltage is applied to the gate electrode, it is shown in FIG. 17 (c). However, when a large negative voltage is applied to the gate electrode, it is as shown in FIG. 17 (d). At this time, there is a forbidden band between the source and the channel region, and the channel region and the drain, and carriers such as electrons and holes cannot move, but the carrier has a gap exceeding the trap level in the tunnel effect or band gap. Jump over.

In the case of ordinary TFTs, which are not LDD structures, since the gap width is smaller, the current is more likely to flow.

It is thought that this is a reverse leak. This phenomenon is particularly noticeable in the TFT. It is presumed that because the TFT is a heterogeneous material such as polycrystal, there are many trap levels due to grain boundaries.

On the other hand, when the band gap of the LDD region is enlarged, such reverse leakage is reduced. An example of the large band gap of the LDD is shown in Figs. 17E and 17F. FIG. 17E shows a state in which no voltage is applied to the gate, and (f) shows a state in which a large voltage of the negative portion (-) is applied to the gate.

As apparent from (f), the width of the gap between the source and channel region or the channel region and drain when the negative voltage is applied is larger than that of (d). The tunnel effect is significantly influenced by the width of the tunnel barrier (in this case, the width of the gap), and the probability decreases significantly with a slight increase in the gap width. In addition, since the excitation via a part of the level is also a complex tunnel effect, the larger the gap width, the smaller the probability will be. For the above reasons, it is considered that forming an LDD region having a large band gap is meaningful. The band gap of amorphous silicon is 1.5 to 1.8 eV, whereas the band gap of polycrystalline silicon is 1.1 eV, and it is very ideal to use such a wide band gap material for LDD.

According to the present invention, in particular, in order to fabricate the semiconductor device having the above-described offset region, the gate electrode portion is formed of an anodizable material after the source layer, the drain layer, the semiconductor layer serving as the channel region, and the gate insulating film layer 110 are formed. Subsequently, the source layer 100 and the drain region 101 are formed by implanting p-type or n-type impurity ions into the semiconductor layer, and then anodizing the gate electrode surface portion to form the gate electrode 111 and the gate electrode 111. The oxide layer 112 may be formed, and a heat treatment step may be performed.

Alternatively, after the semiconductor layer and the gate insulating layer 110 are formed, the gate electrode portion is formed of an anodizable material, and then the surface portion of the gate electrode portion is anodized, and the gate electrode 111 and the oxide layer 112 are formed. And then implanting p-type or n-type impurity ions into the semiconductor layer to form the source region 100 and the drain region 101 and then perform a heat treatment step.

By taking the above steps, the insulated gate field effect transistor whose channel length is longer than the length in the channel length direction of the gate electrode can be easily and reliably without causing an imbalance in performance due to mask misalignment or the like. It becomes possible to produce.

Alternatively, in order to fabricate the semiconductor device of the present invention having an amorphous region, the gate electrode portion is formed of an anodizable material after forming the source, drain, channel region, semiconductor layer, and gate insulating film layer 110. Thereafter, p-type or n-typed impurity ions are implanted into the semiconductor layer, the semiconductor layer is amorphous, the source region 100 and the drain region 101, and the amorphous region 106 adjacent thereto. And (107), and then anodize the surface portion of the gate electrode portion to form the gate electrode 111 and the oxide layer 112. At this time, the surface of the gate electrode retreats by oxidation. Thereafter, for example, only the source region 100 and the drain region 101 may be recrystallized by the laser annealing method or the flash lamp annealing method by self-aligning the gate electrode portion as a mask. Here, the self-alignment is because the impurity region existing below cannot be recrystallized because the gate electrode portion is shadowed.

For example, in the case of using the ion implantation method, the enlargement of the impurity region due to secondary scattering of ions can be calculated by the acceleration energy of the ions, and the retreat of the gate electrode is determined by the thickness of the oxide layer. This is included as a design matter. Therefore, in this invention, the positional relationship of a gate electrode and an impurity region can be made into the optimal state by precise design. That is, since the thickness of an oxide layer can be controlled with the precision of 10 nm or less, and also can control to the same degree about the secondary scattering at the time of ion implantation, this positional relationship can be manufactured with the precision of 10 nm or less.

As mentioned above, in this invention, precise mask registration is not newly requested | required and manufacturing efficiency is less likely to fall by this invention. In addition, the characteristic improvement of the transistor obtained by the present invention is large.

An example is shown below.

Example 1

In this embodiment, a view finder for a video camera using a liquid crystal electro-optical device having a diagonal of 1 inch is produced, and the present invention is described.

In this embodiment, a viewfinder was constructed by forming a device using a high-mobility TFT (thin film transistor) by a low temperature process having the configuration of the present invention as a configuration having a pixel number of 387 × 128. The arrangement of the active elements on the substrate of the liquid crystal display device used in this embodiment is shown in FIG. 7 and the circuit diagram of this embodiment is shown in FIG.

The manufacturing process which shows A-A 'cross section and B-B' cross section of FIG. 7 is shown in FIG. A-A 'cross section shows NTFF, B-B' cross section shows PTFT.

In Fig. 8 (a), the blocking layer 52 is formed on the glass substrate 51 which withstands heat treatment of 700 ° C or less, for example, about 600 ° C or less, by using a magnet RF (high frequency) sputtering method. As a silicon oxide film, a thickness of 1,000 to 3,000 kPa is produced. The process conditions were 100% atmosphere of oxygen, 150 degreeC of film-forming temperature, 400-800 W of outputs, and 0.5 Pa of pressures. The film formation rate using quartz or single crystal silicon as a target was 30 to 100 Pa / min. On this, a silicon film was formed by LPCVD (decompression phase), sputtering, or plasma CVD. When formed by the reduced pressure gas phase method, disilane (SI ₂ H ₆ ) or trisilane (SI ₃ H ₈ ) at 450 to 500 ° C., for example, 530 ° C., lower than the crystallization temperature is 30 to 300 Pa. I did it. The film formation speed was 50 to 250 mW / min. Boron may be added to the film formation at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ using diborane to roughly control the threshold voltage Vth of PTFT and NTFT.

When performing by the sputtering method, the back pressure before sputtering was made into 1x10 <^-5> Pa or less, single-crystal silicon was made into the target, and it performed in the atmosphere which mixed 20%-80% of hydrogen to argon. For example, 20% argon and 80% hydrogen. The film formation temperature was 150 ° C., the frequency was 13.56 MHz, and the sputtering output was 0.5 Pa at 400 to 800 W pressure.

When producing silicon film euhae the plasma CVD method, the temperature for example to 30 ℃, and used a monocyclic means (SiH ₄₎ or a DC field (SI ₂ H _6). These were introduced into a PCVD apparatus and formed into a film by applying a high frequency power of 13.56 MHz.

It is preferable that oxygen in the film formed by these methods is 5 * 10 <^23> cm <^-3> or less.

If this oxygen concentration is high, it is difficult to crystallize, and the thermal annealing temperature must be high or the thermal annealing time must be lengthened. If too small, the leakage current in the off state increases due to the backlight. Therefore, it was set as the range of 4 * 10 <^19> -4 * 10 <^21> cm <^-3> . Hydrogen was ^{4x10 20} cm ^-3 and 1 atom% compared to silicon 4x10 ²² cm ^-3 .

After the silicon film in the amorphous state was produced in a thickness of 500 to 5,000 kPa, for example, 1,500 kPa by the above-described method, heat treatment was performed at elevated temperature in a non-oxidizing atmosphere at a temperature of 450 to 700 ° C. for 12 to 70 hours. For example, the temperature was maintained at 600 ° C. under hydrogen atmosphere. Since an amorphous silicon oxide film is formed on the substrate surface under the silicon film, a specific nucleus does not exist by this heat treatment, and the whole is heat-annealed uniformly. In other words, the film formation has an amorphous structure, and hydrogen is simply mixed. By annealing, the silicon film is changed from the amorphous structure to the state of high order, and partly shows the crystal state. In the state after the film formation of silicon, the region of relatively high order is particularly crystallized and tries to be in the crystalline state. However, since the mutual bonding is performed by the silicon which exists between these areas, silicon pulls together. When measured by laser Raman spectroscopy, the peak of single crystal silicon is observed when measured from the peak of 522 cm ^-1 of single crystal silicon. Its apparent particle size is 50 ~ 5500Å, which is calculated as half-width, and is like a microcrystal, but in reality, there are many regions with high crystallinity, and have a cluster structure. The film of the semi-amorphous structure which became bonded (anchor) was able to be formed. As a result, the film exhibits a state in which it is possible to have substantially no grain boundary (hereinafter referred to as GB). Since the carriers can easily move between each cluster through the anchored points, the carrier mobility is higher than that of polycrystalline silicon in which so-called GB is clearly present. That is, hole mobility (μh) = 10-200 cm <2> / Vsec, electron mobility (μe) = 15-30 cm <2> / Vsec are obtained.

In addition, you may polycrystallize a film by the high temperature annealing of 900-1,200 degreeC instead of the above-mentioned annealing at the medium temperature. However, in this case, segregation of impurities in the film occurs due to solid phase growth from the nucleus, and impurities such as oxygen, carbon, and nitrogen are increased in GB, and mobility in crystal is large, but barriers are formed in GB. It inhibits the movement of the carrier therein. As a result, the current situation is rarely obtained mobility of 10 cm2 / Vsec or more. Therefore, impurity concentrations such as oxygen, carbon, and nitrogen need to be made from one to several tenths of moisture than those of semi-amorphous. In that case, 50-100 cm <2> / Vsec was obtained.

The silicon film thus formed was subjected to photoetching to produce a semiconductor layer 53 (channel width of 20 m) for NTFT and a semiconductor layer 54 for PTFT.

A silicon oxide film serving as a gate insulating film was formed thereon at a thickness of 500 to 2,000 mW, for example, 1,000 mW. This was made under the same conditions as the production of the silicon oxide film as the blocking layer. A small amount of fluorine may be added during the film formation to fix the sodium.

Thereafter, an aluminum film was formed above this. This was patterned in a photomask to obtain FIG. 8 (b). The gate insulating film 55 and the gate electrode part 56 for NTFT were formed, and the length of both channel length directions was 10 micrometers, ie, the channel length was 10 micrometers. Similarly, the gate insulating film 57 and the gate electrode part 58 for PTFT were formed, and the length of both channel length directions was 7 micrometers, ie, the channel length was 7 micrometers. In addition, the thickness of both gate electrode parts 56 and 58 was set to 0.8 micrometer. In Fig. 8 (c), the boron (element symbol (b)) is ionized at a dose of 1 to 5 x 10 ¹⁵ cm ^-2 to the source 59 and the drain 60 for the PTFT. It added by the injection method. Next, as shown in FIG. 8 (d), the photoresist 61 was formed using a photomask. As a source 62 and a drain 63 for NTFT, phosphorus (P) was added by the ion implantation method at the implantation amount of 1-5 * 10 <^15> cm <^-2> .

Thereafter, anodization was performed on the gate electrode portion. L-Tartaric acid was diluted in ethylene glycol at a concentration of 5% and the pH was adjusted to 7.0 ± 0.2 with ammonia. The substrate was immersed in the solution, and the pulsed (+) side of the constant current source was connected, and a platinum electrode was connected to the negative (-) side to apply a voltage at a constant current of 20 mA, and oxidation was continued until 150 V was reached. . Again, oxidation was carried out at 150V under constant voltage until it became 0.μmA or less. Thus, the aluminum oxide layer 64 was formed in the surface of the gate electrode parts 56 and 58, and the gate electrode 65 for NTFT and the gate electrode 66 for PTFT were obtained. The aluminum oxide layer 64 was formed in thickness of 0.3 micrometer.

Next, reheat annealing was performed at 600 ° C. for 10 to 50 hours. The NT62 source 62, drain 63, PTFT source 59, and drain 60 were prepared in N and P by activating the statement. Further, under the gate insulating films 55 and 57, the channel forming regions 67 and 68 are formed of semi-amorphous semiconductors.

In this production method, the order of ion implantation of impurities and anodization around the gate electrode may be changed.

In this way, an insulating layer made of metal oxide is formed around the gate electrode, and the actual length of the gate electrode is about twice the thickness of the insulating film than the channel length, and in this case, becomes shorter by 0.6 μm, and the offset region does not take an electric field. The leakage current during reverse bias could be reduced by installing

In this embodiment, thermal annealing was performed twice in FIGS. 8 (a) and 8 (d).

However, the annealing in FIG. 8 (a) may be omitted depending on the desired characteristics, and may be combined with the annealing in FIG. 8 (e) for both drops to shorten the manufacturing time. In FIG. 8E, the interlayer insulator 69 was formed as the formation of the silicon oxide film by the sputtering method described above. The silicon oxide film may be formed by an LPCVD method, an optical CVD method, or an atmospheric pressure CVD method. The interlayer insulator was formed to a thickness of 0.2 to 0.6 µm, for example, 0.3 µm, and then the window 70 for electrodes was formed using a photomask.

Again, as shown in Fig. 8 (f), aluminum is formed in all of them by sputtering, and the leads 71, 73 and the contact 72 are formed by using a photomask, and then the surface is flattened. For example, a translucent polyamide resin was applied to form the organic resin 74, and the electrode holes were again drilled in a photomask.

ITO (indium tin oxide film) was formed by sputtering in order to make two TFTs a complementary structure, and to connect the output terminal thereof with the electrode of one pixel of a liquid crystal device as a transparent electrode.

It was etched by a photomask and the electrode 75 was constructed. This ITO was achieved by annealing at room temperature or in the atmosphere. Thus, the NTFT 76, PTFT 77, and the electrode 75 of the transparent conductive film were produced on the same glass substrate 51. As shown in FIG. The electrical properties of the obtained TFT were 20 cm 2 / Vs in PTFT, -5.9 V in Vth, 40 cm 2 / Vs in NTFT, and 5.0 V in NTFT.

One board | substrate for liquid crystal devices was produced in accordance with the above-mentioned method. Arrangement of the electrode etc. of this liquid crystal display device is shown in FIG. 7, and the NTFT 76 and PTFT 77 were provided in the intersection part of the 1st signal line 40 and the 2nd signal line 41. As shown in FIG. Such a matrix configuration using C / TFT was provided. The NTFT 76 is connected to the second signal line 41 via the lead 71 of the input terminal of the drain 63, and the gate 56 is connected to the signal line 40 formed with multilayer wiring. The output terminal of the source 62 is connected to the electrode 75 of the pixel via the contact 72.

On the other hand, in the PTFT 77, the input terminal of the drain 60 is connected to the second signal line 41 via the lead 73, the gate 58 is the signal line 40, and the output terminal of the source 59 is a contact. It is connected to the pixel electrode 75 in the same way as NTFT via 72. This embodiment is constituted by repeating such a structure from side to side and up and down.

Next, as a 2nd board | substrate, ITO (indium tin oxide film) was also formed by the sputtering method on the board | substrate which laminated | stacked 2000 microseconds of silicon oxide films using the sputtering method on the blue plate glass. This ITO was formed into a film at room temperature-150 degreeC, and was achieved by oxygen of 200-400 degreeC, or annealing usually.

Moreover, the glass filter was formed on this board | substrate and it was set as the 2nd board | substrate. Then, the said 1st board | substrate and the 2nd board | substrate injected the mixture which the ultraviolet curable acrylic resin and the nematic liquid crystal composition mixed in the ratio of 6 to 4, and fixed the circumference | surroundings with the epoxy adhesive. Since the pitch of the lead on a board | substrate is 46 micrometers fine, it connected using the COG method. In this embodiment, a gold bump provided on an IC chip is connected with an epoxy-based silver palladium resin, and an IC modified acrylic resin for fixing and sealing is used between the IC chip and the substrate. did. Thereafter, a polarizing plate was attached to the outside to obtain a transmissive liquid crystal display device.

In the same manner as in Example 1, a transmissive liquid crystal display device may be manufactured as shown in Figs. 16A to 16F.

Example 2

In this embodiment, the difference in the characteristics of the semi-amorphous silicon TFT by the width of the offset region will be described. In this embodiment, the semi-amorphous silicon TFT uses aluminum as a gate, and forms an offset region by oxidizing around the aluminum gate by anodization. A detailed manufacturing method is described below.

A multilayer film of a silicon nitride film and a silicon oxide film was formed on a glass substrate, and 150 nm of an amorphous silicon film was formed by plasma CVD. In patterning, the width was made into 80 micrometers.

Therefore, the channel width of this TFT is 80 mu m. This was formed into semi-amorphous silicon by heating at 600 ° C. for 60 hours in a nitrogen atmosphere.

Next, the silicon oxide film used as a gate oxide film was formed by sputtering with the silicon oxide target in oxygen atmosphere. The thickness was 115 nm. Again, an aluminum film was formed by electron beam evaporation, the aluminum film and the underlying silicon oxide film were etched by a known photolithography method to form a gate electrode. Reactive ion etching (RIE) method was used for the etching. The channel length of the gate electrode formed in this way was 8 micrometers.

The gate electrode and its wiring were anodized. Anodization was carried out as follows.

First, an ethylene glycol solution of 3% tartaric acid was placed in a container, and 5 wt% of ammonia water was added thereto to adjust the pH to 7.0 ± 0.2. At a temperature of 25 ± 2 ° C., the platinum electrode was used as the cathode, the glass substrate was immersed in the solution, and the aluminum wiring was connected to the anode of a direct current power source to perform anodization.

In the anodic oxidation, a constant current of 0.2 to 1.0 mA / cm 2 is first applied, and after reaching a suitable voltage of 100 to 250 V, anodization is performed while the voltage is kept constant, and the total voltage decreases to 0.005 mA / cm 2. I finished with electricity and took it out.

In the experiments of the present inventors, it was clear that the initial constant current value only affected the oxide film formation time, and had little effect on the thickness of the oxide film finally formed. The parameter having a great influence on the thickness of the oxide film is the maximum voltage reached, for example, the thicknesses of the oxide films obtained when they are 100 V, 150 V, 200 V, and 250 V were 70 nm, 140 nm, 230 nm, and 320 nm, respectively. In addition, at this time, it became clear by the experiment of this inventor that aluminum oxide of 1.5 times the thickness of aluminum oxidized is obtained. Moreover, the thickness of the obtained oxide film was very uniform over all parts.

Thereafter, source and drain regions were formed by laser doping. The laser doping method was performed by the following method. The used laser is KrF laser, which is a kind of excimer laser, and its oscillation wavelength is 248 nm. The sample is placed in an airtight container, and a reduced pressure atmosphere of 95 pa is introduced, and diborane (B ₂ H ₆ ) or phosphine (PH ₃ ) is introduced as a doping gas therein, and the energy of one shot is 350 mJ. 50 shots of the laser pulses were irradiated.

In the case of forming the P-type channel, diborane diluted with hydrogen was used as the doping gas, and the flow rate was set to 100 sccm of diborane and 20 sccm of hydrogen. In addition, when forming an N-type channel, phosphine was used and the flow volume was 100 sccm.

Thereafter, annealing was performed at 250 DEG C for 30 minutes in hydrogen for the purpose of promoting activation of the channel region. Then, an interlayer insulating film, a source, a drain electrode and a wiring were formed by a known method to complete the TFT.

Examples of the characteristics of the TFT thus produced are shown in FIGS. 9 and 10. 9 is a P-channel TFT, and FIG. 10 is an N-channel TFT.

Since the magnitude of the offset is difficult to measure directly, the effect of the present invention is described by the thickness of the oxide film around the gate electrode (presumably reflecting the magnitude of the offset).

As apparent from Figs. 9 and 10, it was found that the larger the thickness of the oxide film, that is, the larger the width of the offset region, the lower the reverse leakage current or the off current. In particular, the effect was evident in the N-channel TFT. That is, as can be seen from the figure, in the N-channel TFT, the current (off current) when the gate voltage is 0 decreases with the formation of the offset region, and has fallen to the practical level. In the P-channel TFT, there was no decrease in off current, but the reverse leakage current was significantly reduced. Thus, the reduction of the off current by providing the offset region is shown in FIG. In the figure, Ioff is off current and Ion is on current.

In addition, no change in the threshold voltage Vth of the TFT by providing the offset region was seen. This pattern is shown in FIG. However, according to another experiment, deterioration of the characteristics was observed because the formation of the channel was discontinuous when the offset region was unusually large. For example, as shown in FIG. 13, when the width of the offset region exceeds 30 nm, the field mobility rapidly decreased in both the N-channel and the P-channel. In view of these results, it became clear that 200-400 nm is suitable as a width of an offset area | region.

Example 3

In the TFT obtained by the present invention, not only the off current but also the breakdown voltage and the operating speed change between the source and the drain depending on the width of the offset region. Therefore, for example, by optimizing a parameter such as the thickness of the anodization film, a TFT corresponding to the purpose can be produced.

However, such parameters are generally not adjustable for individual TFTs formed on one substrate. For example, in an actual circuit, although low speed operation | movement and high breakdown voltage TFT may be sufficient on one board | substrate, it may be desirable to simultaneously form TFT which requires high speed operation | movement simultaneously. In general, in the present invention, the larger the width of the offset region, the smaller the off current and the higher the pressure resistance, but the lower the operating speed.

This embodiment shows an example of solving such a problem. 14 shows the present embodiment (cross section) and 15 (plan view). In this embodiment, the P-channel TFT and the N-channel TFT as described in Japanese Patent Application No. 3-296331 (Japanese Patent Application) are used to drive one pixel (liquid crystal pixel or the like). The present invention relates to the fabrication of circuits used. Here, the N-channel TFT is required to have high speed, and breakdown voltage is not a problem. On the other hand, the operation speed of P-channel TFTs is not a problem, but it is necessary to have a low off-current and, in some cases, also need a good breakdown voltage. Therefore, it is preferable that the N-channel TFT is thin (20-100 nm) and the P-channel TFT is thick. The manufacturing process is demonstrated below.

As shown in Figs. 14A and 15A, Corning 7059 (product name) is used as the substrate 101, and a substantially intrinsic amorphous or polycrystalline semiconductor, for example, an amorphous silicon film, has a thickness of only 50 nm. The N-channel TFT region 102 and the P-channel TFT region 103 are formed by patterning them into islands. This was annealed at 600 ° C. for 60 hours in a nitrogen atmosphere to recrystallize. The silicon oxide film was deposited by the thickness of 15 nm as the gate oxide film 104 by the ECR plasma CVD method. When movable ions, such as sodium, exist in the silicon oxide film formed in this way, it is preferable to remove the obstacle by a movable ion by injecting movable ions, such as phosphorus. For example, these elements can be implanted by ion doping (also called plasma doping).

According to the findings of the present inventors, phosphorus introduced into silicon oxide by the ion doping method effectively functions as a getter of sodium. In the ion doping method, the acceleration voltage of phosphorus ions is set to 2 to 30 KeV, for example, 10 KeV, and the pressure in the vicinity of the doped target (in this case, silicon oxide film) is 2 ± 10 ^-5 to 5 × 10 ^-4 torr. , For example, 1 × 10 ⁻⁴ torr. The phosphorus concentration was 5 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻² , for example, 2 × 10 ¹⁴ cm ⁻² and less than the impurity implantation amount during the formation of an impurity region of a conventional MOS transistor.

After injecting phosphorus in this way, annealing was carried out at 600 ° C. for 24 hours in a nitrogen atmosphere to remove defects in the silicon oxide film generated during ion doping. In this way, by injecting phosphorus into the silicon oxide film, deterioration of characteristics due to movable ions can be significantly reduced and reliability can be improved. For example, in the MOS capacitor with silicon oxide formed by the above method, the voltage fluctuation was only 1 V when the bias / temperature treatment (BT treatment) of 150 ° C. for 1 hour ± 20 V. On the other hand, when phosphorus implantation as described above was not performed, the threshold voltage varied by more than 10V.

After forming the silicon oxide film in this manner, a film of tantalum, which is a heat-resistant metal, was formed by a thickness of 500 nm by the sputtering method, and then patterned to form a gate electrode portion 105 of the N-channel TFT and a gate electrode portion 106 of the P-channel TFT. Formed). Instead of tantalum, polycrystalline silicon with a low resistance (added with impurities) may be used. The channel size at this time was 8 micrometers in length, and 8 micrometers in width. In addition, all the gate electrodes and wirings are electrically connected to the common wiring 150 as shown in fifteenth (a). Furthermore, aluminum oxide films 107 and 108 were formed around the gate electrodes and lines 105 and 106 (top and side surfaces) by anodizing through the gate electrodes and wirings 150 through electricity. . Anodization was carried out under the same conditions as in Example 2. However, the maximum voltage was 50V. Therefore, the thickness of the anodic oxide film produced in this step is about 60 nm. (FIG. 14B) Next, in FIG. 15B, as shown by 151, the gate electrode wiring 05 is removed. It separated from the wiring 150 by laser etching.

In this state, anodization was started again. The conditions were the same as before, but the maximum voltage was raised to 250V. As a result, since no current flowed through the wiring 105, no change occurred. However, since the current flows through the wiring 106, a tantalum oxide film 109 having a thickness of about 300 nm is formed around the gate wiring 106. Degrees (c))

Thereafter, impurities were implanted into the island forming semiconductors 102 and 103 by ion doping. By employing a known CMOS technology, phosphorus (P) was implanted into the semiconductor region 102 and boron (b) was implanted into the semiconductor region 103. The energy of ion doping was 80 KV. As far as the present inventors know, when ion doping through the gate insulating film of thickness 100-300 nm, when this energy exceeds 100 KeV, the crystallinity of a semiconductor by ion implantation energy will be remarkably destroyed, and such impurities In order to activate the diffusion region, a high temperature of 600 ° C or higher is required, but it is very difficult to increase the production efficiency of the product in such a process. However, if the energy of ion doping was 100 Ke or less, the resistance could be made low enough at 600 degrees C or less, for example, 450-500 degreeC. After ion doping, by performing annealing at 500 ° C. for 30 hours in a nitrogen atmosphere, the sheet resistance of the source / drain regions could be sufficiently low. The state thus far is shown in Fig. 14 (d). As is clear from the figure, the width of the offset of the left TFT is small, and the width of the offset of the TFT of the right is large. Thereafter, by a known technique, necessary portions of the metal wirings 106 and 150 (for example, 152 and 153) are cut out, an interlayer insulating film is formed again, a contact hole is formed, and wiring is formed on each electrode (eg 112). B) 113) was formed to complete the circuit as shown in Fig. 15C.

In the circuit fabricated as described above, the N-channel TFT has a small width of the offset region and a little large off current, but was excellent in high speed. On the other hand, although the P-channel TFT was difficult in high speed operation, the off current was low and the ability to hold the charge accumulated in the pixel capacitor was excellent.

Thus, there are other cases in which TFTs having different functions must be integrated on one substrate. For example, in a liquid crystal display driver, a high speed TFT is required for a logic circuit such as a shift register, and a high breakdown voltage TFT is required for an output circuit. In the case of manufacturing a TFT in accordance with such an opposite purpose, the method shown in this embodiment is effective.

Example 4

In the TFT obtained by the present invention, not only the off current but also the breakdown voltage and operating speed between the source and the drain change depending on the width of the offset region. Therefore, for example, by optimizing the parameters such as the thickness of the anodic oxide film, a TFT corresponding to the purpose can be produced. However, such parameters are generally not adjustable for individual TFTs formed on one substrate. For example, in an actual circuit, it may be desirable to simultaneously form a low-speed operation, a high breakdown voltage TFT and a low breakdown voltage on one substrate, but simultaneously form a TFT requiring high-speed operation. In general, in the present invention, the larger the width of the offset region, the smaller the off current and the higher the pressure resistance, but the lower the operating speed.

This embodiment shows an example of solving such a problem. 14 shows the present embodiment (cross section) and 15 (plan view). In this embodiment, a P-channel TFT and an N-channel TFT as described in Japanese Patent Application No. 3-296331 are used to fabricate a circuit used in an image display method using a single pixel (liquid crystal pixel, etc.). It is about. Here, the N-channel TFT is required to have high speed, and breakdown voltage is not a problem. On the other hand, the operation speed of the P-channel TFT is not a problem, but it is necessary to have a low off-current and, in some cases, also need a good breakdown voltage. Therefore, it is preferable that the N-channel TFT has a thin anode line film (20 to 100 nm) and the P-channel TFT has a thick anodic oxide film (250 to 400 nm). The manufacturing process is demonstrated below.

As shown in FIGS. 14A and 15A, Corning 7059 (product name) is used as the substrate 101, and a substantially intrinsic amorphous or polycrystalline semiconductor, for example, an amorphous silicon film is formed. It was formed by 50 nm and patterned into an island shape to form an N-channel TFT region 102 and a P-channel TFT region 103. This was annealed and recrystallized at 600 DEG C for 60 hours in a nitrogen atmosphere.

Then, as the gate oxide film 104 by the ECR plasma CVD method, a silicon oxide film is deposited by 115 nm in thickness, and a film of tantalum, which is a heat-resistant metal, is formed by a thickness of 500 nm by the sputtering method, and patterned to form an N-channel TFT. The gate electrode portion 105 and the gate electrode of the P-channel TFT were formed. Instead of tantalum, polycrystalline silicon having low resistance (added with impurities) may also be used. At this time, the channel size was 8 µm in length and 8 µm in width.

In addition, all the gate electrode wirings are electrically connected to the common wiring 150 as shown in Fig. 15A. In addition, the aluminum oxide films 107 and 108 are applied to the gate electrodes and wirings 150 through the anodic oxidation method and around (top and side surfaces) of the gate electrodes and wirings 105 and 106. Formed. Anodization was carried out under the same conditions as in Example 2. However, the maximum voltage was 50V. Therefore, the thickness of the anodic oxide film produced in this step was about 60 nm (Fig. 14 (b)).

Next, in FIG. 15B, as shown at 151, the gate electrode wiring 150 is separated from the wiring 150 by laser etching.

The conditions were the same as before, but at this time, the maximum voltage was raised to 250V. As a result, since no current flows through the wiring 105, no change occurs. However, since a current flows through the wiring 106, a tantalum oxide film 109 having a thickness of about 300 nm is formed around the gate wiring 106. (Figure 14 (c))

Thereafter, impurities were implanted into the island-like semiconductors 102 and 103 by ion doping. By employing a known CMOS technology, phosphorus (P) was introduced into the semiconductor region 102 and boron (b) was introduced into the semiconductor region 103. The energy of ion doping was 80 KeV. As far as the present inventors know, if this energy exceeds 10 KeV, high temperature of 600 degreeC or more was required in order to activate an impurity diffused region, but it is very difficult to raise the manufacturing efficiency of a product by such a process. However, if the energy of ion doping was 100 KeV or less, 600 degreeC or less, for example, 450-500 degreeC could be made into low enough resistance.

After ion doping, the sheet resistance of the source / drain region could be sufficiently low by performing annealing at 500 ° C. for 30 hours in a nitrogen atmosphere. The state thus far is shown in Fig. 14 (d). As is clear from the figure, the width of the offset of the TFT on the left is small, and the width of the offset of the TFT on the right is large. Thereafter, by a known technique, necessary portions (for example, 152 and 153) of the metal wirings 106 and 150 are cut off, and an interlayer insulating film is formed again, a contact hole is formed, and wirings (for example, 112 and 113) to complete the circuit as shown in Fig. 15C.

In the circuit fabricated in this manner, the N-channel TFT had a small width of the offset region and a little large off current, but was excellent in high speed.

On the other hand, although the P-channel TFT was difficult in high speed operation, there was little off current and the ability to hold the electric charge accumulated in the pixel capacitor was excellent.

Example 5

18 shows a sectional view of this embodiment. First, Corning 7059 (product name) glass was used as the substrate 501. It formed by sputtering method only as thickness of 100 nm. Again, the amorphous silicon film 503 was formed by 50 nm by the plasma CVD method. The silicon oxide film 504 was also formed by 20 nm by sputtering for the purpose of protecting the amorphous silicon film thereon. It was annealed in nitrogen atmosphere at 600 ° C. for 72 hours and recrystallized. Again, this was patterned by photolithography and reactive ion etching (RIE) to form island-like semiconductor regions as shown in Fig. 18A. After the island-like semiconductor region was formed, the protective silicon oxide film 504 was removed. The removal was performed by wet eticheng using a buffer hydrofluoric acid (a solution in which hydrogen fluoride and ammonium fluoride were mixed). As the buffer hydrofluoric acid, for example, a high-purity hydrofluoric acid (50 wt%) for manufacturing semiconductors and an ammonium fluoride solution (40 wt%) were mixed at a ratio of 1:10. In addition, the etching rate with respect to silicon oxide of this buffer hydrofluoric acid was 70 nm / min, similarly 60 nm / min in aluminum oxide, and 150 nm / min in aluminum. Again, the gate oxide film 505 was deposited by 115 nm in thickness by the sputtering method in an oxygen atmosphere targeted at silicon oxide. In this state, phosphorus ions were added to the gate oxide film 505 by plasma doping. This is for removing movable ions such as sodium present in the gate oxide film, and may not be performed when the concentration of sodium is low enough to not interfere with the operation of the device. In this embodiment, the plasma acceleration voltage was 10 KeV and the injection amount was 2 x 10 ¹⁴ cm ^-2 . Subsequently, annealing was performed at 600 ° C. for 24 hours to recover damages of the oxide film and the silicon film caused by the impact of plasma injection.

Next, the aluminum film was formed by the sputtering method, and this was patterned by the mixed acid (phosphate solution which added 5% acetic acid), and the gate electrode wiring 506 was formed. The etching rate was 225 nm / min when the temperature of etching was 40 degreeC. In this way, the external shape of the TFT was adjusted. The channel size at this time was 8 micrometers in length, and 20 micrometers in width.

Next, an N-type impurity region (source, drain) 507 was formed in the semiconductor region by the ion implantation method. Phosphorus ion was used as an impurity, ion energy was 80 KeV, and the injection amount was 5 * 10 <^15> cm <^-2> . As shown in the figure, doping was carried out by a through impeller through which an impurity was introduced to penetrate the oxide film. The advantage of using such a draw impeller is that the surface of the impurity region remains smooth during the recrystallization process by later laser annealing. In the case of non-drug impellers, a large number of crystal nuclei are generated on the surface of the impurity region during recrystallization, and irregularities are formed on the surface. In this way, a structure was obtained as shown in Fig. 18B. Further, as a matter of course, the crystal of the portion into which the impurity is implanted by such ion implantation is significantly weakened, and is substantially in an amorphous state (amorphous state or a polycrystalline state close thereto). Furthermore, an aluminum oxide film 508 was formed in the periphery (upper surface and side surfaces) of the gate electrode and wiring through the wiring 506 through electricity. Anodic oxidation was carried out using a solution in which an ethylene glycol solution of tartaric acid of 3% was neutralized with 5% ammonia and the pH was 7.0 ± 0.2 ° C. First, platinum was immersed in a solution as a cathode, TFT was immersed for each board | substrate again, and the wiring 506 was connected to the anode of a power supply. The temperature was kept at 25 ± 2 ° C.

In this state, when a current of 0.5 mA / cm 2 is first flowed and the voltage reaches 200 V, the current is kept energized while the current is kept constant. When the current reaches 0.005 mA / cm 2, the current is cut off and the anodization is terminated. The thickness of the anodic oxide film thus obtained was about 250 nm. The shape is shown in Fig. 18C.

Thereafter, laser annealing was performed. The laser irradiated 10 shots of the laser pulse of the power density of 350 mJ / cm <2>, for example using KrF excimer laser. It has been confirmed by at least one laser irradiation that the crystallinity of the silicon in the amorphous state can be recovered until it can withstand the operation of the TFT. However, in order to sufficiently reduce the probability of occurrence of defects due to variations in the laser power, a sufficient number of times Laser irradiation is preferred. However, since too many laser irradiations lower productivity, it is clear that about 10 times used in this embodiment is most preferable.

Laser annealing was performed at atmospheric pressure in order to improve mass productivity.

Since the silicon oxide film is already formed on the impurity region, there is no particular problem. Even if laser annealing is performed in the state in which the impurity region is exposed, coral penetrates into the impurity region from the air at the same time as crystallization, and the crystallinity is not good. Thus, a TFT having sufficient characteristics could not be obtained. Therefore, it was necessary to perform laser annealing in vacuum that the impurity region was exposed. In addition, in the present Example, as shown in FIG. 18 (d), a biscuit was made to enter a laser beam. For example, in the present Example, the laser beam was irradiated at the angle of 10 degrees with respect to the perpendicular | vertical line of a board | substrate. The angle is determined according to the design specifications of the device to be manufactured. By doing in this way, the area | region crystallized by a laser among impurity areas can be made asymmetric. That is, the regions 509 and 510 in the figure are impurity regions sufficiently crystallized. The region 511 is not an impurity region, but is a region crystallized by laser light. Region 512 is an impurity region but is not crystallized. For example, an impurity region on the right side of FIG. 18 (d) may be used on the drain side where hot electrons are easily generated.

In this way, the shape of the element was arranged. Thereafter, an interlayer insulator is formed by sputtering film formation of silicon oxide in a conventional manner, holes for electrodes are formed by known photolithography techniques, and the surface of the semiconductor region or the gate electrode / wiring is exposed, and finally a metal The film was selectively formed to complete the device.

Example 6

In the TFT obtained by the present invention, not only the off current but also the breakdown voltage and operating speed between the source and the drain vary depending on the width of the amorphous semiconductor region and the offset region. Therefore, for example, by optimizing the parameters such as the thickness of the anodic oxide film, the ion implantation energy, and the like, a TFT that meets the purpose can be produced. However, these parameters are generally not adjustable for individual TFTs formed on one substrate. For example, in an actual circuit, it may be desirable to simultaneously form a low voltage operation, a high breakdown voltage TFT and a low breakdown voltage TFT on one substrate which are required for high speed operation. In general, in the present invention, the larger the width of the offset region or the width of the amorphous impurity semiconductor region, the smaller the off current and the higher the pressure resistance, but the lower the operating speed.

This embodiment shows an example of solving such a problem. FIG. 22 (top view) and 19 (sectional view) show this embodiment. In this embodiment, in particular, in the fabrication of a circuit used in an image display method using a P-channel TFT and an N-channel TFT as described in H3-396331 to drive one pixel (liquid crystal pixel, etc.). It is about. Here, the N-channel TFT is required to have high speed, and breakdown voltage is not a problem. On the other hand, the operation speed of the P-channel TFT is not a problem, but it is necessary to have a low off-current and, in some cases, also need a good breakdown voltage. Therefore, it is preferable that the N-channel TFT has a thin anodic oxide film (20-100 nm), and the P-channel TFT has a thick anodic oxide film. The manufacturing process is demonstrated below.

In the same manner as in Example 5, Corning 7059 (product name) was used as the substrate 601, and the N-type impurity region 602, the P-type impurity region 603, the gate insulating film 604, and the gate electrode and wiring were All are connected to the wiring 650. (Fig. 22 (a)), 189 (a))

In addition, an aluminum oxide film 613 is formed around the gate electrodes and wirings 606 and 607 by electricity through the gate electrodes and wirings 606 and 607, and by anodizing. Formed 614. Anodic coral was performed under the same conditions as in Example 5. However, the maximum voltage was 50V. Therefore, the thickness of the anodic oxide film produced by this process is about 60 nm (Fig. 19 (b)).

Next, as shown at 651 in Fig. 22B, the gate electrode wiring 606 was separated from the wiring 650 by laser etching. In this state, anodization was started again. The conditions were the same as before, but the maximum voltage was raised to 250V at this time. As a result, no change occurred because no current flowed through the wiring 606, but because an electric current flows through the wiring 607, an aluminum oxide film 615 having a thickness of 300 nm is formed around the gate wiring 607. (19 (c))

Thereafter, laser annealing was performed. The conditions were the same as in Example 5. In this case, the N-channel TFT (left side of FIG. 19) is narrow enough that the width al of the amorphous region and the offset region is negligible, but irradiates with laser light unless the surface of the aluminum wiring is covered by the anodization film. Because of the remarkable damage, it was necessary to form an anode line film even if it was thin. On the other hand, in the P-channel TFT (right side of FIG. 19), the thickness of the anodic oxide film was 300 nm and the amorphous region also existed 150 to 200 nm. The width a2 of the offset region is also estimated to be 100 to 150 nm. (Fig. 19 (d).

As in the case of Example 5, by laser irradiation in the air, a necessary portion of the aluminum wiring was etched, the P-channel TFT gate electrode was separated from the wiring 607, and the wiring 650 was sheared. Then, an interlayer insulating film was formed, contact holes were formed, and wirings 624 and 611 were formed. In this way, a circuit was formed.

In the circuit fabricated in this manner, the N-channel TFT has a small width of the offset region and the amorphous region and a little large off current, but has excellent speed. On the other hand, although the P-channel TFT was difficult in high speed operation, the off current was small and the ability to hold the charge accumulated in the pixel capacitor was excellent.

Thus, there are other cases where TFTs having different functions must be integrated on one substrate. For example, in a liquid crystal display driver, a high speed TFT is required for a logic circuit such as a shift register, and a high breakdown voltage TFT is required for an output circuit. In the case of manufacturing a TFT according to such an opposite purpose, the method shown in this embodiment is effective.

Example 7

Using the fabrication method used in Example 1 of the present invention, an active matrix circuit composed of N-channel TFTs as shown in FIG. 20 was fabricated. In other words, the active matrix is a matrix of the gate line 701 and the data line 702, and both of them are made of aluminum having low resistance. In the present invention, since the anodization process is performed, aluminum oxide having a thickness of 200 to 40 nm is used. It is covered by. These line widths were 2 micrometers. In addition, the thickness was 0.5 micrometer. In addition, a gate electrode 703 of the TFT of each pixel is provided on the gate line. This is similarly covered with aluminum oxide. A semiconductor layer 704 is formed under the gate electrode, and there is an N-type polycrystalline impurity region to which phosphorus is added in the same way as the N-channel TFT of Example 1, and the characteristic of the present invention is its width with respect to the offset region. Is designed to be about 200-400nm. The source of this semiconductor layer is connected to the data line 702, while the drain is connected to the display pixel electrode (made of ITO) 706 via the aluminum electrode 705.

FIG. 21 shows a circuit diagram of the active matrix device fabricated in this embodiment and the operation of the device using a TFT fabricated by a conventional method for the operation and comparison of the device of this embodiment. As described above, in the matrix of the structure as described above, when the charging of the capacitor c is terminated and the gate voltage is turned off, the capacitor c is gated through the parasitic capacitance c of the gate and the drain. It is known that the capacitance is coupled to the line and the voltage drops by ΔV from the charging voltage thereof.

This phenomenon is the same as the circuit in which the N-channel TFT and the P-channel TFT are connected in parallel as in the first embodiment. The details are described in the application type 3-208648 filed by the present inventors.

As shown in Fig. 21, the voltage drop ΔV is represented by V = C V / (C + C) in a circuit composed of only one TFT, either N channel or P channel. Here, V is the variation range from the on voltage of the gate voltage to the off voltage. For example, in the TFT fabricated without using the self-array, the parasitic capacitance c is significantly large, so that ΔV becomes large, and to overcome this, the storage capacitance c is parallel to the pixel capacitor as shown in FIG. And the capacitance of the pixel capacitor was enlarged in appearance. However, such a measure could not solve the problem inherently, and it was as mentioned above that the problem of the opening ratio was newly raised.

This voltage drop becomes a serious problem when the pixel size is also manufactured in the self-aligned method and the parasitic capacitance of the TFT cannot be ignored as compared with the pixel capacitor. For example, in a diagonal 3-inch high-vision panel (for projection), the pixel capacity is very small, 13 fF. On the other hand, when the TFT is manufactured by employing the 2 μm method in the process, the aspect ratio of the wiring is large and parasitic capacitance is generated in three-dimensional geometry even if there is no planar overlap, and the size may reach several fF. That is, 10% or more of the pixel capacitor capacity is reached.

Although Fig. 21A shows an example of an active matrix using a conventional TFT, it is clearly impossible to display the original display due to? V. That is, in order to operate the TFT at high speed, the gate voltage is required to be higher than the drain voltage. Usually, a voltage about twice the drain voltage is employed as the gate voltage. Therefore, when the drain voltage is 5V, the gate voltage is 10V or more. Further, for the purpose of perfecting the operation of the TFT, the change in the gate voltage becomes larger when the gate voltage is made negative in the off state. For example, in the case of Fig. 21, the drain voltage is an alternating current of + 6V, but the gate voltage is + 12V in the on state and -4V in the off state, so that V = 16V in the above equation. If the parasitic capacitance is 2fF, as shown in Fig. 21A,? V is 2V and is actually 1/3 of the drain charging voltage. Of course, since the electric charges accumulated in the pixels are discharged by natural discharge, it is difficult to actually perform the display more abnormally. And in order to avoid such a problem, the storage capacity had to be installed at the expense of the aperture ratio.

On the other hand, when the present invention is applied, the parasitic capacity can be significantly reduced. Specifically, it can be 0.1fF or less. Thus, as shown in Fig. 21B,? U can be almost ignored. In addition, in the present invention, since the off current is about one digit less than that of the TFT produced by the conventional method, the natural discharge is also very gentle, and the display can be extremely ideally performed.

Thus, in the present invention, by providing an insulating layer of anodization on the surface of the gate electrode, the channel length is longer than the length of the gate electrode in the channel length direction, and the electric field by the gate electrode is not applied to both sides of the channel region. An offset region that takes a very weak electric field can be provided, or an amorphous impurity semiconductor region having the same effect can be provided by the same method, and the leakage current at the reverse bias can be reduced.

As a result, the charge holding capacity required by the prior art becomes unnecessary, and the aperture ratio which was about 20% of the conventional can be made 35% or more, and better display quality was obtained.

In the present invention, since the offset region or the amorphous impurity region is determined by the thickness of the anodic oxide film of the gate electrode, the width of these regions can be controlled very precisely between 10 and 100 nm. Moreover, the addition of this step significantly reduced the production efficiency, which was not particularly found, and there was no factor that could be considered as a cause of the decrease in production efficiency.

Although the present invention has been mainly described with respect to silicon-based semiconductor devices, it is obvious that the present invention can be applied to semiconductor devices using other materials such as germanium, silicon carbide, gallium arsenide, and the like.

Claims (15)

A substrate having an insulating surface, a pixel semiconductor formed on the insulating surface, a source semiconductor layer and a drain semiconductor layer on an insulating surface of a substrate including a source region and a drain region, a channel semiconductor layer interposed between the source region and the drain region, A gate electrode formed on the channel semiconductor layer, the source semiconductor layer and the drain semiconductor layer, the gate insulating layer formed between the gate electrode and the channel semiconductor layer, and a thin film transistor connected to the pixel electrode, on the substrate And a transparent organic resin film covering the thin film transistor, wherein the pixel electrode is formed on an upper surface thereof, wherein the channel semiconductor layer of the thin film transistor is part of the channel semiconductor layer and extends over a side edge of the gate electrode. At least one offset The electro-optical device, characterized by the gateum station. A substrate having an insulating surface, a pixel electrode formed only on the insulating layer, a pair of impurity regions having a first conductivity type, and a channel semiconductor layer having a second conductivity type extending between the pair of impurity regions And one of the impurity regions is connected to the pixel electrode, the semiconductor layer formed on the insulating surface (of the substrate), the gate insulating layer formed adjacent to the channel semiconductor layer, and the gate formed adjacent to the gate insulating layer. At least one of the pair of impurity regions including an electrode, a thin film transistor formed on the insulating surface, the pixel, and an electrode formed on an upper surface of the substrate, the transparent organic resin film formed on the substrate and covering the thin film transistor; The first region includes a first region adjacent to the channel semiconductor layer and a second region away from the channel semiconductor layer. And a second region having the same conductivity type, wherein the first region (having a lower conductivity than the second region) comprises a lower concentration of ionized dopant impurities than the second region, And the boundary between the first regions is offset outward from the side edge of the gate electrode. A semiconductor layer comprising a source, a drain, and a channel formed therebetween, the thin film transistor formed on an insulating surface of a substrate, a gate insulating layer formed on the semiconductor layer, a gate electrode formed on the gate insulating layer, and the gate An anodizing coating film formed on the surface of the electrode, a first insertion insulating layer formed on the thin film transistor, a wire formed on the source and drain of the thin film transistor, a wiring formed on the first insertion insulating layer, and a transparent organic material formed on the wiring A second insertion insulating layer including a resin film, and a pixel, an electrode, electrically connected to the other of the source and the drain of the thin film transistor, and formed on the transparent organic resin film (the second insertion insulating layer), A boundary between the channel and one of the source and drain is connected to the gate electrode. Electro-optic device, characterized in that offset from the side edge to the outside. A substrate having an insulating surface, a pixel electrode formed on the insulating surface, at least a channel semiconductor layer, a pair of impurity regions extending between the channel semiconductor layer, a gate insulating film formed on the channel semiconductor layer, a gate formed on the gate insulating film A thin film transistor including an electrode, wherein the pixel electrode is electrically connected to one of the pair of impurity regions, the pixel electrode is formed on an upper surface, and a transparent organic resin film formed on the thin film transistor, And anodizing film formed by anodizing the outer surface of the gate electrode. The electro-optical device according to claim 1, wherein the transparent organic resin film comprises polyimide. The electro-optical device according to claim 2, wherein the transparent organic resin film comprises polyimide. The electro-optical device according to claim 3, wherein the transparent organic resin film comprises polyimide. A source semiconductor layer and a drain semiconductor layer on an insulating surface of a substrate including a substrate having an insulating film, a pixel electrode formed on the insulating surface, a source region and a drain region, and a channel channel layer interposed between the source region and the drain region, A gate insulating layer formed on the source semiconductor layer and a drain semiconductor layer, and a gate electrode formed on the channel semiconductor layer, wherein the gate insulating layer is formed between the gate electrode and the channel semiconductor layer while being connected to the pixel electrode. And a thin film transistor formed on the substrate, the transparent planar chemistry covering the thin film transistor, wherein the pixel electrode is formed on the planarized surface of the transparent planarization layer, and the channel semiconductor layer of the thin film transistor is the channel semiconductor layer. Being part of, the gate electrode Electro-optical device characterized in that it has at least one off region which extends beyond the side edges. A substrate having a creepage surface, a pixel electrode formed on the insulating surface, a pair of impurity regions having a first conductivity type, and a channel semiconductor layer having a second conductivity type extending between the pair of impurity regions; And one of the impurity regions formed on the insulating surface, the semiconductor layer connected to the pixel electrode, a gate insulating layer formed adjacent to the channel semiconductor layer, and formed adjacent to the gate insulating layer. The layer includes a gate electrode interposed between the gate electrode and the channel semiconductor layer, and includes a thin film transistor formed on the insulating surface and a transparent planarization film formed on the substrate and covering the thin film transistor. Is formed on the planarized surface of the transparent planarization film, the minimum of the pair of impurity regions One has a first region adjacent to the channel semiconductor layer and a second region away from the channel semiconductor layer, wherein the first region and the second region have the same conductivity type, and the first region is the second region. And a lower concentration of ionized dopant impurity, wherein a boundary between the channel semiconductor layer and the first region is offset outward from a side edge of the gate electrode. A semiconductor layer comprising a source, a drain, and a channel formed therebetween, the thin film transistor formed on an insulating surface of the substrate, a gate insulating layer formed on the semiconductor layer, a gate electrode formed on the gate insulating layer, and the gate electrode An anodizing coating layer formed on a surface of the first insulating layer formed on the thin film transistor, a first insertion insulating layer formed on the thin film transistor, a wiring connected to one of the source and drain of the thin film transistor, and formed on the wiring line, A transparent planarization film having a planarized top surface, a pixel electrode formed on the planarized top surface, the pixel electrode being electrically connected to the other of the source and the drain of the thin film transistor, the boundary between the channel and one of the source and the drain Is outward from the side edge of the gate electrode. Electro-optic device, characterized in that the preset. A substrate having an insulating surface, a pixel electrode formed on the insulating surface, at least a channel semiconductor layer, a pair of impurity regions extending between the channel semiconductor layer, a gate insulating film formed on the channel semiconductor layer, a gate formed on the gate insulating film An electrode, the pixel electrode comprising a thin film transistor electrically connected to one of the pair of impurity regions, a planarized top surface, and a transparent planarization film formed on the thin film transistor, wherein the pixel electrode is disposed on the planarized surface. And an anode oxide film formed by anodization of an outer surface of the gate electrode. The electro-optical device according to claim 8, wherein the transparent planarization film comprises a transparent polyimide. The electro-optical device according to claim 9, wherein the transparent planarization film comprises polyimide. The electro-optical device according to claim 10, wherein the transparent planarization film comprises a transparent polyimide. The electro-optical device according to claim 11, wherein the transparent planarization film comprises a transparent polyimide.