JPH10313119A - Insulated gate field effect semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the aspect ratio of the gate electrode by forming first impurity region near channel semiconductor layer, second impurity region apart therefrom and the first regions having a lower impurity concn. than that of the second regions. SOLUTION: This device is manufactured by forming a low-temp. oxidized film 302 and Si film on a quartz substrate 301, forming a gate oxide film 304 and portions 303 to be gate electrodes, implanting As ions to form n<-> -type impurity regions 305 involving first regions, oxidizing the portions 303 to form an Al oxide film 306, implanting As ions to form n<-> -type impurity regions 307 to be second regions, and performing laser irradiation to form first uncrystallized regions 308 and second crystallized regions 307 below the gate electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect type semiconductor device (semiconductor device) which is excellent in high speed and can be highly integrated. The semiconductor device according to the present invention comprises:
It is used for a microprocessor, a microcontroller, a microcomputer, a semiconductor memory, or the like.

[0002]

2. Description of the Related Art Many researches and developments have been made on miniaturization and high integration of semiconductor devices. In particular, MOSF
A remarkable progress has been made in the miniaturization technology of an insulated gate field effect type semiconductor element called ET. MOS stands for Metal
-Oxide-An abbreviation for Semiconductor. A metal is not limited to a pure metal, but is used in a broad sense including a semiconductor material having sufficiently high electrical conductivity and an alloy of a semiconductor and a metal. In addition, instead of an oxide between a metal and a semiconductor, not only a pure oxide but also an insulating material having a sufficiently high resistance such as a nitride may be used. Is MOS
Although the term is not correct, in the present specification, a field-effect element having such a structure, including a nitride and other insulators, will be referred to as a MOSFET hereinafter.

The miniaturization of a MOSFET is performed by reducing the width of a gate electrode. Reducing the width of the gate electrode means reducing the length of the underlying channel region, i.e., the channel length, which reduces the time required for carriers to pass through the channel length. As a result, the speed is increased as well as the integration becomes higher.

[0004] However, this also causes another problem (short channel effect). The most important of these is the hot electron problem. As before,
In a structure in which a channel region doped with impurities of opposite polarity is sandwiched between impurity regions of a source and a drain having sufficiently high impurity concentrations, the voltage applied to the source and the drain increases as the channel region is narrowed. The electric field near the boundary between the channel region and the impurity region increases. As a result, the operation of the MOSFET becomes extremely unstable.

[0005] The structure of a new MOSFET proposed to solve such a problem is a lightly-doped LDD (LDD).
ped-Drain). This is typically shown in FIG.
It is shown in (D). In FIG. 2D, a region 207 having a low impurity concentration provided shallower than the region 206 having a high impurity concentration is referred to as an LDD. By providing such a region, the electric field near the boundary between the channel region and the impurity region can be reduced and the operation of the element can be stabilized.

The LDD is usually formed as shown in FIG. FIG. 2 shows an example of an NMOS, but a PMOS may be formed similarly. First, an oxide film and a conductive film are formed on a p-type semiconductor substrate, and these are etched to form a gate insulating film 202 and a gate electrode 201 as shown in FIG. Then, using this gate electrode as a mask, an impurity region 203 having a relatively low impurity concentration (indicated by n ^{− in the} symbol) is formed in a self-aligned (self-aligned) manner by, for example, ion implantation.

Next, an insulating film 204 such as PSG is formed thereon. And this insulating film 204
Although it is removed by an anisotropic etching method (also called a directional etching method) such as a bias plasma etch, as a result of the anisotropic etching, P
The SG is not etched and remains in a shape as indicated by 205 in FIG. This residue is called a spacer. Then, using the spacer 205 as a mask, an impurity region 206 having a high impurity concentration (indicated by n ^{+ in the} symbol) is formed in a self-aligned manner. This n ⁺ -type impurity region is used as a source and a drain of the FET.

It has been shown that by adopting such an LDD structure, it is possible to reduce the channel length, which is said to be 0.5 μm as the limit in the conventional method, to 0.1 μm.

[0009]

However, this does not completely solve the problem of shortening the channel. Another problem is the problem of the resistance of the gate electrode caused by reducing the gate width. Even if the operating speed is improved by shortening the channel, if the resistance of the gate electrode is large, the propagation speed is reduced by compensating for that. In order to reduce the resistance of the gate electrode, for example, a metal silicide having a small resistivity is used instead of the conventionally used polycrystalline silicon having a high impurity concentration, or a low-resistance wiring such as aluminum is used in parallel with the gate electrode. Has been studied and adopted, but it is expected that the limit will be reached in situations where the width of the gate electrode is 0.3 μm or less.

As another solution in that case, it is conceivable to increase the ratio (aspect ratio) between the height and the width of the gate electrode. By increasing the aspect ratio of the gate electrode, it is possible to increase the cross-sectional area of the gate electrode and reduce the resistance. However, conventional LDD
Cannot increase the aspect ratio indefinitely due to a problem in its fabrication.

This is because the width of the spacer formed by anisotropic etching depends on the height of the gate electrode.
Usually, the width of the spacer was 20% or more of the height of the gate electrode. Therefore, the width L of the LDD region 207 in FIG.
Is 0.1 μm, the height h of the gate electrode must be 0.5 μm or less. If the height of the gate electrode is more than that, L will be 0.1 μm or more. This means that the resistance between the source and the drain increases, which is not desirable.

The height h of the gate electrode is 0.5 μm, the width W of the gate electrode is 1.0 μm, and the width L of the LDD is 0.1 μm.
Let m. By reducing the scale of this element,
If W is to be 0.5 μm, h must be 1.0 μm in order to maintain the resistance of the gate electrode. However, for that reason, L becomes 0.2 μm. That is, although the resistance of the gate electrode does not change,
State (voltage is applied to the gate electrode, and the resistance of the channel region is sufficiently smaller than the resistance of the n ⁻ region)
, The resistance between the source and the drain is doubled. On the other hand, since the channel length has been reduced by half, the element can be expected to respond at twice the speed. However, since the resistance between the source and the drain has doubled, this is canceled.
As a result, only high integration of the device has been achieved, but the speed remains the same. On the other hand, h must be 0.5 μm in order to keep L the same as in the prior art. However, in this case, the resistance of the gate electrode is doubled, and eventually high speed cannot be obtained.

In a typical example, the width of the spacer is 50% to 100% of the height of the gate electrode, which is a much more difficult condition than that shown above. Therefore, in the conventional LDD manufacturing method, the aspect ratio of the gate electrode is 1 or less, and often 0.2 or less. In addition, the width of the spacer varies greatly, and the characteristics between the transistors often vary. As described above, the conventional LDD manufacturing method has provided stability in a short channel and accompanying high integration and high speed, but has a problem in manufacturing that hinders further higher speed and higher integration. Contradiction.

In recent years, in addition to a semiconductor single crystal substrate, a thin film semiconductor element is formed on an insulating substrate such as glass to form a semiconductor integrated circuit, or a thin film semiconductor element is formed on a single crystal semiconductor substrate. However, a thin-film semiconductor element may be formed on an insulating film formed thereon.
The former is found in liquid crystal displays and image sensors, and the latter is found in three-dimensional ICs. Such a thin film semiconductor is called T
Although called an FT (thin film transistor), an LDD structure may be required in this case as well. However,
For example, when a TFT is formed on a glass substrate having a large area, the thickness of the PSG varies depending on the location on the same substrate, so that there is a problem that the size of the spacer varies depending on the location.

Even in the case of a three-dimensional IC, if another element is provided below, it is difficult to keep the size of the spacer constant because the element is rarely formed horizontally. Conventionally, even in such a TFT, the LDD formation method as in the past has been used without sufficient consideration, so that sufficient characteristics and yield cannot be obtained.

The present invention proposes an entirely new method for overcoming the above problems as a method of fabricating an LDD structure in a TFT, and a completely new LDD type TFT.
Advocate.

[0017]

FIG. 1 shows a typical example of the present invention. The TFT obtained by the present invention is shown in FIG.
As shown in FIG. 3, a gate electrode 105 mainly made of titanium (Ti), aluminum (Al), tantalum (Ta), or chromium (Cr) alone or an alloy thereof and an anodic oxidation method provided around the gate electrode 105 are provided. An oxide layer 104 of the gate electrode, a gate insulating film 102 provided under the gate electrode, a pair of first impurity regions 107, and a pair of second impurity regions 106;
A channel region sandwiched between the first impurity regions.

FIG. 1 shows the case of an NMOS, but the PMOS
Can be similarly implemented. The procedure for implementing the present invention will be described. First, an insulating film such as an oxide film and the above-described metal film are formed on a thin-film semiconductor layer such as p-type silicon,
The insulating film and the metal film are etched to form a portion 101 to be a gate electrode and a gate insulating film 102 as shown in FIG. Then, using the portion to be the gate electrode as a mask, self-alignment (self-alignment) is performed.
For example, 1 × 10
^A first impurity region 103 having a low impurity concentration (represented by n ^{− in the} symbol) with a concentration of about ^{17 to} 5 × 10 ¹⁸ cm ⁻³ is formed.

Next, the surface of the portion to be the gate electrode is oxidized by an anodic oxidation method. By this process,
The surface of the part to be the gate electrode recedes. And
Eventually, the gate electrode 105 remains inside the oxide layer 104. (FIG. 1B) In this step, the positional relationship between the gate electrode and the impurity region 103 is different from that immediately after ion implantation. In the present invention, it is necessary to operate the element efficiently as a field-effect transistor, so that sufficient attention must be paid to the positional relationship between the gate electrode and the impurity region. That is, when the portion where the impurity region and the gate electrode do not overlap at all is extremely large (offset state), the channel is insufficiently formed. Conversely, when the impurity region and the gate electrode overlap more than necessary, the parasitic capacitance decreases. The occurrence causes a decrease in the operation speed and the like.

However, in the present invention, when the ion implantation method is used, the spread of the impurity region due to the secondary scattering of the ions can be calculated by the acceleration energy of the ions and the like. Since this is determined by the thickness of the material layer, this is also included as a design item. Therefore, in the present invention, the positional relationship between the gate electrode and the impurity region can be optimized by a precise design. That is, the thickness of the oxide layer can be controlled with an accuracy of 10 nm or less, and the secondary scattering at the time of ion implantation can be controlled to the same degree.
This positional relationship can be manufactured with an accuracy of 10 nm or less.

The gate electrode 105 formed in this manner and the oxide layer 104 around the gate electrode 105 are used as a mask.
The second having a high impurity concentration of 1 × 10 ^{20 to} 5 × 10 ²¹ cm ^-3 (represented by n ^{+ in the} symbol) in a self-aligned manner.
Impurity region 106 is formed. The first formed earlier
Impurity region remains at 107 in the figure and functions as an LDD. Thus, an LDD having the same shape as that obtained by the conventional LDD manufacturing method can be obtained. It should be noted in this process that the LD
Since the width L of D is not restricted by the height of the gate electrode, the aspect ratio of the gate electrode can be increased.

Further, according to the present invention, the width L of the LDD can be very finely controlled. For example, L is changed from 10 nm to 0.1
It can be arbitrarily changed up to μm. In addition, as described above, the overlap between the gate electrode and the LDD can be controlled with the same level of accuracy. At this time, the channel length W can be 0.5 μm or less. In the conventional method, it is extremely difficult to make the width of the LDD 100 nm or less, and an error of about 20% is natural. However, according to the present invention, when the width of the LDD is 10 to 100 nm, the width is about 10%. It is possible to manufacture with an error of.

Further, according to the present invention, as compared with the conventional LDD manufacturing method, there is no need to form an insulating film to be a spacer, so that the steps are simplified and the productivity is improved.
The thickness of the oxide obtained by the anodic oxidation method is the same on the side surface and the upper surface of the gate electrode, and is extremely uniform and has good insulating properties. In addition, no particular difference in thickness depending on the location on the substrate can be found.

The above example is for obtaining an LDD structure similar to the conventional one, but a function similar to the LDD is achieved by forming a substantially amorphous or semi-amorphous amorphous semiconductor region in the impurity region. Is achieved. An example is shown in FIG.

In FIG. 3, there is a gate electrode having a structure similar to that of FIG. Then, an impurity-doped amorphous semiconductor region 308 and a normal substantially polycrystalline or substantially single-crystal normal impurity region 307 are formed. The present inventors have found that by providing such a substantially amorphous region, the characteristics of the TFT can be improved as in the case of the LDD. Of course, it is necessary to sufficiently terminate dangling bonds in the semiconductor with hydrogen or halogen in this amorphous region so that the number of tangling bonds is reduced as much as possible.

By providing such an amorphous region, good TFT characteristics could be exhibited as shown in FIG. FIG. 4B shows a conventional TFT having no LDD structure or amorphous region. As is clear from FIG.
Drain current I _D when the gate voltage V _G is positive not only rapidly increases, even if V _G is negative I _D is required to have to remain constant low value would otherwise I _D Gradually increases. Such a characteristic is called reverse leakage, and is a serious problem when TFTs are operated complementarily.

On the other hand, when the semiconductor device has an amorphous region, ideal MOSFET characteristics are exhibited as shown in FIG. The reason why the characteristics are improved by providing the amorphous region in this manner has not yet been well understood.
For one thing, in the non-crystalline region, the ionization rate of the added impurity element is lower than that in the crystalline region, so that even if the same amount of impurity is added, the amorphous region has a lower impurity concentration. It is thought to behave as if. For example, in the amorphous state, silicon has an ionization rate of 0.1 to 10% at room temperature, which is significantly smaller than that of a single crystal or polycrystalline semiconductor (almost 100%).

Alternatively, the band gap is larger in the non-crystalline state than in the crystalline state. For example, it can be explained from the energy band diagrams as shown in FIGS. Normal LDD TFT
Then, the energy band diagrams of the source / channel / drain are as shown in FIGS. 4 (c) and 4 (d). The bulge in the center is the channel region. The step-like portion is an LDD region. When no voltage is applied to the gate electrode, it is shown in FIG. 4C, but when a large negative voltage is applied to the gate electrode, it becomes as shown in FIG. 4D. At this time, there is a forbidden band between the source and the channel region, and between the channel region and the drain, and carriers such as electrons and holes cannot move. However, hopping occurs due to tunneling or trap levels in the band gap. The carrier jumps over the gap. L
In the case of a normal TFT having no DD structure, a current flows more easily because the width of the gap is smaller. This is considered a reverse leak. This decrease is particularly remarkable in TFTs. This is presumed to be because TFT is an inhomogeneous material such as polycrystal and has many trap levels due to grain boundaries and the like.

On the other hand, when the band gap of the LDD region is increased, such reverse leakage is reduced. Examples in which the band gap of the LDD is large are shown in FIGS. FIG. 4E shows a state where no voltage is applied to the gate, and FIG. 4F shows a state where a large negative voltage is applied to the gate. As is clear from FIG.
The width of the gap between the source and the channel region or between the channel region and the drain when a negative voltage is applied is larger than that in (d). Tunneling is significantly affected by the width of the tunnel barrier (in this case the width of the gap), with a small increase in the width of the gap significantly reducing its probability. In addition, hopping via a local level is also a complex tunnel effect, so that the probability decreases dramatically as the gap width increases. For the above reasons, it is considered significant to form an LDD region having a large band gap. The band gap of polycrystalline silicon is 1.1 eV, whereas the band gap of amorphous silicon is 1.5 to 1.8 eV.
It is extremely ideal to use a material having V and such a wide band gap for LDD.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail with reference to the following examples. Example 1 An example using the present invention will be described. This embodiment shows a case where the present invention is applied to an N-channel TFT formed on a quartz glass substrate. This embodiment is shown in FIG. First, as shown in FIG. 3A, a low-temperature oxide film (silicon oxide) 302 having a thickness of 10 to 500 nm, for example, 100 n is formed on a quartz substrate 301 by a low pressure CVD method.
m. Then, similarly, by the low pressure CVD method,
An intrinsic amorphous silicon film having a thickness of 10 to 1
It is formed to a thickness of 00 nm, for example, 20 nm. At this time,
The film may be formed in a microcrystalline or polycrystalline state by increasing the film formation temperature. In addition, in addition to the above-described low-pressure CVD method, a plasma CVD method or an optical CVD method may be used for manufacturing an amorphous silicon film. The amorphous silicon film produced in this manner is reduced to an appropriate size, for example, 10 μm.
The resultant was patterned into a rectangular shape of × 30 μm ² , and crystallization was performed by irradiating the pattern with an excimer laser beam. A KrF laser (wavelength 248 nm, pulse width 10 nsec) is used as the excimer laser, and the energy density of the laser is 150 to 250 mJ / c.
m ² , for example, 200 mJ / cm ² . 1 to 1
Crystallization is achieved by irradiating zero pulses.

Thereafter, a gate insulating film (silicon oxide) having a thickness of 50 to 150 nm, for example, 70 nm, is formed by an ECR plasma CVD method, and an electron beam vacuum deposition method is performed.
An aluminum film having a thickness of 100 to 800 nm, for example, 500 nm is formed, and is patterned to form a portion 303 to be a gate electrode and a gate insulating film 304. The width of the gate electrode was, for example, 500 nm. Then, arsenic ions are implanted, and the impurity concentration becomes 1
× 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ , preferably 1 × 10 ¹⁸
N ^{− of} −2 × 10 ¹⁸ cm ⁻³ , for example, 2 × 10 ¹⁸ cm ⁻³
A type impurity region 305 is formed.

Next, as shown in FIG. 3B, a portion to be a gate electrode is oxidized by anodic oxidation, and an aluminum oxide film 3 having a thickness of 200 nm is formed on the surface of the gate electrode.
06 is formed. As an oxidation method, for example, L-tartaric acid is diluted with ethylene glycol at a concentration of 5%, and the substrate is immersed in a solution whose pH has been adjusted to 7.0 ± 0.2 using ammonia, and the positive electrode of a DC power supply is Is connected to a platinum electrode in which a negative electrode is immersed in a solution, and a voltage is applied at a constant current of 20 mA until the voltage reaches 100 V to perform oxidation. Further, when the voltage reaches 100 V, oxidation is performed with the voltage kept constant until the current reaches 0.1 mA. Thus, an aluminum oxide film is obtained.

At this time, as shown in FIG. 3B, the aluminum oxide film 306 wraps around the gate electrode. In this state again by ion implantation,
Arsenic ions are implanted to form an n ⁺ -type impurity region 307. The impurity concentration is 1 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ ,
For example, it may be 0.8 × 10 ²¹ cm ⁻³ .

Thereafter, as shown in FIG. 3C, laser irradiation is performed from the upper surface of the substrate under the same conditions as the previous laser irradiation. At this time, since the aluminum oxide film 306 is formed on the upper surface of the gate electrode, damage to the gate electrode is reduced. If the aluminum film does not have a sufficient thickness of the oxide film, the laser light will cause the aluminum to expand or melt, causing the gate electrode / wiring to peel, scatter or deform. . If it is covered with a sufficiently thick oxide film, even if the aluminum inside melts momentarily,
There is no problem because it solidifies while keeping its shape.

Further, laser light does not reach below the gate electrode and the oxide layer around the gate electrode. Therefore, the regions 307 and 3 that have been made amorphous by the previous ion implantation
08, the portion below the oxide layer 306 does not crystallize. Thus, a TFT having an impurity region of an amorphous region is formed. The effect was as described above.

Instead of providing an amorphous region, the band gap can also be increased by providing a region in which silicon, for example, carbon, nitrogen, oxygen, or the like is mixed in a stoichiometric or non-stoichiometric ratio. Is possible,
Therefore, although it is known that similar effects can be obtained, elements such as carbon, oxygen, and nitrogen are not preferable materials for a silicon semiconductor, and a reduction in their concentration is required. On the other hand, the method using an amorphous semiconductor such as amorphous silicon described in this embodiment is a clean method that does not use any harmful elements. If the present invention were to be practiced more effectively, carbon, nitrogen,
It is desired that each concentration of oxygen be 7 × 10 ¹⁹ cm ⁻³ or less.

After the crystallization in this manner, passivation was performed at 250 ° C. for 2 hours in a hydrogen gas at 1 atm in order to improve the semiconductor characteristics of the crystallized portion and the amorphous portion. This is because TFTs cannot be operated sufficiently because there are many localized levels in the semiconductor in the channel region and the amorphous region as they are.

After that, a phosphorus glass layer 309 is formed as an interlayer insulator in the same manner as in the case of manufacturing a conventional integrated circuit. For forming the phosphorus glass layer, for example, a low pressure CVD method may be used. As a material gas, monosilane SiH ₄
Using oxygen, oxygen O ₂ and phosphine PH ₃ at 450 ° C.

Thereafter, a hole for forming an electrode is formed in the interlayer insulating film, and an aluminum electrode 310 is formed. Thus, FIG.
An N-channel TFT device as shown in (D) is completed. According to the present invention, the gate electrode and the wiring are covered with an anodized oxide layer. For example, in the case of a matrix circuit for a liquid crystal display, the gate wiring has to cross three-dimensionally with many signal lines. In this case, the gate wiring and the signal line are insulated by an interlayer insulating layer.However, due to the inhomogeneity of the insulating layer and low withstand voltage, the gate wiring may be short-circuited with the signal line. Well.

In the present invention, in addition to a film having a problem in insulating properties such as PSG, the gate wiring has an extremely large withstand voltage.
Such a short circuit is extremely unlikely to occur because it is covered with a dense (no pinholes or the like) oxide layer. As a result, short-circuiting of cross wiring, which was the biggest problem in improving the yield of the liquid crystal matrix, did not need to be a problem at all,
Yield can be significantly improved.

FIG. 4A shows the characteristics of the TFT obtained by this embodiment. The size of the TFT channel region is 0.5 μm × 20 μm, and the width of the amorphous region 308 is 0.1 μm.
μm. In the measurement, the voltage between the source and the drain was 5 V. Similarly, FIG. 4B shows a TFT having a normal structure in which the size of the channel region is 0.5 μm.
× 20 μm. As is apparent from the figure, by implementing the present invention, the reverse leakage was eliminated and the off current (drain current when the gate voltage was 0 V) was significantly reduced. Especially TFT with small off current
Is important when used for controlling pixels in an active matrix type liquid crystal panel. This is because when the off-state current of the TFT used for such a purpose is large, charges leak from the capacitor. In this embodiment, an N-channel TFT has been described. However, a P-channel TFT can be similarly manufactured.

Embodiment 2 FIGS. 5 to 7 show this embodiment. First, as a substrate 501, Corning 7059
Glass was used. Then, an amorphous silicon film was formed to a thickness of 150 nm by a plasma CVD method. This is annealed at 600 ° C. for 60 hours in a nitrogen atmosphere,
Recrystallized. Further, this was patterned to form island-shaped semiconductor regions 502 and 503. Here, the semiconductor region 502 is a region to be a P-channel TFT later, and the semiconductor region 503 is a region to be an N-channel TFT.

Further, a gate oxide film 504 is formed by a sputtering method in an oxygen atmosphere targeting silicon oxide.
Is deposited by a thickness of 115 nm, and then an aluminum film is formed by electron beam evaporation, and is patterned to form a gate electrode 506 of a P-channel TFT, a gate electrode 507 of an N-channel TFT, and wirings 505 and 508.
Was formed. Thus, the outer shape of the TFT was adjusted.
At this time, the size of the channel is 8 μm in length and 8 μm in width.
μm. Further, all the gate electrodes and wirings are electrically connected. FIG. 5A shows the state of the TFT obtained in the steps up to here.

Next, as shown in FIG.
Boron fluoride (BF ₃ ⁺ ) or boron ion (B ⁺ ) is ion-implanted with the photoresist 509 applied to the FT region 503, and a P-type impurity region 510 is self-aligned into the left TFT region 502. Form. The ion energy was 70 to 100 keV, and the dose was 1 to 5 × 10 ¹³ cm ⁻² .

This impurity region forming step may be performed by another known technique, for example, plasma doping (a method of doping by blowing a plasma of a gas containing a dopant onto a target). Both in the case of ion implantation and in the case of plasma doping, the impurity region thus formed is substantially in an amorphous state due to ion bombardment or plasma bombardment. is there.

Similarly, an N-type impurity (for example, phosphorus) is introduced with the photoresist 511 applied to the left TFT region 502 to form an N-type impurity region 512.

Further, gate electrodes and wirings 505 to 508
Then, aluminum oxide films 513 to 516 were formed around the gate electrodes and wirings 505 to 508 (upper surface and side surfaces) by anodizing. Anodization was performed under the following conditions. An example of a top view of the substrate at this time is shown in FIG. That is, all the metal wirings (for example, the gate wirings 506 and 507) are connected to the same wiring 550.

As a solution, a 3% solution of tartaric acid in ethylene glycol was neutralized with 5% ammonia to adjust the pH to 7.0.
The test was performed using a solution having a concentration of ± 0.2. Platinum is immersed in the solution as a cathode, and the substrate is further immersed.
0 was connected to the anode of the power supply. The temperature was kept at 25 ± 2 ° C.

In this state, a current of 0.5 mA / cm ^{2 was} first passed, and when the voltage reached 250 V, current was supplied while the voltage was kept constant. When the current reached 0.005 mA / cm ² , Was stopped, and the anodic oxidation was terminated. The thickness of the anodic oxide film thus obtained was 320 nm. As described above, oxides 513 to 516 as shown in FIG. 5D were formed around the gate electrode and the wiring.

Then, laser annealing was performed.
Laser annealing fixes the sample to the XY stage,
Irradiation was performed while moving a laser beam having a size of 1 × 300 mm ^{2 in} the atmosphere (at least 10 ² torr). As a laser, a KrF excimer laser was used, and a laser pulse having a power density of, for example, 350 mJ / cm ² was irradiated for 50 shots. By such laser annealing, since the laser light does not reach the impurity regions located below the oxides 514 and 516, crystallization does not occur and an amorphous region is formed. The width is only the increase b of the width of the gate electrode portion (gate electrode and its surrounding oxide) due to anodic oxidation. Fig. 5
It is shown in (D). Thus, P-type crystalline impurity region 517 and P-type amorphous impurity region 518 adjacent thereto are formed.
However, an N-type crystalline impurity region 519 and an N-type amorphous impurity region 520 are formed adjacent thereto. Also,
Since the surface of the gate electrode recedes due to anodic oxidation,
As shown in the drawing, a portion (offset region) where the gate electrode and the impurity region do not overlap by the width a is formed. The magnitude of the receding of the gate electrode is 1/3 to 1/2 of the thickness of the oxide film formed by anodic oxidation. b is 0.1
Ａ0.2 μm, and a is 0.03 to 0.2 μm
By setting m, good characteristics were obtained.

Necessary portions were crystallized by the above-described laser annealing. At the same time, cracks, holes, and elution of aluminum were observed in a part of the anodic oxide film due to the impact during laser irradiation. Was. Therefore,
Again, oxidize under the first conditions, close the cracks,
The exposed aluminum surface was oxidized. However, at this time, care must be taken in adjusting the current. That is,
Since the area of cracks and exposed aluminum is extremely small, when a current under the exact same conditions as the first condition is applied, the current concentrates on such a narrow part, and the chemical reaction (oxidation reaction) occurs. ) Progresses remarkably, resulting in local extreme heat generation and destruction.

Then, the current was gradually increased while watching the voltage. For example, the set current at the start of oxidation is preferably about 1 to 5% of the initial anodic oxidation. In this oxidation step, the surface of the gate electrode is not oxidized uniformly, so the definition of current density is not appropriate, but if the unit of current density is used for the purpose of comparing with the first condition, the current is not applied. Sometimes, a current of 5 μA / cm ² was passed, and the voltage was increased by 2 V per minute. Then, when the voltage reached 250 V, the energization was stopped. The value of this maximum voltage is determined by the required thickness of the anodic oxide, and according to our knowledge, the thickness is approximately proportional to the maximum voltage. For example, at a maximum voltage of 250 V, the resulting anodic oxide thickness was about 320 nm.

In this way, the defect of the wiring was removed.
Thereafter, the aluminum wiring was etched by laser irradiation in the atmosphere. As the laser, a Q-switch Nd: YAG laser (wavelength: 10
64nm) second harmonic (wavelength 532nm),
The spot diameter was 5 μm. The pulse width of the laser light was 5 nsec. The energy density is 1 kJ
/ Cm ² . The sample is fixed on an XY stage and irradiated with a beam, for example, as shown in FIG.
The portion indicated by 52 was etched.

This etching process may be performed by a known photolithography process. Which method to choose is a matter of cost and mass productivity. In general, the photolithography method is suitable for a case where there are many portions to be etched, a case where the shape of the etching is complicated, and a case where the area of the portion to be etched is large. But,
There are few places to be etched and the area is small,
If the shape is simple, etching with a laser may be more cost effective. Etching with a simple pattern as shown in FIG. 6 (B), and when not so high accuracy is required, etching with laser is superior.

Further, the sample was carried into a chamber of a CVD film forming apparatus, and a silicon oxide film was deposited thereon, and this was used as an interlayer insulating film (for example, 521 in FIG. 5E). Then, an electrode forming hole (553 in FIG. 6C) was formed. At this time,
In the etching, it is desired to selectively remove only the silicon oxide which is an interlayer insulator and the aluminum oxide covering the gate electrode / wiring. Therefore, the etching rate for silicon oxide and aluminum oxide is higher for aluminum and aluminum oxide. It is required to be larger than for silicon. According to the findings of the present inventors, a suitable etching ratio was obtained with so-called buffered hydrofluoric acid (a solution in which hydrogen fluoride and ammonium fluoride were mixed). For example, in a solution in which high-purity hydrofluoric acid for semiconductor production (50 wt%) and the same ammonium fluoride solution (40 wt%) are mixed at a ratio of 1:10, the etching rate of aluminum oxide is 60 nm / min. Whereas aluminum is 1
It was 5 nm / min. In reactive ion etching using carbon tetrafluoride, silicon oxide is etched, but aluminum oxide and aluminum are hardly etched. By utilizing this characteristic, it is also possible to adopt a method in which only silicon oxide near the contact of the wiring is etched by reactive etching, and thereafter, only aluminum oxide around the wiring is etched by buffer hydrofluoric acid. At this time, the conditions of the reactive ion etching were a gas flow rate of 20 sccm and a pressure of 0.08 t.
orr, RF power was 100 W. The etching rate of silicon oxide was 10 nm / min. In this way,
The electrode was drilled. The mask was a photoresist.

Thereafter, the metal wirings 522 to 524 are connected as shown in FIG.
(E) or as shown in FIG. 6 (C).
FIG. 7 is a circuit diagram of the top view shown in FIG. Initially, the gate electrode of the P-channel TFT was connected to the wiring 507, but was later cut off,
It was connected to the source (or drain) of the N-channel TFT. The source (or drain) of the P-channel TFT was finally connected to the wiring 507.

[Embodiment 3] FIG. 8 is a sectional view of this embodiment. First, Corning 7059 glass was used as the substrate 801. Then, a silicon oxide film 802 as a base was formed with a thickness of 100 nm by a sputtering method. Further, the amorphous silicon film 803 is plasma-CV
Only 50 nm was formed by the D method. On top of that, a silicon oxide film 804 was formed to a thickness of 20 nm also by sputtering for the purpose of protecting the amorphous silicon film. This was annealed at 600 ° C. for 72 hours in a nitrogen atmosphere and recrystallized. Further, this was patterned by photolithography and reactive ion etching (RIE) to form an island-shaped semiconductor region as shown in FIG. After forming the island-shaped semiconductor region, the protective silicon oxide film 8 is formed.
04 was removed. The buffer hydrofluoric acid used in Example 2 was used for the removal.

Further, a gate oxide film 805 is formed by a sputtering method in an oxygen atmosphere targeting silicon oxide.
Was deposited to a thickness of 115 nm. In this state, phosphorus ions were doped into the gate oxide film 805 by a plasma doping method. This is to getter mobile ions such as sodium existing in the gate oxide film and need not be performed when the concentration of sodium is low enough not to hinder the operation of the device. In this example, the plasma acceleration voltage was 10 keV and the dose was 2 × 10 ¹⁴ cm ⁻² . Then, annealing was performed at 600 ° C. for 24 hours, and an oxide film generated by the impact of plasma doping,
The damage of the silicon film was recovered.

Next, an aluminum film was formed by a sputtering method, and this was patterned with a mixed acid (a phosphoric acid solution to which 5% nitric acid was added) to form a gate electrode / wiring 806. The etching rate was 225 nm / min when the etching temperature was 40 ° C.
Thus, the outer shape of the TFT was adjusted. At this time, the channel had a length of 8 μm and a width of 20 μm.

Next, an N-type impurity region (source, drain) 807 was formed in the semiconductor region by ion implantation. Phosphorus ions are used as the dopant, the ion energy is 80 keV, and the dose is 5 × 10 ¹⁵ cm ^−2.
And As shown in the figure, the doping was performed by a through-implant in which an impurity was implanted through the oxide film. The advantages of using such a through implant are:
This means that the surface of the impurity region is kept smooth during recrystallization by laser annealing. If the substrate is not through-implanted, a large number of crystal nuclei are generated on the surface of the impurity region during recrystallization, and irregularities are generated on the surface.
Thus, a structure as shown in FIG. 8B was obtained. Naturally, the crystallinity of the portion into which the impurities are implanted is remarkably degraded by such ion implantation, and is substantially in an amorphous state (amorphous state or a polycrystalline state close thereto).

Further, electricity was passed through the wiring 806, and an aluminum oxide film 808 was formed around the gate electrode and wiring (upper surface and side surfaces) by anodic oxidation. Anodization is performed by adding 3% tartaric acid solution in ethylene glycol to 5%.
This was performed using a solution that was neutralized with ammonia to a pH of 7.0 ± 0.2. First, platinum is immersed in a solution as a cathode, and further, the TFT is immersed in the substrate together with the wiring.
Was connected to the anode of the power supply. The temperature was kept at 25 ± 2 ° C.

In this state, a current of 0.5 mA / cm ^{2 was} first passed, and when the voltage reached 200 V, current was supplied while the voltage was kept constant. When the current reached 0.005 mA / cm ² , Was stopped, and the anodic oxidation was terminated. The thickness of the anodic oxide film thus obtained was about 250 nm. This is shown in FIG.

Thereafter, laser annealing was performed.
As a laser, a KrF excimer laser is used.
A laser pulse with a power density of 50 mJ / cm ²
Shot irradiation was performed. It has been confirmed that the crystallinity of amorphous silicon can be restored to withstand TFT operation by at least one laser irradiation, but the probability of occurrence of defects due to fluctuations in laser power has been sufficiently reduced. For this purpose, a sufficient number of laser irradiations is desirable. However, too many laser irradiations will reduce productivity,
It became clear that about ten times used in this example is most desirable.

The laser annealing was performed under atmospheric pressure in order to enhance mass productivity. Since a silicon oxide film has already been formed on the impurity region, there has been no particular problem. If laser annealing is performed in a state where the impurity region is exposed, oxygen enters the impurity region from the air at the same time as crystallization, and the crystallinity is not good, so that a TFT having sufficient characteristics cannot be obtained. Was. For this reason, it is necessary to perform laser annealing in a vacuum on the substrate where the impurity region is exposed.

Further, in this embodiment, as shown in FIG. 8D, laser light was made to enter obliquely. For example,
In this embodiment, the laser light was irradiated at an angle of 10 ° with respect to the normal to the substrate. The angle is determined according to the design specifications of the element to be manufactured. By doing so, the region crystallized in the impurity region by the laser can be made asymmetric. That is, the area 80 in the figure
9 and 810 are impurity regions that are sufficiently crystallized. The region 811 is not an impurity region, but is a region crystallized by a laser beam. The region 812 is an impurity region but is not crystallized. For example, on the drain side where hot electrons are easily generated, FIG.
The impurity region on the right side of (D) may be used.

Thus, the shape of the element was adjusted. Thereafter, as usual, an interlayer insulator is formed by sputter deposition of silicon oxide, an electrode hole is formed by a known photolithography technique, and the surface of the semiconductor region or the gate electrode / wiring is exposed. Then, a metal film was selectively formed to complete the device.

Example 4 T obtained by the present invention
In the FT, not only the off-state current but also the withstand voltage between the source and the drain and the operation speed change depending on the width of the amorphous semiconductor region or the offset region. Therefore, for example, by optimizing parameters such as the thickness of the anodic oxide film and the ion implantation energy, it is possible to manufacture a TFT suitable for the purpose. However, these parameters are generally not adjustable for individual TFTs formed on a single substrate. For example, in an actual circuit, a low-speed operation may be performed on one substrate, or a high-breakdown-voltage TFT and a low-breakdown-voltage TFT may be used.
It may be desired that T be formed simultaneously. Generally, Japanese Patent Application No. 3-237 of the present invention or a similar invention.
In 100, the larger the width of the offset area,
Although the off-state current is small and the withstand voltage is improved, there is a disadvantage that the operation speed is reduced.

This embodiment shows an example for solving such a problem. This embodiment is shown in FIG. 9 (top view) and FIG. 10 (cross-sectional view). In this embodiment, Japanese Patent Application No. 3-296331 is used.
P-channel TFT and N-channel T, as described in
The present invention relates to the fabrication of a circuit used in an image display method used to drive one pixel (such as a liquid crystal pixel) of an FT. Here, an N-channel TFT is required to have a high speed, and the withstand voltage is a serious problem. On the other hand, the operation speed of the P-channel TFT does not matter so much, but it is required that the off-state current is low, and in some cases, the breakdown voltage is also good.
It is desired that T has a thin anodic oxide film (20 to 100 nm) and P-channel TFT has a thick anodic oxide film (250 to 400 nm). Hereinafter, the manufacturing process will be described.

As in the case of Example 2, Corning 705
9 was used as a substrate 901, an N-type impurity region 902, a P-type impurity region 903, a gate insulating film 904, and gate electrodes / wirings 906 and 907 were formed. Both the gate electrode and the wiring are connected to the wiring 950. (FIG. 9 (A), FIG. 10
(A))

Further, gate electrodes and wirings 906 and 907
Then, aluminum oxide films 913 and 914 were formed around the gate electrodes / wirings 906 and 907 (upper and side surfaces) by anodizing. Anodization was performed under the same conditions as in Example 2. However, the maximum voltage is 5
It was set to 0V. Therefore, the thickness of the anodic oxide film manufactured in this step is about 60 nm. (FIG. 10B)

Next, in FIG. 9B, the gate electrode / wiring 906 was cut off from the wiring 950 by laser etching, as indicated by reference numeral 951. Then, in this state, anodic oxidation was started again. The conditions were the same as before, but at this time the maximum voltage was increased to 250V. As a result, no current flowed through the wiring 906, and no change occurred. However, since current flowed through the wiring 907,
An aluminum oxide film having a thickness of about 300 nm was formed around the gate wiring 907. (FIG. 10 (c))

Thereafter, laser annealing was performed.
The conditions were the same as in Example 2. In this case, the amorphous region of the N-channel TFT (left side in FIG. 10) is so small that it can be neglected. However, if the surface of the aluminum wiring is not covered with the anodic oxide film, it is significantly damaged by laser light irradiation. Therefore, it was necessary to form an anodic oxide film even if it was thin. On the other hand, the P-channel TFT (right side in FIG. 10) has an anodic oxide film thickness of 300 n.
m, and an amorphous region was also present at 150 to 200 nm.
Further, it is estimated that the width of the offset region was also 100 to 150 nm. (FIG. 10 (D))

Then, as in the case of the second embodiment, a necessary portion of the aluminum wiring is etched by laser irradiation in the air, the gate electrode of the P-channel TFT is separated from the wiring 907, and the wiring 950 is cut. did. Further, an interlayer insulating film was formed, a contact hole was formed, and wirings 924 and 911 were formed. In this way,
A circuit has been formed.

In the circuit fabricated in this manner, the N-channel TFT has a small width of the offset region and the non-crystalline region and a slightly large off-state current, but is excellent in high-speed operation. On the other hand, the P-channel TFT has difficulty in high-speed operation, but has a small off-current and has an excellent ability to hold the electric charge accumulated in the pixel capacitor.

As described above, T with different functions is provided on one substrate.
There are other cases where the FT must be integrated. For example, in a liquid crystal display driver, a high-speed TFT is used for a logic circuit such as a shift register, and a high-voltage TFT is used for an output circuit.
FT is required. T corresponding to such conflicting objectives
The method described in this embodiment is effective for manufacturing an FT.

[0076]

According to the present invention, L with very few restrictions
It has become possible to manufacture a DD type TFT. As described in the text, when the present invention is used, an LDD region can be formed with almost no limitation on the aspect ratio of the gate electrode. The width of the LDD region is also 10 to 100.
It can be controlled very precisely between nm. In particular, the present invention is an effective method for increasing the aspect ratio of the gate electrode, which is expected to progress in the future by shortening the channel.

Of course, the present invention can be applied to a conventional low-aspect-ratio gate electrode having an aspect ratio of 1 or less. The effect of the present invention is remarkable because an isotropic etching step is not required and the width of the LDD region can be precisely controlled.

Although the present invention has been described mainly with respect to a silicon-based semiconductor device, it is apparent that the present invention can be applied to a semiconductor device using other materials such as germanium, silicon carbide, and gallium arsenide.

[Brief description of the drawings]

FIG. 1 shows a cross-sectional view of a method for manufacturing an LDD according to the present invention.

FIG. 2 shows a cross-sectional view of a conventional LDD manufacturing method.

FIG. 3 shows a method for manufacturing an NMOS on an insulating substrate using the present invention.

FIG. 4 shows characteristics of a TFT manufactured in this example.

FIG. 5 is a sectional view showing an example of a manufacturing process of a TFT according to the present invention.

FIG. 6 shows a top view of an example of a manufacturing process of a TFT according to the present invention.

FIG. 7 is a circuit diagram showing an example of a manufacturing process of a TFT according to the present invention.

FIG. 8 is a sectional view showing an example of a manufacturing process of a TFT according to the present invention.

FIG. 9 shows a top view of an example of a manufacturing process of a TFT according to the present invention.

FIG. 10 is a sectional view showing an example of a manufacturing process of a TFT according to the present invention.

[Explanation of symbols]

Reference Signs List 101 part to be a gate electrode 102 gate insulating film 103 n ^- impurity region 104 oxide layer 105 gate electrode 106 n ⁺ impurity region 107 LDD region

Claims (25)

[Claims] 1. A semiconductor device comprising: a pair of impurity regions having a first conductivity type; and a channel semiconductor layer having a second conductivity type formed between the pair of impurity regions, formed on an insulating surface of a substrate. A gate insulating layer in contact with the channel semiconductor layer, a gate electrode made of an anodizable material, and adjacent to the channel semiconductor layer via the gate insulating layer, and a side surface of the gate electrode and An anodic oxide layer formed on an upper surface, and at least one of the impurity regions is a first region close to the channel semiconductor layer and a second region distant from the channel semiconductor layer; The insulated gate field effect semiconductor device, wherein the first region contains a dopant that imparts the first conductivity type to the region at a lower concentration than the second region. 2. The insulated gate field effect semiconductor device according to claim 1, wherein a pixel electrode is connected to one of the pair of impurity regions. 3. The insulated gate field effect semiconductor device according to claim 1, wherein said semiconductor device is a p-channel transistor. 4. The insulated gate field effect semiconductor device according to claim 1, wherein said impurity region is a drain region. 5. The insulated gate field effect according to claim 1, wherein a boundary between the first region and the channel semiconductor layer is located outside from a side end of the gate electrode. Semiconductor device. 6. A semiconductor layer formed on an insulating surface including a pair of impurity regions having a first conductivity type and a channel semiconductor layer having a second conductivity type formed between the pair of regions. A gate insulating layer formed on the channel semiconductor layer, a gate electrode made of an anodizable material, and disposed on the channel semiconductor layer via the gate insulating layer, and a side surface of the gate electrode. And an anodic oxide layer formed on the upper surface, wherein at least one of the impurity regions is a first region close to the channel semiconductor layer and a second region remote from the channel semiconductor layer; The insulated gate field effect semiconductor device, wherein the first region contains a dopant that imparts the first conductivity type to the region at a lower concentration than the second region. 7. The insulated gate field effect semiconductor device according to claim 6, wherein a pixel electrode is connected to one of the pair of impurity regions. 8. The insulated gate field effect semiconductor device according to claim 6, wherein the semiconductor device is a p-channel transistor. 9. The insulated gate field effect semiconductor device according to claim 6, wherein said impurity region is a drain region. 10. The insulated gate field effect according to claim 6, wherein a boundary between the first region and the channel semiconductor layer is located outward from a side end of the gate electrode. Semiconductor device. 11. A semiconductor layer formed on an insulating surface including a pair of impurity regions having a first conductivity type and a channel semiconductor layer having a second conductivity type formed between the pair of regions. A gate insulating layer formed on the channel semiconductor layer, a gate electrode made of an anodizable material, and disposed on the channel semiconductor layer via the gate insulating layer, and a side surface of the gate electrode. And an anodic oxide layer formed on the upper surface. At least one of the impurity regions includes a first region close to the channel semiconductor layer and a second region remote from the channel semiconductor layer, The first region includes a dopant that imparts the first conductivity type to the region at a lower concentration than the second region, and a boundary between the first region and the second region includes: The channel From the boundary between the semiconductor layer and the first region from 0.03 to
An insulated gate field effect semiconductor device, which is located 0.2 μm outside. 12. The semiconductor device according to claim 11, wherein a boundary between the channel semiconductor layer and the first region is located 0.1 to 0.2 μm outside a side end of the gate electrode. Gate type field effect semiconductor device. 13. The insulated gate field effect semiconductor device according to claim 11, wherein a pixel electrode is connected to one of the pair of impurity regions. 14. The insulated gate field effect semiconductor device according to claim 11, wherein the semiconductor device is a p-channel transistor. 15. The insulated gate field effect semiconductor device according to claim 11, wherein the impurity region is a drain region. 16. The insulated gate field effect according to claim 11, wherein a boundary between the first region and the channel semiconductor layer is located outside a side end of the gate electrode. Semiconductor device. 17. The insulated gate field effect semiconductor device according to claim 1, wherein the semiconductor device is an n-channel transistor. 18. The insulated gate field effect semiconductor device according to claim 6, wherein the semiconductor device is an n-channel transistor. 19. The insulated gate field effect semiconductor device according to claim 11, wherein the semiconductor device is an n-channel transistor. 20. The method according to claim 1, wherein the first region contains a dopant in an amount of 1 × 10 ^{17 to} 5 × 10 ¹⁸ a.
An insulated gate field effect semiconductor device characterized by containing toms / cm ³ . 21. The method according to claim 1, wherein the second region has a dopant concentration of 1 × 10 ^{20 to} 5 × 10 5.
An insulated gate field effect semiconductor device comprising ²¹ atoms / cm ³ . 22. The method according to claim 6, wherein the first region has a dopant concentration of 1 × 10 ^{17 to} 5 × 10 ^17.
An insulated gate field effect semiconductor device characterized by containing ¹⁸ atoms / cm ³ . 23. The method according to claim 6, wherein the second region has a dopant concentration of 1 × 10 ^{20 to} 5 × 10 5.
An insulated gate field effect semiconductor device comprising ²¹ atoms / cm ³ . 24. The method according to claim 11, wherein the first region has a dopant concentration of 1 × 10 ^{17 to} 5 × 10 ^17.
An insulated gate field effect semiconductor device characterized by containing ¹⁸ atoms / cm ³ . 25. The method of claim 11, wherein the second region is doped with a dopant at a concentration of 1 × 10 ^{20 to} 5 × 10 5.
An insulated gate field effect semiconductor device comprising ²¹ atoms / cm ³ .