JPH0630391B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a read-only memory (mask ROM) for writing information in a manufacturing process.
It relates to a manufacturing method.

[Conventional technology]

A mask ROM in which information is written using a photomask in a manufacturing process is suitable when a large amount of ROMs having the same storage content are used, and is often used as a control storage ROM in a computer or a program memory of a microcomputer. .

A MOS structure transistor (M
Information is written in a mask ROM using OST) as a memory cell by changing the thickness of the gate oxide film of the MOST, presence or absence of a wiring on the source or drain side of the MOST (contact method), or the like.

[Problems to be solved by the invention]

ROM made by the method of changing the thickness of the gate oxide film,
For example, as shown in FIG. 3, a thick gate oxide film 20 and a thin gate oxide film 21 formed on the P-type silicon substrate 1 are formed.
And gate electrodes G ₀ and G ₁ formed on these gate oxide films, and a source S and a drain D made of N-type impurity regions. Then, the MOST due to the difference in threshold voltage (V _T ) between the gate electrodes G ₀ and G ₁
The written information is read by turning on and off.

In the mask ROM configured as described above, the source S and the drain D are commonly used for the gate electrodes G ₀ and G ₁ , so that the degree of integration of the ROM is high. However, since the information is written in the step of forming the gate oxide films 20 and 21, many steps are required for writing the information until the ROM is completed, so that there is a drawback that it takes a long time to complete the product.

On the other hand, the ROM by the contact method uses the master slice method. That is, for an insulating film deposited on a silicon substrate on which a large number of MOSTs are aligned,
The ROM is completed only by selectively forming a contact hole for the source S or the drain D using a mask based on the information content, and then performing a wiring formation passivation film formation and a bonding pad formation process. Therefore, although there is an advantage that the period from the writing of information to the completion of the product is short, as shown in FIG. 4, the source (S _D ) in which the information is written is commonly used for the gate electrodes G ₀ and G _1. However, there is a problem in that the isolation region W must be provided between the memory cells, which is insufficient for improving the degree of integration.

[Object of the Invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a semiconductor memory device, which eliminates the above-mentioned drawbacks, has a short process from the process of writing information to the completion of a product, and has a high degree of integration.

[Means for solving problems]

A semiconductor memory device according to the present invention includes a source region, an opposite conductivity type impurity region, and a drain region, which are separated from each other on a one conductivity type silicon substrate, and a gate oxide film between the source region, the opposite conductivity type impurity region, and the drain region. And a floating gate and a control gate, which are electrically separated and formed in parallel, and an insulating film having positive ions or negative ions formed on the floating gate.

According to the method of manufacturing a semiconductor memory device of the present invention, a gate oxide film is formed on a silicon substrate of one conductivity type, and then electrically isolated floating gates and control gates are formed in parallel on the gate oxide film. A step of forming a source region, an opposite conductivity type impurity region, and a drain region on the silicon substrate by ion-implanting impurities of opposite conductivity type using the floating gate and the control gate as a mask, and after forming an insulating film on the entire surface. A step of forming a contact hole on the source region or the drain region; a step of avoiding the floating gate and forming an A wiring connected to the source region or the drain region through the contact hole; and a photoresist film on the entire surface. A step of forming an opening in the photoresist film on the floating gate selected according to write information after formation, Configured to include a step of injecting positive ions or negative ions in the insulating film on the serial floating gate.

〔Example〕

 Next, an embodiment of the present invention will be described with reference to the drawings.

1 (a) and 1 (b) are a top view and an AA 'sectional view of an embodiment of a semiconductor memory device of the present invention.

In FIGS. 1A and 1B, a source region S, an N-type impurity region 2 and a drain region D are separated on a P-type silicon substrate 1, and the source S and the N-type impurity region 2 are separated from each other. A floating gate G _F is electrically isolated on the gate oxide film 3, and a control gate G _C (word line) is electrically isolated on the gate oxide film 3 between the drain D and the N-type impurity region 2 and formed in parallel. Has been done. Then, the insulating film 4 on the floating gate G _F
Positive ions 5 are selectively introduced into the insulating film 4 on the basis of write information, and a bit line A is formed on the insulating film 4.
The wiring 6 is formed so as to be connected to the source S and avoid the floating gate G _F. Although 7 is a passivation film, it is omitted together with the insulating film 4 in FIG. 1 (a).

In the mask ROM configured as described above, the floating gate G _F1 in which the positive ions 5 are introduced into the upper insulating film 4 is polarized by the charge of the positive ions 5 and is negative on the positive ion 5 side.
Positive charge is induced respectively in the silicon substrate 1 side, because the inversion layer 8 is always formed on the surface of the silicon substrate 1 immediately below the floating gate G _F1 by the induced positive charges to the floating gate G _F1, control When the control voltage (V _S ) is applied to the gate G _C , a current flows from the drain D (power source) to the source S, and “1” is read, for example. On the other hand, since the inversion layer 8 is not formed on the surface of the silicon substrate 1 immediately below the floating gate G _F0 in which the positive ions 5 are not introduced into the upper insulating film 4, the drain D is applied even if V _S is applied to the control gate G _C. -No current flows between the sources S, and "0" is read.

The ROM of the above embodiment has a structure in which a floating gate G _F and an N-type impurity region are mainly added to the conventional ROM shown in FIG. 3 in which the thickness of the gate oxide film is changed, and the control gate G _{Since the} source S and the drain D can be commonly used for _C , the degree of integration is high, and since the ROM can be completed by the master slice method, the period from the information writing process to the product completion can be shortened.

Next, the manufacturing method of the present invention will be described.

2 (a) to 2 (d) are process sectional views for explaining one embodiment of the manufacturing method of the present invention.

First, as shown in FIG. 2A, a gate oxide film 3 made of a thin SiO ₂ film is formed in an active region on a P-type silicon substrate 1 by a well-known technique, and then a polysilicon film is formed on the entire surface by a CVD method. A film is deposited and patterned to form a parallel floating gate G _F and control gate G _C (word line).

Next, as shown in FIG. 2 (b), N type impurities such as A _S are ion-implanted by using the floating gate G _F and the control gate G _C as a mask, and a source region S and an N type impurity region 2 are formed on the silicon substrate.
And a drain region D are formed respectively.

Next, as shown in FIG. 2 (c), an insulating film 4 such as a SiO ₂ film or a phosphosilicate glass film (PSG film) is formed on the entire surface by 0.2 to 2
It is formed to a thickness of μm. Then, after forming a contact hole 9 in the insulating film 4 and the gate oxide film 3 on the source region S by a dry etching method or the like, an A film is deposited on the entire surface by a plasma sputtering method or the like and patterned to form a floating gate G _F on the floating gate G _F. A wiring 6 (bit line) connected to the source S through the contact hole 9 is formed by avoiding the above [FIG.
(See (a)]. Avoiding upper floating gate G _F to form A wiring 6 is for the positive ions are implanted into the insulating film 4 on the floating gate G _F in the next step.

To write information in the MOST thus formed, as shown in FIG. 2 (d), a photoresist film (PR film) 10 is formed on the entire surface, and then a mask formed based on the write information. PR film on floating gate G _F using
An opening 11 is provided at 0. Then, using this PR film 10 as a mask, 1 × 10 ¹² to 1 × 1 under the condition of 30 to 150 KeV.
0 ¹³ / positive ions 5 A _s ^+, etc. cm ² is ion-implanted. The inversion layer 8 is formed on the surface of the silicon substrate 1 below the floating gate G _F1 selected by the implantation of the positive ions 5 as in the case where a voltage is applied to G _F1 .

After the PR film 10 is removed, a passivation film 7, bonding pads, etc. are formed on the entire surface to complete a mask ROM [see FIGS. 1 (a) and 1 (b)].

As described above, according to the manufacturing method of the present invention, the ROM can be completed by the master slice method. Therefore, as compared with the conventional method of forming the ROM by changing the thickness of the gate oxide film, from the writing of information to the completion of the product. It is possible to manufacture a ROM having a shorter process and a higher degree of integration than the contact method.

In the above description, the case where the drain D is used as a positive potential power source has been described, but it is also possible to use the drain D as a ground potential. In this case, as shown in FIG.
The symbols (S, D) of the source and drain regions in (b) and FIGS. 2 (a) to (d) are reversed.

Further, in the above two embodiments, the case where the P-type silicon substrate is used and the MOST in which the N-type impurities are introduced to form the source / drain regions is used is described, but the present invention is not limited to this. It can also be applied to a method of manufacturing a semiconductor memory device using a type silicon substrate.

〔The invention's effect〕

As described in detail above, according to the present invention, a process from the writing of information to the completion of a product is short, and a highly integrated semiconductor memory device manufacturing method can be obtained.

[Brief description of drawings]

1 (a) and 1 (b) are a top view and a sectional view of an embodiment of a semiconductor memory device of the present invention, and FIGS. 2 (a) to 2 (d) are drawings of an embodiment of a manufacturing method of the present invention. Process cross-sectional views, FIG. 3 and FIG. 4 are schematic views for explaining a conventional semiconductor memory device. 1 ... Silicon substrate, 2 ... N-type impurity region, 3 ... Gate oxide film, 4 ... Insulating film, 5 ... Positive ion, 6 ... A
Wiring, 7 ... passivation film, 8 ... inversion layer, 9
...... Contact hole, 10 ... Photoresist film, 11 ...
… Opening holes, 20, 21… Gate oxide film, S… Source,
D: drain, G _F: floating gate, G _C: control gate.

Claims (1)

[Claims] 1. A step of forming a gate oxide film on a one conductivity type silicon substrate and then forming a floating gate and a control gate in parallel on the gate oxide film, and a step of using the floating gate and the control gate as a mask. Forming a source region, an opposite conductivity type impurity region, and a drain region on the silicon substrate by introducing a conductivity type impurity; and forming a contact hole on the source region or the drain region after forming an insulating film on the entire surface. And a step of forming a wiring that avoids the floating gate and connects to the source region or the drain region through the contact hole, and then implanting ions into the insulating film on the floating gate. The floating gate is polarized by the charge of the ions in the film, and the opposite conductivity type is applied to the surface of the one conductivity type semiconductor substrate directly below the floating gate. Method of manufacturing a semiconductor memory device characterized by the formation of the layer.