JPH09275152A - Method for manufacturing semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a multilevel semiconductor memory device provided with a MOS type mask ROM by a method wherein a channel region is divided into a plurality of parts in self-aligned manner. SOLUTION: A polysilicon film 3 and a WSi film 4 are formed via a gate insulation film 2 on a silicon substrate 1. Next, by using an anisotropic etching method, the WSi film 4 is etched in a specific shape. Next, a silicon oxide film 5 is formed on the entire face, and by using the anisotropic etching method, a sidewall is formed. Next, by use of the WSi film 4 and the sidewall as a mask, by using the anisotropic etching method, the polysilicon film 3 is etched to form a projected gate electrode. Next, ions are implanted aslant from a specific implantation angle from the perpendicular direction with respect to the gate electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-level output level MOS (Metal-Oxide film-Semi).
on-mask mask ROM (Read-Onl)
The present invention relates to a method of manufacturing a semiconductor memory device having a y-Memory).

[0002]

2. Description of the Related Art Mask ROMs currently commercialized are
Most of them are different in the threshold voltage of the cell transistor to determine whether or not a current flows between the source / drain of the cell transistor with respect to the word line potential, which is 1-bit data of "0" or "1". Is stored in one memory cell.

Conventionally, the mask ROM has been increased in capacity by miniaturizing the minimum processing size and reducing the size of the transistor. However, if three or more threshold voltages are set for one memory cell transistor and the memory capacity is increased by differentiating the current drive capability, high integration is possible without relying only on the transistor size reduction. Becomes

In the conventional multi-valued ROM, a method of setting the channel length of the cell transistor to several types (for example, disclosed in Japanese Patent Laid-Open No. 5-48044) and a number of channel widths are set. Method (for example, Japanese Patent Laid-Open No. 59-1
It is disclosed in Japanese Patent No. 48360 and Japanese Patent Laid-Open No. 61-263263. ), A method of changing the gate oxide film thickness (for example, disclosed in Japanese Patent Laid-Open No. 58-209155), a method of performing core injection a plurality of times, and the like, and setting three or more types of current driving capability of the cell transistor. , Multi-valued ROM
Is realized.

However, in these methods, the time (TAT: Turn A) from the time an user receives an order until the time it is delivered.
There are problems that the round time) becomes long, and that the photo step or the injection step when writing data must be performed a plurality of times.

As a method for improving this problem, core implantation is performed through a gate electrode, a mask material or the like having different film thicknesses or transmissivities to change the ion implantation depth and the implantation amount to be implanted, There is a method of dividing the channel region into a plurality (for example, disclosed in Japanese Patent Laid-Open No. 5-283654).

This method is shown in FIG. FIG. 5A is a plan view of a memory cell transistor in which the channel region is divided into a first channel 67 and a second channel 68, and FIG. 5B shows a BB cross section of FIG. A field insulating film 62 is provided in the element isolation region of the P-type silicon substrate 61, and a gate oxide film 63 is formed on the channel region. The source region 65 and the drain region 66 are formed by diffusing N-type impurities. The source region 65 is connected to the ground potential by the diffusion layer, and the drain region 66 is connected to the bit line through the contact hole. The polysilicon gate 64 also serving as the word line is thick on the first channel 67,
The second channel 68 is thinly formed.

In this method, by selectively implanting ions for writing data into the first channel 67 and the second channel 68, the source / drain of the cell transistors having different current driving capabilities are commonly connected in parallel. Since it is connected to each other, a plurality of types of cell transistors, that is, a multi-valued ROM can be realized by combining the channel width and the presence or absence of core injection. For example, when a photoresist having a predetermined pattern opened for writing data and an ion implantation process are performed once, a four-value multi-value ROM
Can be realized.

That is, when impurities are implanted only in the first channel 67, when impurities are implanted only in the second channel 68, and when impurities are implanted in both the first channel 67 and the second channel 68. , A four-valued level multi-valued ROM can be realized when impurities are not implanted into both the first channel 67 and the second channel 68.

[0010]

However, according to the above method, when the channel region is divided into a plurality of regions, the alignment margin between the gate electrode and the photoresist is strict at the time of processing the gate electrode, and further, the photo-writing for data writing after the processing of the gate electrode. The alignment margin of the resist is strict,
The misalignment of the photoresist directly affects the division of the channel region, changes the characteristics, and makes it impossible to recognize each multi-valued level.

The present invention divides the channel region into a plurality of regions in a self-aligned manner, thereby providing a multi-level MOS mask RO.
It is an object of the present invention to provide a method of manufacturing a semiconductor memory device including M.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor memory device manufacturing method including a MOS type mask ROM having memory cells including a plurality of transistors having different current driving capabilities. In the manufacturing method of, a step of forming a convex gate electrode on the semiconductor substrate through a gate insulating film or a gate electrode made of a material having different permeability of implanted ions at both side portions and a central portion, A step of forming a photoresist in which a predetermined pattern is opened according to writing, and oblique ion implantation from a direction perpendicular to the gate electrode at a predetermined implantation angle,
And a step of writing data.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device in which a MOS type mask RO having memory cells including a plurality of transistors having different current driving capabilities.
In the method for manufacturing a semiconductor memory device including M, a conductive film and a thin film having an etching rate at the time of etching the conductive film lower than that of the conductive film are formed on a semiconductor substrate through a gate insulating film, and the thin film is formed. A step of forming a photoresist having a predetermined pattern on the top surface, a step of etching the thin film by using the photoresist as a mask by an anisotropic etching method to expose the surface of the conductive film, and an oxide film over the entire surface. Forming and forming a sidewall on the side wall of the thin film by using an anisotropic etching method, and removing the conductive layer by an anisotropic etching method using the thin film and the sidewall as a mask to form a convex shape. And a step of performing oblique ion implantation from the direction perpendicular to the first gate electrode at a predetermined implantation angle. .

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device in which a MOS type mask RO having memory cells including a plurality of transistors having different current driving capabilities.
In a method of manufacturing a semiconductor memory device including M, a first conductive film is formed on a first conductive type semiconductor substrate via a gate insulating film, and a photoresist having a predetermined pattern is formed on the first conductive film. A step of forming, a step of etching the first conductive film by using an anisotropic etching method using the photoresist as a mask to expose the surface of the gate insulating film, and a step of transmitting the first conductive film and implanted ions. A second conductive film having a different property is deposited on the entire surface, and a sidewall made of the second conductive film is formed on the side wall of the first conductive film by using an anisotropic etching method. A step of forming a second gate electrode made of a material having different transmissivity, and a step of performing oblique ion implantation from the direction perpendicular to the second gate electrode at a predetermined implantation angle. is there.

Further, in the method of manufacturing a semiconductor memory device according to the present invention, a MOS type mask RO having memory cells including a plurality of transistors having different current driving capabilities.
In a method of manufacturing a semiconductor memory device including M, a third conductive film is provided on a first conductivity type semiconductor substrate via a gate insulating film,
Alternatively, a step of forming a two-layer film including a fourth conductive film and a fifth conductive film and forming a photoresist having a predetermined pattern on the third conductive film or the fourth conductive film; and using the photoresist as a mask. Using the isotropic etching method, the third
After etching the conductive film to a predetermined depth or etching the fourth conductive film to expose the surface of the fifth conductive film,
A step of etching the third conductive film or the fifth conductive film to form a convex third gate electrode, and a step of performing oblique ion implantation on the third gate electrode from a vertical direction at a predetermined implantation angle. It is characterized by having.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIG. 1 is a manufacturing process diagram of a semiconductor memory device according to a first embodiment of the present invention, and FIG. 2A is a plan view of the semiconductor memory device formed by the process of FIG. b)
2A is a diagram showing a cross section taken along the line AA in FIG. 2A, and FIG.
FIG. 4B is an enlarged cross-sectional view of the fourth transistor, FIG. 3 is a manufacturing process diagram of the semiconductor memory device of the second embodiment of the present invention, and FIG. 4 is a semiconductor memory of the third embodiment of the present invention. It is a manufacturing process figure of a device.

The manufacturing process of the semiconductor memory device according to the first embodiment of the present invention will be described below with reference to FIG.

First, a gate oxide film 2 having a thickness of about 170 Å is formed on a silicon substrate 1 on which a source region and a drain region (not shown) are formed, and a polysilicon film 3 having a thickness of about 1500 Å. Then, a tungsten silicide (WSi) film 4 is formed thereon with a thickness of about 1500Å,
A photoresist 5 having a predetermined pattern is formed thereon (FIG. 1 (a)). Next, anisotropic etching is used with the photoresist 5 as a mask to remove silicon tungsten (WS).
i) Etch the film 4.

Instead of the above steps, the polysilicon film 3 is used.
Is formed to a thickness of about 3000Å, and then a film having an etching rate lower than that of the polysilicon film 3 that acts as an etching stopper during etching of the polysilicon film 3 and the polysilicon, for example, a silicon oxide film formed by the CVD method is formed. After forming about 1000Å, the polysilicon film 3 may be etched by about 1500Å using an anisotropic etching method using the photoresist 5 having a predetermined pattern. still,
The process using the WSi film 4 has better controllability because the selection ratio during etching can be increased. In addition, the process using the WSi film 4 can lower the gate wiring resistance.

Next, after removing the photoresist, an oxide film 6 for forming sidewalls is formed with a thickness of about 2000 Å (FIG. 1B).

Next, the oxide film 6 for forming the side wall is processed into a side wall shape by using anisotropic etching. Since the side wall width can be controlled by the film thickness of the oxide film 6 for forming the side wall, the division width of the channel region can be controlled, and the space size between the gate electrodes can be set to the resolution limit of the photoresist pattern or less. This is possible, and the cell size can be reduced as compared with the case where a separate photo-etching process is performed (FIG. 1C).

Next, using the WSi film 4 and the sidewall 6 as a mask, the polysilicon film 3 is formed by anisotropic etching.
After etching 1500 Å to form the gate electrode,
Oxide film 7 as an injection protection film by removing the side wall
Is formed to a thickness of about 200Å (Fig. 1 (d)).

Next, a photoresist 8 having an opening of a predetermined pattern is formed according to the writing of data, and an oblique implantation of boron ions is performed on the surface of the gate electrode through the photoresist 8 for writing data. The ion implantation region 9 is formed by performing an implantation angle of 10 to 30 ° from one vertical direction, an implantation energy of 50 to 100 keV, and a dose amount of 1 × 10 ¹⁴ to 2 × 10 ¹⁴ cm ⁻² (see FIG. )).
Here, by optimizing the implantation energy with respect to the thickness of the gate electrode, the ions that pass through the thin portion of the gate electrode reach the channel, while the ions that pass through the thick portion of the gate electrode reach the channel. do not do. Also,
By optimizing the implantation angle for the channel width,
The channel width can be divided into three (the first channel 55, the second channel 56, and the third channel 57 in FIG. 2C), and the respective output levels can be made different.

For example, the width of the gate electrode is 0.5 μm, the width of the upper surface of the convex portion of the gate electrode is 0.2 μm, and the width of the thin portions on both sides of the convex portion of the gate electrode is 0.15 μm, respectively, and 15 ° Channel widths of about 0.11 μm, about 0.16 μm, and about 0.23 μm, respectively.
m.

Through the above steps, the following multi-value ROM in which the channel region is divided in a self-aligning manner in combination with each photoresist pattern can be realized. That is, as shown in FIG. 2, the first transistor Tr1
With respect to, the impurity ion implantation for writing data is not performed, and the effective channel width (W1) is almost equal to the gate width. Regarding the second transistor Tr2, the impurity ion implantation for writing data is performed in a region of 1/4 of the channel width, and the effective channel width (W
2) is about 3/4 of the gate width. Further, in the third transistor Tr3, the impurity ion implantation for writing data is performed in the region of 1/2 the channel width, and the effective channel width (W3) becomes about 1/2 of the gate width.
Further, regarding the fourth transistor Tr4, the impurity ion implantation for writing data is 3/4 of the channel width.
Region, and the effective channel width (W4) becomes about 1/4 of the gate width. In FIG. 2, 30 is a source region,
Reference numeral 31 indicates a drain region.

Regarding the division of the channel width, FIG.
As shown in (c), the channel width region is divided into three regions, that is, the first channel 55 and the third channel 57 where the implanted ions have reached the channel, and the second channel 56 where the implanted ions have not reached the channel. It is divided.

As described above, the first transistor Tr1,
A memory cell is formed in which the second transistor Tr2, the third transistor Tr3, and the fourth transistor Tr4 have different current driving capacities, and the driving capacities are substantially equal.

Next, the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIG.

First, a gate oxide film 12 is formed to a thickness of about 170Å on a silicon substrate 11 on which a source region and a drain region (not shown) are formed, and a WSi film 13 is formed thereon to a thickness of about 3000Å. And a photoresist 14 having a predetermined pattern is formed thereon (see FIG. 3).
(A)).

Next, using the photoresist 14 as a mask, the WSi film 13 is etched to about 3000 Å by anisotropic etching.
Etching. After removing the photoresist, a polysilicon film 15 for forming a sidewall is formed to a thickness of about 2000 Å (FIG. 3B).

Next, the polysilicon film 15 is processed into a sidewall shape by using anisotropic etching. Since the side wall width can be controlled by the film thickness of the polysilicon film 15 for forming the side wall, the division width of the channel region can be controlled, and the space between the gate electrodes should be equal to or less than the resolution limit of the photoresist pattern. Is possible,
The cell size can be reduced as compared to the case where the cell is formed by a photo etching process. After that, an oxide film 16 as an injection protection film is formed with a thickness of about 200Å (FIG. 3C).

Next, in accordance with the writing of data, a photoresist 17 having a predetermined pattern is formed, and through the photoresist 17, oblique implantation of boron ions for writing data is performed perpendicularly to the gate electrode surface. The implantation angle is 10 to 20 ° from one direction, the implantation energy is 110 to 130 keV, the dose is 1 × 10 ¹⁴ to 2 × 10 ¹⁴ cm ⁻² , and the ion implantation region 18 is formed (FIG. 3).
(D)). Here, by optimizing the implantation energy with respect to the thickness of the gate electrode, the ions that pass through the thin portion of the gate electrode reach the channel, while the ions that pass through the thick portion of the gate electrode reach the channel. do not do. Further, by optimizing the implantation angle with respect to the channel width, the channel width can be divided into three and each output level can be made different.

Through the above steps, the channel region is divided in a self-aligning manner in combination with each photoresist pattern, and a multi-valued ROM can be realized.

Next, a manufacturing process of the semiconductor memory device according to the third embodiment of the present invention will be described with reference to FIG.

First, a gate oxide film 20 having a thickness of about 170 Å is formed on a silicon substrate 19 having a source region and a drain region (not shown) formed thereon, and a polysilicon film 21 having a thickness of about 1500 Å is formed thereon. Formed with thickness and W on it
A Si film 22 is formed with a thickness of about 1500Å, and a photoresist 23 having a predetermined pattern is formed thereon (FIG. 4).
(A)).

Next, the WSi film 22 is etched by about 1500 Å using isotropic etching with the photoresist 23 as a mask (FIG. 4B). Next, photoresist 2
Using polysilicon 3 as a mask, the polysilicon film 21 is etched by about 1500 Å to form a convex gate electrode. However, regarding the formation of the convex-shaped gate electrode, one layer of polysilicon film is formed to a thickness of about 3000 Å, isotropic etching is performed to a thickness of about 1500 Å, and then the remaining is left by anisotropic etching. The polysilicon film of about 1500 Å may be etched. After that, an oxide film 24 as an injection protection film is formed with a thickness of about 200Å (FIG. 4C).

Next, a photoresist 25 having an opening of a predetermined pattern is formed according to the writing of data, and an oblique implantation of boron ions for writing data is performed through the photoresist 25 perpendicularly to the surface of the gate electrode. The ion implantation region 26 is formed by performing an implantation angle of 10 to 30 ° from one direction, an implantation energy of 80 to 130 keV, and a dose amount of 1 × 10 ¹⁴ to 2 × 10 ¹⁴ cm ⁻² (FIG. 4).
(D)). Here, by optimizing the implantation energy with respect to the thickness of the gate electrode, the ions that pass through the thin portion of the gate electrode reach the channel, while the ions that pass through the thick portion of the gate electrode reach the channel. do not do. Further, by optimizing the implantation angle with respect to the channel width, the channel width can be divided into three and each output level can be made different.

Through the above steps, the channel region is divided in a self-aligning manner in combination with each photoresist pattern, and a multi-valued ROM can be realized.

In the above-mentioned first to third embodiments,
A photoresist for data writing and ion implantation are each performed once, and a 4-level multi-value ROM
However, this step is not limited to once, but the same mask is used and the implantation angle is appropriately selected.
By performing the oblique ion implantation a plurality of times, it is possible to realize a multi-valued ROM having four or more levels or a multi-valued ROM having a wide margin between respective characteristic levels.

[0041]

As described above in detail, the following effects can be obtained by using the present invention.

First, a self-aligned convex gate electrode is formed by forming a photoresist having a predetermined pattern and performing oblique ion implantation one or more times for writing data. The channel region can be divided into a plurality of regions. Further, regarding alignment of the photoresist for writing data, even if the photoresist is slightly shifted from the center of the gate electrode, the channel region is divided by ion implantation through the convex portion of the gate electrode itself. A large alignment margin can be secured.

Therefore, the channel region of the cell transistor is divided in a self-aligned manner, and as a result, the cell transistor has a plurality of types of transistors having different current driving capabilities, the sources / drains of which are connected in parallel. Since it has a shape, it is possible to realize a MOS mask ROM of a multi-value level system with little characteristic variation, and it is possible to achieve high integration or large capacity without increasing the size of the cell area.

Further, the combination of the ion implantations performed on the first channel region, the second channel region and the third channel region makes it possible to easily and reliably develop a MOS having a four-value output level.
Type mask ROM can be realized, and the area of the memory cell can be reduced to about 50% as compared with the currently used binary memory cell with the same storage capacity. Even in the area including circuits other than the cell part, it is 50 to 70 as compared with the binary mask ROM.
It can be reduced to about%. As a logic circuit, the binary method is more efficient in terms of circuit, and four values are most suitable in consideration of the circuit (characteristic) margin when identifying multi-valued levels.

Further, by processing the gate electrode using the side wall, the convex gate electrode can be processed in a self-aligning manner with good controllability, and the space between the gate electrodes should be set to a size below the processing limit. You can

Further, by forming the gate electrode in a two-layer structure made of different materials, it is possible to obtain an etching selection ratio when forming the gate electrode in a convex shape. Also, by using a material having a lower resistance as the material of the gate electrode. The wiring resistance of the gate electrode can be reduced.

Furthermore, by processing the gate electrode by utilizing isotropic etching, the manufacturing process can be simplified, and the gate electrode can be processed within the resolution limit of photolithography. The increase in transistor size can be suppressed.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor memory device according to a first embodiment of the present invention.

2A is a plan view of a semiconductor device according to an embodiment of the present invention, FIG. 2B is a sectional view taken along line AA of FIG. 2A, and FIG. It is an expanded sectional view of a 4th transistor.

FIG. 3 is a manufacturing process diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of a semiconductor memory device according to a third embodiment of the present invention.

5A is a plan view of a conventional semiconductor memory device, and FIG. 5B is a sectional view taken along line BB of FIG.

[Explanation of symbols]

 1, 11, 19 Silicon substrate 2, 12, 20 Gate insulating film 3, 15, 21 Polysilicon film 4, 13, 22 WSi film 5, 8, 14, 17, 23, 25 Photoresist 6 Side wall oxidation Films 7, 16 and 24 Oxide film as an implantation protection film 9, 18 and 26 Ion implantation region 30 Source region 31 Drain region 55 First channel 56 Second channel 57 Third channel

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor memory device comprising a MOS mask ROM having memory cells including a plurality of transistors having different current driving capabilities, wherein a convex gate is provided on a semiconductor substrate with a gate insulating film interposed therebetween. An electrode or a step of forming a gate electrode made of a material having different permeability of implanted ions at both side portions and a central portion, and a step of forming a photoresist in which a predetermined pattern is opened according to data writing, And a step of performing oblique ion implantation from a direction perpendicular to the gate electrode at a predetermined implantation angle to write data, the method for manufacturing a semiconductor memory device. 2. A method of manufacturing a semiconductor memory device comprising a MOS type mask ROM having memory cells including a plurality of transistors having different current driving capabilities, wherein a conductive film is formed on a semiconductor substrate via a gate insulating film. A step of forming a thin film having an etching rate lower than that of the conductive film at the time of etching the conductive film and forming a photoresist having a predetermined pattern on the thin film; and an anisotropic etching method using the photoresist as a mask And etching the thin film to expose the surface of the conductive film, forming an oxide film on the entire surface, and forming a sidewall on the side wall of the thin film using an anisotropic etching method; A step of removing the conductive layer using an anisotropic etching method using the sidewall as a mask to form a convex first gate electrode; Characterized by a step of performing oblique ion implantation from a predetermined injection angle from the direction perpendicular to the method of manufacturing a semiconductor memory device. 3. A method for manufacturing a semiconductor memory device comprising a MOS type mask ROM having memory cells including a plurality of transistors having different current driving capabilities, wherein a gate insulating film is provided on a first conductivity type semiconductor substrate. First
A step of forming a conductive film and forming a photoresist having a predetermined pattern on the first conductive film; and using the photoresist as a mask to etch the first conductive film by using an anisotropic etching method, A step of exposing the surface of the gate insulating film, a second conductive film having a different permeability of implanted ions from the first conductive film are deposited on the entire surface, and an anisotropic etching method is used to form a first conductive film on the sidewall of the first conductive film. A step of forming a side wall made of two conductive films and forming a second gate electrode made of a material having different permeability of implanted ions at both sides and a central part; And a step of performing oblique ion implantation from the implantation angle of 1. 4. A method of manufacturing a semiconductor memory device having a MOS mask ROM having memory cells including a plurality of transistors having different current driving capabilities, wherein a gate insulating film is provided on a first conductivity type semiconductor substrate. 3rd
A step of forming a conductive film or a two-layer film including a fourth conductive film and a fifth conductive film, and forming a photoresist having a predetermined pattern on the third conductive film or the fourth conductive film; Is used as a mask to etch the third conductive film to a predetermined depth, or the fourth conductive film is etched to expose the surface of the fifth conductive film, and then the third conductive film is exposed. The method includes a step of etching the conductive film or the fifth conductive film to form a convex third gate electrode, and a step of performing oblique ion implantation on the third gate electrode from a vertical direction at a predetermined implantation angle. A method of manufacturing a semiconductor memory device, comprising: