JPH02307265A - Mask rom and its manufacture - Google Patents

Abstract

PURPOSE: To provide NAND logic type ROM structure wherein high integration is attained by constituting each of memory strings with a bulkhead layer of insulation material separating memory cells, a gate oxide film layer, a gate electrode formed on a side wall of the bulkhead layer and the gate oxide film layer, and specific channel area. CONSTITUTION: Each of many memory strings 14 where many memory cells 20-28 are connected in series compresses a bulkhead layer 16 of insulation material set away by a specified distance between a connection area 16 and a reference area 18 for separating the memory cells 20-28, a gate oxide film layer 42 formed on the surface of a substrate 8 on which the memory cells 20-28 are formed, a gate electrode 44 formed on each of the gate oxide film layers 42 and on the side wall of the bulkhead layer 46 between adjoining memory calls, a channel area 48 having the first conductive type ion below the memory cell 20 adjoining the connection area 16 and a selected memory cell or cell's oxide film layer 42, and a channel area having the second conductive type ion below a not-selected memory cell or cell's oxide film layer 42 and the bulkhead layer 46.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is directed to a mask read-only memory (MaskROM).
In particular, the present invention relates to a serial read-only memory structure having a spacer film and a manufacturing method thereof.

BACKGROUND OF THE INVENTION Mask programmable ROMs are sometimes referred to as mask ROMs. A mask ROM is used in an information processing system to write game contents 1a on a control logic such as a microprogram or a game chip. It is desirable that such control logic be highly integrated and stored in smaller footprint memory devices.

As a ROM structure used to store a relatively large amount of control logic information in a predetermined area, there is a ROM structure having NAND logic connected in series.

This is disclosed in US Pat. No. 4,142,176. This prior art is a ROM structure in which a large number of depletion mode transistors and enhancement mode transistors are connected in series and arranged in a NAND logic matrix. The gates of the transistors in each row are common to one row line, and the sources and drains of adjacent transistors in one string in each column are connected in series in each column.

Therefore, in such a NAND logic type ROM structure, an insulating layer overlying the sources and drains of adjacent transistors in one string is used as an insulator for separating row lines.

<Problem to be solved> However, in a ROM in which a large number of series-connected transistors are arranged in a large number of rows and columns, it is difficult to achieve a higher degree of integration with the ROM structure having an insulating layer over the source and drain. Can not do it.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a NAND ROM structure that solves the problems of the prior art described above.

Another object of the present invention is to provide a method for manufacturing a NAND logic type ROM structure that can achieve a high degree of integration.

<Means for Solving the Problems> In order to achieve the above-mentioned object, a mask ROM according to the present invention has a structure in which each of the connection regions of the second conductivity type on the semiconductor substrate of the first conductivity type and the second conductivity type are connected to each other. In a mask ROM having a large number of memory strings in which a large number of memory cells are connected in series between a type base ($ area), each of the memory strings is connected to the connection area in order to isolate the memory cells. a barrier layer of an insulator separated by a predetermined distance from a reference region; a gate oxide film layer formed on the surface of a substrate on which a memory cell is formed; and a memory cell adjacent to each of the gate oxide film layers. Ions of the first conductivity type are applied to the gate electrode formed on the sidewall of the partition layer between the cells, the memory cell adjacent to the connection region, and the selected memory cell or under the oxide film layer of the cell. and a channel region having ions of the second conductivity type under the oxide film layer of the unselected memory cell or cell and under the above-mentioned barrier layer. Manufacturing method This is a method for manufacturing a mask ROM having a memory string in which a large number of memory cells are connected in series, which consists of the following steps.In other words, the active region where the memory string is formed is of the first conductivity type. a step of forming a thick oxide layer to confine the memory cells on the semiconductor substrate; a step of implanting ions of a second conductivity type into the active region on the substrate; and a barrier layer of insulator to isolate the memory cells. a step of forming a gate oxide film layer of a memory cell on the substrate surface within the active region;
forming a conductive type gate electrode on each surface of the gate oxide film layer and the sidewall of the barrier layer between adjacent memory cells; This process consists of a step of implanting ions of the first conductivity type into the lower part.

<Embodiment> Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a plan view of a portion of a NAND logic type ROM structure according to the present invention, and only two memory strings are shown for convenience of explanation. The memory string 14 is composed of a group of cells 20 to 2B connected in series between each column line 10 and a base region providing a reference voltage (ground).

FIG. 2 is a sectional view taken along the line ``---'' in FIG.

The ROM structure according to the present invention will be explained with reference to FIGS. 1 and 2.

On the surface of the P-type substrate 8, there are column lines 1 made of a conductor such as metal.
0 through the aperture 12, and N''7J?J connected to a reference voltage such as ground voltage.
A field oxide film layer 40 is formed to separate the area 1 and the memory 1 and the ring 14.

Further, cells 20 to 28 connected in series are formed on the surface of the substrate 8 below the column line 10 between the N'' connection region 16 and the N'' reference region 18. -28, cell 20 is a string selection cell, and cells 21-28 are composed of eight ROM cells.R
It will be readily apparent to those skilled in the art that the number of OM cells is not necessarily limited to eight. Each of the cells 20-2 was formed on the substrate surface.

It is composed of a thin gate oxide film layer 42 having a diameter of 0□, and a gate electrode 44 of a conductive type on top of this layer. The gate electrode 44 may be made of N'' F-type polycrystalline silicon. Also, between the cells 20 to 28, SizN4
A barrier layer 46 of an insulating material such as
Eight gate electrodes 44 are formed on both side walls of the partition layer 46 . The channel fJf region 48 under the gate electrode 44 of each cell 21-28 is programmed by N or P type ion implantation. However, P-type ions are implanted into channel region 48 corresponding to cell 20 of the string selection cell. A cell in which P-type ions are implanted into the channel region 48 of the P-type substrate operates in a manner similar to an enhancement moat transistor of a conventional MOSFET, and a cell in which N-type ions are implanted operates in a manner similar to a depletion moat transistor. Operate.

Therefore, programming in the present invention means manufacturing a ROM cell into enhancement mode or depletion mode by ion implantation technology. For example, assuming that the ROM cell 22 is programmed into enhancement mode, application of a positive voltage to the gate electrode 44 of the RO,M cell 22 will cause the channel region 48 of the ROM cell 22 to become conductive, and vice versa. The application should be non-conductive. On the other hand, assuming that ROM cell 22 is programmed as depletion mode, channel region 48 of ROM cell 22 will be conductive despite the grounded state of gate electrode 44.

An insulating layer 50 is formed on the gate electrode 44 , and a column line 10 is formed on the insulating layer 50 and connected to the connection region 16 through the opening 12 . On the other hand, each gate electrode 44 of the cells 20 to 28 is connected to the row lines 30 to 38, which extend in the row direction perpendicularly to the column line IO. The material of the row lines 30 to 38 may be the same material as the gate electrode 44, ie, doped polycrystalline silicon.

FIG. 3 shows an equivalent circuit of one memory string connected between one column line in FIG. 1 and ground.

Now, assuming that ROM cells 21 and 23 are programmed in depletion mode and the remaining ROM cells are programmed in enhancement mode, the ROM
The operation will be explained without reading out the cell 23. To read the logic information stored in ROM cell 23, a voltage of approximately 2 volts is applied to the selected column line 10 and a ground voltage is applied to the selected row line 33. At the same time, power supply voltage Vcc (5 volts) is applied to string selection row line 30 and unselected row lines 31, 32 and 34-38. Then, all cells including the ROM cell 23 become conductive, so i! Translated column line 10 goes to ground, thereby not reading a logic "O'". However, if the ROM cell 23 were programmed into enhancement mode, the selected column line 10 would maintain a voltage of 2 volts since the ROM cell 23 would be non-conductive, thereby causing a logic "1" to be output. .

4(A) to 4(G) are drawings showing the manufacturing process of the cross-sectional view of FIG. 2.

Referring to FIG. 4(A), the P-type substrate 8 is a wafer having an orientation <100> and a resistance of 5 to 50 Ωcm. P-type substrate 8 can also be a P-type well. Approximately 5000 field oxidation) film layers 40
and about 380 P channel stopper layers 52 below the bad oxide layer 51 and the field oxide layer 40.
However, normal LOG OS (Local Oxidat
It is formed on the surface of the substrate 8 to define an active area in which a memory string is formed by an ion of silicon (ion of silicon) process.

Thereafter, arsenic ions are implanted at an energy of about 100 KeVO and a dose of about 2.0 x 10'' ons/cffl to convert the channel region 48 into depletion.

Thereafter, as shown in FIG. 4B, a first silicon nitride layer 54 of approximately 500 layers is formed on the band oxide layer 51 and field oxide layer 40, and a silicon oxide layer 54 of approximately 7000 layers is formed on the band oxide layer 51 and field oxide layer 40. is a normal CV on the first silicon nitride film layer 54.
D (Chemical Vapor Deposits)
tion) step. Thereafter, the silicon oxide layer 56 is etched using conventional photolithography techniques to form a barrier layer for insulation between the cells.

It should be noted that the height of silicon oxide layer 56 from the surface of substrate 8 is much higher than the height of field oxide layer 40 from the surface of the substrate.

After that, as shown in FIG. 4(C), 4121(B)
) After depositing approximately 1000 silicon nitride layers over the entire surface of the structure, a conventional etch bank (etch-ba
In step ck), a second silicon nitride film barrier layer 46 is formed on the silicon oxide film layer 56 barrier.

Thereafter, the silicon oxide layer 56 is removed by a conventional wet etching process, and the exposed portion of the first silicon nitride layer 54 and the underlying Bundt oxide layer 51 are etched onto the surface of the substrate. Normal dry-etching to expose
) or by a wet etching process. A gate oxide layer 42 is then grown on the exposed surface of the substrate 8 to a thickness of about 250 nm, and about 150 nm thick over the entire surface.
0 people polycrystalline silicon 5 days is normal L P CV D
(Low Pressure Chemical Vap
our Deposition) process.

Thereafter, the polycrystalline silicon 58 is converted to a conductivity type layer by doping with an N-type impurity such as POCl3. However, No.sub.2 doped polycrystalline silicon 58 can also be deposited.

Thereafter, after forming doped polycrystalline silicon 58 as shown in FIG. Polycrystalline silicon 58 is removed by a hack process. Because of this etch pack process,
The height of the partition layer 46 from the surface of the substrate 8 is the height of the field oxide film 40 from the surface of the substrate 8 and the height of the polycrystalline silicon 5.
It is easy to understand that it must be higher than the sum of the heights of 8. After that, the photoresist film 6
Remove 0. Then, the gate electrodes 44 of the ROM cells 21 to 27 are insulated from the gate electrodes 44 of adjacent cells by the partition layer 46.

Thereafter, as shown in FIG. 4(F), the string selection cell 20 and the gate electrode (not shown) of the ROM cell 2 are identified by applying a photoresist film 62 and etching polycrystalline silicon. .

Thereafter, as shown in FIG. 4C, a photoresist layer 64 is formed to expose the gate electrode 44 of the string select cell 20 and the selected ROM cell 22 to be programmed. Ru.

After that, the poron ion is released with an energy of 75 keV at about 3
It is injected at a dose of 1 oz/c.

By implanting this boron ion, the string selection cell 2
0 and ROM cell 22 is programmed for enhancement.

Thereafter, after removing the photoresist film 64, as shown in FIG.
An insulating layer 50, such as PSG or 13PsG, is deposited over the entire surface. Thereafter, an opening 12 is formed to expose a portion of the N° connection region 16, and the column lines 10 are formed by a metal application and patterning process, such as A/2.

<Effects of the Invention> Since the mask ROM according to the present invention described above can reduce the width of the partition layer, it can have a structure with high density in terms of usage. In addition, since the source and drain of the conventional MO3FET can be removed, the channel resistance can be reduced without having to expand the channel region. Unnecessary programmed ion implantation due to misalignment can be prevented by the photo process and the partition wall of the insulating film for gate insulation during ion implantation, and the polycrystalline polysilicon formed on the side walls thereof.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a part of the mask ROM according to the present invention, FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1, and FIG.
An equivalent circuit diagram of one memory string connected between the column line of the mask ROM shown in the figure and the ground, and FIGS. 4(A) to 4(G) are process diagrams sequentially showing the manufacturing process of the mask ROM. It is. 8 - Substrate 10 - Column line 14 - Memory string 16 - Connection area 18 - Base Y$ area 0 to 28 - Cells 30 to 38 - Row line 44 - Gate voltage (5 46 --- Barrier layer 48 - Channel region 50 - Insulating layer Fig. 1 Fig. 2 Fig. 3

Claims (7)

[Claims] (1) Having a large number of memory strings in which a large number of memory cells are connected in series between each of the second conductive type connection regions on the first conductive type semiconductor substrate and the second conductive type reference region. In the mask ROM, each of the memory strings includes an insulating barrier layer separated by a predetermined distance between the connection region and the reference region to isolate the memory cells, and a substrate on which the memory cells are formed. a gate oxide layer formed on the surface of the memory cell, a gate electrode formed on the sidewall of the barrier layer between each gate oxide layer and the adjacent memory cell, and a memory cell adjacent to the connection region. a channel region having ions of a first conductivity type under the oxide film layer of the selected memory cell or cell; and a channel region having ions of the first conductivity type under the oxide film layer of the unselected memory cell or cell and under the barrier layer. A mask ROM comprising: a channel region having ions of a second conductivity type; (2) Claim (1) characterized in that the partition layer is a Si_3N_4 layer or a multilayer structure including a Si_3N_4 layer.
Mask ROM described. (3) The mask ROM according to claim 1, wherein the memory cell adjacent to the connection region is a string selection cell. (4) A method for manufacturing a mask ROM having a memory string in which a large number of memory cells are connected in series, comprising the following steps. A process of forming a thick oxide film layer to limit the active region where the memory string is formed on the semiconductor substrate of the first conductivity type.A process of implanting ions of the second conductivity type into the active region on the substrate. Forming a gate oxide layer of a memory cell on the substrate surface in the active area to provide isolation between each surface of the gate oxide layer and adjacent memory cells A step of forming a gate electrode of a conductive type on the side wall of a partition layer located in the memory cell A step of implanting ions of a first conductive type into the lower part of the gate oxide film of a selected memory cell among the memory cells. (5) After the step of implanting ions of the first conductivity type, the method further comprises the step of forming a connection region and a reference region of the second conductivity type on the semiconductor substrate at both ends of the memory string. ) The method for manufacturing the mask ROM described in . (6) The memory cell connected to the connection region is a string selection cell in which the lower part of the gate oxide film layer of the memory cell is ion-implanted with a first conductivity type. Method for manufacturing mask ROM. (7) The insulator of the partition layer is Si_3N_4 layer or Si_3
6. The method of manufacturing a mask ROM according to claim 5, wherein the mask ROM has a multilayer structure including N_4 layers.