JPH06203225A - メモリ装置 - Google Patents

メモリ装置

Info

Publication number
JPH06203225A
JPH06203225A JP4360097A JP36009792A JPH06203225A JP H06203225 A JPH06203225 A JP H06203225A JP 4360097 A JP4360097 A JP 4360097A JP 36009792 A JP36009792 A JP 36009792A JP H06203225 A JPH06203225 A JP H06203225A
Authority
JP
Japan
Prior art keywords
chip
memory device
substrate
conductive plate
connection terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4360097A
Other languages
English (en)
Inventor
Koichi Saito
浩一 斉藤
Takeshi Iijima
武 飯島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP4360097A priority Critical patent/JPH06203225A/ja
Priority to US08/163,428 priority patent/US5440451A/en
Publication of JPH06203225A publication Critical patent/JPH06203225A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Abstract

(57)【要約】 【目的】 ＩＣチップを内蔵した携帯可能なメモリ装置
において、ＩＣチップが帯電しないようにする。 【構成】 基板１の上面には絶縁板１１が接着剤１２に
よって接着されている。絶縁板１１の上面には導電板１
３が貼り付けられている。導電板１３、絶縁板１１およ
び接着剤１２の各所定の２箇所にはスリットが形成さ
れ、これらスリットによって非導電構造の凹部１４が形
成されている。そして、これら凹部１４内に、ＩＣチッ
プ６を処理機器に接続するための複数の接続端子２が配
置されている。このため、導電板１３の表面で静電気が
発生しても、この静電気を導電板１３で保持し、非導電
構造の凹部１４内の接続端子２に伝導しないようにする
ことができ、したがってＩＣチップ６が帯電しないよう
にすることができる。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】この発明は、データを処理あるい
は記憶するＩＣチップを内蔵した携帯可能なメモリ装置
に関する。
【０００２】
【従来の技術】携帯可能なメモリ装置には、全体の形状
がカード形状やコイン形状等の平板状であって、データ
を処理あるいは記憶するＩＣチップを基板の一面に搭載
し、処理機器との間でデータの授受を行う際に処理機器
の複数の外部端子とそれぞれ接続される複数の接続端子
を基板の他面に設けた構造のものがある。この場合、基
板の他面に設けられた複数の接続端子は、基板に設けら
れたスルホール導通部および基板の一面に設けられた配
線パターン等を介してＩＣチップと接続されている。
【０００３】
【発明が解決しようとする課題】ところで、このような
メモリ装置では、ＩＣチップを含む基板の一面を塩化ビ
ニル等の樹脂からなる外装材で被っているが、基板の他
面が直接メモリ装置の一外面となり、基板の他面に設け
られた複数の接続端子がメモリ装置の一外面からもろに
突出されている。このため、メモリ装置の一外面におい
て所持者の衣服等との摩擦により静電気が発生した場
合、メモリ装置の一外面から突出されている接続端子お
よびこれに接続されているスルホール導通部、配線パタ
ーン等を介してＩＣチップが帯電することがある。この
ような場合、メモリ装置の一外面から突出されている複
数の接続端子の一部に人体等の導体が接触すると、この
一部の接続端子およびこれに接続されているスルホール
導通部、配線パターン等を介してＩＣチップから放電が
生じ、このときＩＣチップ内のアルミニウム等の金属か
らなる配線パターンの一部に比較的大きな電流が流れ、
この配線パターンの一部が発熱して溶融し、断線してし
まうことがあるという問題があった。この発明の目的
は、ＩＣチップが帯電しないようにすることのできるメ
モリ装置を提供することにある。
【０００４】
【課題を解決するための手段】この発明は、ＩＣチップ
を内蔵した平板状のメモリ装置であって、導電構造とさ
れた一外面に形成された非導電構造の凹部内に、前記Ｉ
Ｃチップを処理機器に接続するための複数の接続端子を
設けたものである。
【０００５】
【作用】この発明によれば、メモリ装置の一外面におい
て静電気が発生しても、この静電気を導電構造の一外面
で保持し、非導電構造の凹部内の接続端子に伝導しない
ようにすることができ、したがってＩＣチップが帯電し
ないようにすることができる。
【０００６】
【実施例】図１（Ａ）および（Ｂ）はこの発明の一実施
例におけるメモリ装置を示したものである。このメモリ
装置はガラスエポキシ等からなる円板状の基板１を備え
ている。基板１の上面の互いに平行する所定の２箇所に
は各１０個ずつの接続端子２がパターン形成されてい
る。各接続端子２は、基板１の上面に設けられた配線パ
ターン３および基板１に設けられたスルホール導通部４
を介して基板１の下面に設けられた配線パターン５に接
続されている。基板１の下面の所定の個所にはＥＥＰＲ
ＯＭやマスクＲＯＭ等の半導体素子からなるＩＣチップ
６が接着剤７によって接着されて搭載されている。ＩＣ
チップ６は、アルミニウムや金等の細線からなるワイヤ
８を介して基板１下の配線パターン５にワイヤボンディ
ングされている。このワイヤボンディングの部分は、エ
ポキシ樹脂やシリコン樹脂等の樹脂からなる封止材９に
よって封止されている。
【０００７】基板１の上面には絶縁性樹脂等からなる円
板状の絶縁板１１が接着剤１２によって接着されてい
る。絶縁板１１の上面には銅等の導電体からなる円板状
の導電板１３が貼り付けられている。なお、導電板１
３、絶縁板１１および接着剤１２の各所定の２箇所には
スリットが形成され、これらスリットによって非導電構
造の凹部１４が形成されている。そして、これら凹部１
４内に接続端子２が配置されている。また、導電板１
３、絶縁板１１および接着剤１２の他の各所定の２箇所
には、このメモリ装置を図示しない処理機器に装着する
際に位置決めとしての役目を果たす凹部１５が形成され
ている。封止材９を含む基板１の下面には塩化ビニル等
の樹脂からなる外装材１６が射出成形等によって形成さ
れている。さらに、基板１、外装材１６および導電板１
３等の外周面にはステンレス等の金属からなる外装リン
グ１７が設けられている。ここで、このメモリ装置の外
径が２２〜２４ｍｍ程度である場合には、一例として、
導電板１３と絶縁板１１との合計厚さを０．２ｍｍ程度
とし、凹部１４の幅を１〜２ｍｍ程度とする。
【０００８】このように、このメモリ装置では、基板１
の上面側に導電板１３を設け、この導電板１３等に形成
された非導電構造の凹部１４内に複数の接続端子２を配
置しているので、導電板１３の表面において静電気が発
生しても、この静電気を導電板１３で保持し、非導電構
造の凹部１４内の接続端子２に伝導しないようにするこ
とができる。したがって、ＩＣチップ６が帯電しないよ
うにすることができ、ひいては帯電したＩＣチップ６か
らの放電に起因するＩＣチップ６内の配線パターンの断
線が生じないようにすることができる。
【０００９】なお、ＩＣチップ６の基板１上への搭載方
法は、ワイヤボンディングに限定されるものではなく、
フリップチップボンディング等であってもよいことはも
ちろんである。また、ＩＣチップ６の個数は、ＥＥＰＲ
ＯＭやマスクＲＯＭ等の１チップの実装の場合のみに限
定されるものではなく、ＥＥＰＲＯＭやマスクＲＯＭ等
のメモリチップとＡＳＩＣ等のコントローラチップとの
２チップの実装の場合であってもよく、またそれ以上の
チップ数であってもよい。
【００１０】
【発明の効果】以上説明したように、この発明によれ
ば、メモリ装置の一外面において静電気が発生しても、
この静電気を導電構造の一外面で保持し、非導電構造の
凹部内の接続端子に伝導しないようにすることができる
ので、ＩＣチップが帯電しないようにすることができ、
ひいては帯電したＩＣチップからの放電に起因するＩＣ
チップ内の配線パターンの断線が生じないようにするこ
とができる。
【図面の簡単な説明】
【図１】（Ａ）はこの発明の一実施例におけるメモリ装
置の平面図、（Ｂ）はそのＸ−Ｘ線に沿う断面図。
【符号の説明】
１ 基板 ２ 接続端子 ６ ＩＣチップ １１ 絶縁板 １３ 導電板 １４ 凹部

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】 ＩＣチップを内蔵した平板状のメモリ装
    置であって、導電構造とされた一外面に形成された非導
    電構造の凹部内に、前記ＩＣチップを処理機器に接続す
    るための複数の接続端子を設けたことを特徴とするメモ
    リ装置。
JP4360097A 1992-12-29 1992-12-29 メモリ装置 Pending JPH06203225A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP4360097A JPH06203225A (ja) 1992-12-29 1992-12-29 メモリ装置
US08/163,428 US5440451A (en) 1992-12-29 1993-12-08 Memory Assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4360097A JPH06203225A (ja) 1992-12-29 1992-12-29 メモリ装置

Publications (1)

Publication Number Publication Date
JPH06203225A true JPH06203225A (ja) 1994-07-22

Family

ID=18467888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4360097A Pending JPH06203225A (ja) 1992-12-29 1992-12-29 メモリ装置

Country Status (2)

Country Link
US (1) US5440451A (ja)
JP (1) JPH06203225A (ja)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
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US5526235A (en) * 1994-06-23 1996-06-11 Garmin Communication And Navigation Electronic storage device and receptacle
US5731629A (en) * 1995-03-10 1998-03-24 Data-Disk Technology, Inc. Personal memory devices carried by an individual which can be read and written to
JP3507251B2 (ja) * 1995-09-01 2004-03-15 キヤノン株式会社 光センサｉｃパッケージおよびその組立方法
US6072698A (en) * 1995-09-27 2000-06-06 Siemens Aktiengesellschaft Chip module with heat insulation for incorporation into a chip card
US6001672A (en) * 1997-02-25 1999-12-14 Micron Technology, Inc. Method for transfer molding encapsulation of a semiconductor die with attached heat sink
US6282097B1 (en) 1998-10-28 2001-08-28 Garmin Corporation Data card having a retractable handle
US6215671B1 (en) 1998-12-10 2001-04-10 Garmin Corporation Method and apparatus for connecting circuit boards
US6250553B1 (en) 1998-12-30 2001-06-26 Garmin Corporation Data card having a retractable handle
US7220615B2 (en) * 2001-06-11 2007-05-22 Micron Technology, Inc. Alternative method used to package multimedia card by transfer molding
US7193305B1 (en) * 2004-11-03 2007-03-20 Amkor Technology, Inc. Memory card ESC substrate insert
US7908080B2 (en) 2004-12-31 2011-03-15 Google Inc. Transportation routing

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61266299A (ja) * 1985-05-20 1986-11-25 三菱電機株式会社 カ−ドｉｃ
JPS62124995A (ja) * 1985-11-26 1987-06-06 株式会社東芝 Ｉｃカ−ド
JPS62169697A (ja) * 1986-01-22 1987-07-25 シャープ株式会社 Ｉｃカ−ド

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3436604A (en) * 1966-04-25 1969-04-01 Texas Instruments Inc Complex integrated circuit array and method for fabricating same
JPH0517268Y2 (ja) * 1986-04-16 1993-05-10

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61266299A (ja) * 1985-05-20 1986-11-25 三菱電機株式会社 カ−ドｉｃ
JPS62124995A (ja) * 1985-11-26 1987-06-06 株式会社東芝 Ｉｃカ−ド
JPS62169697A (ja) * 1986-01-22 1987-07-25 シャープ株式会社 Ｉｃカ−ド

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