JPH06101489B2 - フレキシブルプリント基板 - Google Patents

フレキシブルプリント基板

Info

Publication number
JPH06101489B2
JPH06101489B2 JP63308205A JP30820588A JPH06101489B2 JP H06101489 B2 JPH06101489 B2 JP H06101489B2 JP 63308205 A JP63308205 A JP 63308205A JP 30820588 A JP30820588 A JP 30820588A JP H06101489 B2 JPH06101489 B2 JP H06101489B2
Authority
JP
Japan
Prior art keywords
film
flexible printed
printed circuit
circuit board
polyimide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63308205A
Other languages
English (en)
Other versions
JPH02153543A (ja
Inventor
文博 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63308205A priority Critical patent/JPH06101489B2/ja
Publication of JPH02153543A publication Critical patent/JPH02153543A/ja
Publication of JPH06101489B2 publication Critical patent/JPH06101489B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、フレキシブルプリント基板に関し、特に折り
曲げ性に富むポリイミドフィルムをベースにしたフレキ
シブルプリント基板の構造に関する。
〔従来の技術〕
従来、この種のフレキシブルプリント基板は、ベース基
板としてポリイミドフィルム，ガラエポ板が使用されて
おり、これらのベース基板と銅箔は接着材で貼り合わさ
れ、所定の回路パターンに銅箔を加工し使用される。
〔発明が解決しようとする課題〕
上述したポリイミドフィルムをベース基板として用いた
フレキシブルプリント基板は、ポリイミドフィルム自体
に吸水性があるので、集積回路素子チップ搭載には、信
頼性上の問題がある。一方、ガラエポ板をベース基板と
して用いた場合は、集積回路素子チップ搭載する上での
信頼性は確保されるが、ガラエポ板が折り曲げ性に乏し
いという別の欠点がある。
〔課題を解決するための手段〕
本発明のフレキシブルプリント基板は、ベース基板とし
てのポリイミドフィルムと、折り曲げ部分を除き少なく
とも部品実装部分に成膜された無機膜と、所定のパター
ンに加工された導体膜とを有している。無機膜及び導体
膜は、接着材を用いずポリイミドフィルム上に、真空蒸
着，スパッタあるいはCVDにより直接成膜される。
〔作用〕
上記した本発明のフレキシブルプリント基板の無機膜
は、ポリイミドフィルムに吸着した水が実装される部品
（例えば、集積回路素子チップ）に影響を与えないよう
に阻止層の作用を有ししかも、この無機膜は折り曲げ部
分を避けて形成されているので折り曲げ性も確保され
る。又、上述したように、本発明のフレキシブルプリン
ト基板は、接着材を用いず薄膜形成技術を用いて無機膜
及び導体膜を形成しているので、部品実装性に富む効果
も合わせて持っている。
〔実施例〕
次に、本発明について、実施例を用い説明する。第１図
は、本発明の第１の実施例のフレキシブルプリント基板
に集積回路素子チップを実装した模式断面図である。厚
さ35μｍのポリイミドフィルム１上に選択的にSiO2膜２
（厚さ１μｍ）をスパッタ法で成膜する。本実施例で
は、図中Ａ−Ａを折り曲げるため、SiO2が幅1mm取り除
かれている。次に、銅膜３を真空蒸着法で１μｍ厚に形
成し、フォトリソグラフィ法で所定のパターンに加工す
る。パターン形成後、ニッケル・金を銅膜上に電解メッ
キする。集積回路素子チップ４をダイボンディングし、
この集積回路素子チップ４とフレキシブルプリント基板
の各々の端子パッドを金ワイヤー５でワイヤーボンディ
ングし、最後にモールド材としてエポキシ樹脂６を用い
モールドする。
第２図は、本発明の第２の実施例の模式断面図である。
この実施例は、両面配線パターンの例で、スルーホール
７の部分は、両面の接続を確実に行なうため、SiO2膜２
がスルーホール径に対し一廻り大きな径で除かれてい
る。この実施例では、折り曲げ部Ａ−Ａを除き、ベース
基板の両面にSiO2が成膜されており、より高い信頼性が
得られる利点がある。
上記実施例で用いたSiO2膜は、一例にすぎず、例えばプ
ラズマCVD法で形成されるSiNXを用いてもよいことは、
言うまでもない。又、導体膜として銅膜を実施例では用
いたが、他の金属例えば金を用いてもよいことは言うま
でもない。又、実施例で用いた数値（ポリイミドフィル
ム膜厚SiO2膜厚等）は、一例でありこの値に限るもので
はない。
〔発明の効果〕
以上、説明したように本発明によれば、ベース基板に折
り曲げ性のよいポリイミドフィルムを用い、部品実装部
に無機膜を設けることにより耐湿性にも優れ、高信頼性
が要求される集積回路素子チップ実装にも適するフレキ
シブルプリント基板が得られる。
【図面の簡単な説明】
第１図は、本発明の第１の実施例のフレキシブルプリン
ト基板に集積回路素子を実装した模式断面図、第２図
は、本発明の第２の実施例の模式断面図である。 １……ポリイミドフィルム、２……SiO2膜、３……銅膜
（Ni−Auメッキ）、４……集積回路素子チップ、５……
金ワイヤー、６……エポキシ樹脂、７……スルーホー
ル。

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】ポリイミドフィルム上に折り曲げ部分を除
    き少なくとも部品実装部分に無機膜を設け、さらに所定
    のパターンに加工された導体膜を設けたことを特徴とす
    るフレキシブルプリント基板。
JP63308205A 1988-12-05 1988-12-05 フレキシブルプリント基板 Expired - Lifetime JPH06101489B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63308205A JPH06101489B2 (ja) 1988-12-05 1988-12-05 フレキシブルプリント基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63308205A JPH06101489B2 (ja) 1988-12-05 1988-12-05 フレキシブルプリント基板

Publications (2)

Publication Number Publication Date
JPH02153543A JPH02153543A (ja) 1990-06-13
JPH06101489B2 true JPH06101489B2 (ja) 1994-12-12

Family

ID=17978181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63308205A Expired - Lifetime JPH06101489B2 (ja) 1988-12-05 1988-12-05 フレキシブルプリント基板

Country Status (1)

Country Link
JP (1) JPH06101489B2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6280828B1 (en) 1999-04-27 2001-08-28 Nitto Denko Corporation Flexible wiring board

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9930793B2 (en) * 2014-03-27 2018-03-27 Intel Corporation Electric circuit on flexible substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6280828B1 (en) 1999-04-27 2001-08-28 Nitto Denko Corporation Flexible wiring board

Also Published As

Publication number Publication date
JPH02153543A (ja) 1990-06-13

Similar Documents

Publication Publication Date Title
JP2002016181A (ja) 半導体装置、その製造方法、及び電着フレーム
JPH02272737A (ja) 半導体の突起電極構造及び突起電極形成方法
JP2005277356A (ja) 回路装置
US6407458B1 (en) Moisture-resistant integrated circuit chip package and method
JPH01276750A (ja) 半導体装置
JP3158073B2 (ja) 電子素子のパッケージ方法および電子素子パッケージ
JPH06101489B2 (ja) フレキシブルプリント基板
JPH0425038A (ja) 半導体装置およびその製造方法ならびに半導体装置を用いた電子回路装置
JP2727435B2 (ja) 外部露出型ヒートシンクが付着された薄型ボールグリッドアレイ半導体パッケージ
JP2000208548A (ja) 半導体装置
KR920005952Y1 (ko) 반도체장치
JPH06104375A (ja) 半導体集積回路装置
JPS6276661A (ja) 樹脂封止型半導体装置
JPH0222992Y2 (ja)
JPS6037640B2 (ja) プリント基板
JPH05166961A (ja) 半導体装置及びその実装方法
JPS60200545A (ja) 実装基板
JP2872531B2 (ja) 半導体モジュール基板，及びそれを用いた半導体装置
JPH08241913A (ja) 半導体パッケージ材料および半導体パッケージ
JPS62271442A (ja) 混成集積回路
JPS60262434A (ja) 半導体装置
JPS61272956A (ja) ハイブリツド型半導体装置
JPH1092964A (ja) 半導体装置
JPS6317263Y2 (ja)
KR0122757B1 (ko) 인쇄회로기판을 이용한 멀티 칩 패키지