JPH058864B2 - - Google Patents

Info

Publication number
JPH058864B2
JPH058864B2 JP61189094A JP18909486A JPH058864B2 JP H058864 B2 JPH058864 B2 JP H058864B2 JP 61189094 A JP61189094 A JP 61189094A JP 18909486 A JP18909486 A JP 18909486A JP H058864 B2 JPH058864 B2 JP H058864B2
Authority
JP
Japan
Prior art keywords
wiring
opening
film
disconnected
laser light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61189094A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6344739A (ja
Inventor
Ryoichi Mukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61189094A priority Critical patent/JPS6344739A/ja
Priority to EP87111603A priority patent/EP0256494B1/en
Priority to DE8787111603T priority patent/DE3783404T2/de
Priority to KR1019870008776A priority patent/KR910004038B1/ko
Publication of JPS6344739A publication Critical patent/JPS6344739A/ja
Priority to US07/344,525 priority patent/US4968643A/en
Publication of JPH058864B2 publication Critical patent/JPH058864B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H01L23/5254—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/093—Laser beam treatment in general

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP61189094A 1986-08-12 1986-08-12 半導体装置の製造方法 Granted JPS6344739A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP61189094A JPS6344739A (ja) 1986-08-12 1986-08-12 半導体装置の製造方法
EP87111603A EP0256494B1 (en) 1986-08-12 1987-08-11 Activatable conductive links for semiconductor devices
DE8787111603T DE3783404T2 (de) 1986-08-12 1987-08-11 Leitende aktivierungsverbindungen fuer halbleiteranordnungen.
KR1019870008776A KR910004038B1 (ko) 1986-08-12 1987-08-11 반도체 장치의 금속배선용 활성화 가능 도통링크 및 그의 제조 및 활성화 방법
US07/344,525 US4968643A (en) 1986-08-12 1989-04-26 Method for fabricating an activatable conducting link for metallic conductive wiring in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61189094A JPS6344739A (ja) 1986-08-12 1986-08-12 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS6344739A JPS6344739A (ja) 1988-02-25
JPH058864B2 true JPH058864B2 (enExample) 1993-02-03

Family

ID=16235236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61189094A Granted JPS6344739A (ja) 1986-08-12 1986-08-12 半導体装置の製造方法

Country Status (5)

Country Link
US (1) US4968643A (enExample)
EP (1) EP0256494B1 (enExample)
JP (1) JPS6344739A (enExample)
KR (1) KR910004038B1 (enExample)
DE (1) DE3783404T2 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5070392A (en) * 1988-03-18 1991-12-03 Digital Equipment Corporation Integrated circuit having laser-alterable metallization layer
US5250465A (en) * 1991-01-28 1993-10-05 Fujitsu Limited Method of manufacturing semiconductor devices
US5451811A (en) * 1991-10-08 1995-09-19 Aptix Corporation Electrically programmable interconnect element for integrated circuits
US5321322A (en) * 1991-11-27 1994-06-14 Aptix Corporation Programmable interconnect architecture without active devices
WO1993012582A1 (en) * 1991-12-13 1993-06-24 Knights Technology, Inc. Programmable logic device cell and method
JPH0799791B2 (ja) * 1992-04-15 1995-10-25 インターナショナル・ビジネス・マシーンズ・コーポレイション 透明基板上の回路ライン接続方法
JPH06124913A (ja) * 1992-06-26 1994-05-06 Semiconductor Energy Lab Co Ltd レーザー処理方法
KR960009996B1 (ko) * 1992-08-24 1996-07-25 금성일렉트론 주식회사 반도체 소자의 리페어장치 및 그 배치방법
US5453402A (en) * 1992-12-15 1995-09-26 Advanced Micro Devices, Inc. Selective metal via plug growth technology for deep sub-micrometer ULSI
JPH06260441A (ja) * 1993-03-03 1994-09-16 Nec Corp 半導体装置の製造方法
US5940727A (en) * 1994-10-11 1999-08-17 Massachusetts Institute Of Technology Technique for producing interconnecting conductive links
US5585602A (en) * 1995-01-09 1996-12-17 Massachusetts Institute Of Technology Structure for providing conductive paths
WO1995024734A1 (en) * 1994-03-10 1995-09-14 Massachusetts Institute Of Technology Technique for producing interconnecting conductive links
US5861325A (en) * 1994-03-10 1999-01-19 Massachusetts Institute Of Technology Technique for producing interconnecting conductive links
US5920789A (en) * 1994-10-11 1999-07-06 Massachusetts Institute Of Technology Technique for producing interconnecting conductive links
TW278229B (en) * 1994-12-29 1996-06-11 Siemens Ag Fuse structure for an integrated circuit device and method for manufacturing a fuse structure
JP3160198B2 (ja) * 1995-02-08 2001-04-23 インターナショナル・ビジネス・マシーンズ・コーポレ−ション デカップリング・コンデンサが形成された半導体基板及びこれの製造方法
US5731047A (en) * 1996-11-08 1998-03-24 W.L. Gore & Associates, Inc. Multiple frequency processing to improve electrical resistivity of blind micro-vias
JPH10229125A (ja) * 1997-02-14 1998-08-25 Nec Corp 半導体装置
US6288437B1 (en) * 1999-02-26 2001-09-11 Micron Technology, Inc. Antifuse structures methods and applications
US6472253B1 (en) * 1999-11-15 2002-10-29 Vlsi Technology, Inc. Programmable semiconductor device structures and methods for making the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780738A (en) * 1980-11-07 1982-05-20 Seiko Epson Corp Semiconductor integrated device
US4585490A (en) * 1981-12-07 1986-04-29 Massachusetts Institute Of Technology Method of making a conductive path in multi-layer metal structures by low power laser beam
JPS5996746A (ja) * 1982-11-26 1984-06-04 Hitachi Ltd 半導体装置およびその製造方法
EP0167732B1 (de) * 1984-06-27 1990-09-05 Contraves Ag Verfahren zur Herstellung eines Basismaterials für eine Hybridschaltung
US4674176A (en) * 1985-06-24 1987-06-23 The United States Of America As Represented By The United States Department Of Energy Planarization of metal films for multilevel interconnects by pulsed laser heating
US4814578A (en) * 1985-06-24 1989-03-21 The United States Of America As Represented By The Department Of Energy Planarization of metal films for multilevel interconnects
US4681795A (en) * 1985-06-24 1987-07-21 The United States Of America As Represented By The Department Of Energy Planarization of metal films for multilevel interconnects
JPS62293740A (ja) * 1986-06-13 1987-12-21 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
JPS6344739A (ja) 1988-02-25
US4968643A (en) 1990-11-06
KR880003407A (ko) 1988-05-17
KR910004038B1 (ko) 1991-06-22
EP0256494B1 (en) 1993-01-07
DE3783404T2 (de) 1993-05-06
EP0256494A3 (en) 1988-07-27
EP0256494A2 (en) 1988-02-24
DE3783404D1 (de) 1993-02-18

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