JPH0587178B2 - - Google Patents

Info

Publication number
JPH0587178B2
JPH0587178B2 JP63156225A JP15622588A JPH0587178B2 JP H0587178 B2 JPH0587178 B2 JP H0587178B2 JP 63156225 A JP63156225 A JP 63156225A JP 15622588 A JP15622588 A JP 15622588A JP H0587178 B2 JPH0587178 B2 JP H0587178B2
Authority
JP
Japan
Prior art keywords
wiring
layer
tisi
word line
dissolve
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63156225A
Other languages
English (en)
Japanese (ja)
Other versions
JPH01321656A (ja
Inventor
Hideo Takagi
Noryuki Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP63156225A priority Critical patent/JPH01321656A/ja
Priority to EP19890111073 priority patent/EP0347792A3/en
Priority to KR8908624A priority patent/KR930001543B1/ko
Publication of JPH01321656A publication Critical patent/JPH01321656A/ja
Priority to US07/565,866 priority patent/US5072282A/en
Publication of JPH0587178B2 publication Critical patent/JPH0587178B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P50/667—
    • H10P50/283—
    • H10W20/031—
    • H10W20/081—
    • H10W20/42—
    • H10W20/4441—
    • H10W20/4451—
    • H10W20/47—
    • H10W20/48—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP63156225A 1988-06-23 1988-06-23 半導体装置 Granted JPH01321656A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP63156225A JPH01321656A (ja) 1988-06-23 1988-06-23 半導体装置
EP19890111073 EP0347792A3 (en) 1988-06-23 1989-06-19 Multi-layer wirings on a semiconductor device and fabrication method
KR8908624A KR930001543B1 (en) 1988-06-23 1989-06-22 Multilayer wiring and manufacturing method of semiconductor device
US07/565,866 US5072282A (en) 1988-06-23 1990-08-10 Multi-layer wirings on a semiconductor device and fabrication method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63156225A JPH01321656A (ja) 1988-06-23 1988-06-23 半導体装置

Publications (2)

Publication Number Publication Date
JPH01321656A JPH01321656A (ja) 1989-12-27
JPH0587178B2 true JPH0587178B2 (OSRAM) 1993-12-15

Family

ID=15623095

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63156225A Granted JPH01321656A (ja) 1988-06-23 1988-06-23 半導体装置

Country Status (4)

Country Link
US (1) US5072282A (OSRAM)
EP (1) EP0347792A3 (OSRAM)
JP (1) JPH01321656A (OSRAM)
KR (1) KR930001543B1 (OSRAM)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH073835B2 (ja) * 1990-03-19 1995-01-18 日本プレシジョン・サーキッツ株式会社 半導体装置
EP0491433A3 (en) * 1990-12-19 1992-09-02 N.V. Philips' Gloeilampenfabrieken Method of forming conductive region on silicon semiconductor material, and silicon semiconductor device with such region
KR940006689B1 (ko) * 1991-10-21 1994-07-25 삼성전자 주식회사 반도체장치의 접촉창 형성방법
GB2276491A (en) * 1993-03-26 1994-09-28 Lucas Ind Plc Multilayered connections for intergrated circuits
CN1155062C (zh) * 1996-04-19 2004-06-23 松下电器产业株式会社 半导体器件
KR100346843B1 (ko) * 2000-12-07 2002-08-03 삼성전자 주식회사 층간절연막 형성 방법 및 이를 이용한 반도체 소자의 제조방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3123348A1 (de) * 1980-06-19 1982-03-18 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Halbleiterbaustein und verfahren zu dessen herstellung
JPS5745967A (en) * 1980-09-04 1982-03-16 Toshiba Corp Semiconductor device
US4436582A (en) * 1980-10-28 1984-03-13 Saxena Arjun N Multilevel metallization process for integrated circuits
JPS61166075A (ja) * 1985-01-17 1986-07-26 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPS61206243A (ja) * 1985-03-08 1986-09-12 Mitsubishi Electric Corp 高融点金属電極・配線膜を用いた半導体装置
US4723197A (en) * 1985-12-16 1988-02-02 National Semiconductor Corporation Bonding pad interconnection structure
JPS6358943A (ja) * 1986-08-29 1988-03-14 Mitsubishi Electric Corp 電極・配線膜の構造

Also Published As

Publication number Publication date
US5072282A (en) 1991-12-10
EP0347792A3 (en) 1990-12-05
JPH01321656A (ja) 1989-12-27
EP0347792A2 (en) 1989-12-27
KR930001543B1 (en) 1993-03-04

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees