JPH0585875B2 - - Google Patents

Info

Publication number
JPH0585875B2
JPH0585875B2 JP60075957A JP7595785A JPH0585875B2 JP H0585875 B2 JPH0585875 B2 JP H0585875B2 JP 60075957 A JP60075957 A JP 60075957A JP 7595785 A JP7595785 A JP 7595785A JP H0585875 B2 JPH0585875 B2 JP H0585875B2
Authority
JP
Japan
Prior art keywords
clock
data
latch
delay
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60075957A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61234377A (ja
Inventor
Takeshi Mihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP60075957A priority Critical patent/JPS61234377A/ja
Publication of JPS61234377A publication Critical patent/JPS61234377A/ja
Publication of JPH0585875B2 publication Critical patent/JPH0585875B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
JP60075957A 1985-04-10 1985-04-10 アナログｌｓｉ試験装置 Granted JPS61234377A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60075957A JPS61234377A (ja) 1985-04-10 1985-04-10 アナログｌｓｉ試験装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60075957A JPS61234377A (ja) 1985-04-10 1985-04-10 アナログｌｓｉ試験装置

Publications (2)

Publication Number Publication Date
JPS61234377A JPS61234377A (ja) 1986-10-18
JPH0585875B2 true JPH0585875B2 (de) 1993-12-09

Family

ID=13591213

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60075957A Granted JPS61234377A (ja) 1985-04-10 1985-04-10 アナログｌｓｉ試験装置

Country Status (1)

Country Link
JP (1) JPS61234377A (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2839938B2 (ja) * 1990-06-27 1998-12-24 富士通株式会社 回路模擬試験装置及び該装置における半導体集積回路の試験方法

Also Published As

Publication number Publication date
JPS61234377A (ja) 1986-10-18

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