JPH0584674B2 - - Google Patents

Info

Publication number
JPH0584674B2
JPH0584674B2 JP60074806A JP7480685A JPH0584674B2 JP H0584674 B2 JPH0584674 B2 JP H0584674B2 JP 60074806 A JP60074806 A JP 60074806A JP 7480685 A JP7480685 A JP 7480685A JP H0584674 B2 JPH0584674 B2 JP H0584674B2
Authority
JP
Japan
Prior art keywords
channel mos
mos transistor
transistors
capacitors
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP60074806A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61232633A (ja
Inventor
Shinji Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP60074806A priority Critical patent/JPS61232633A/ja
Publication of JPS61232633A publication Critical patent/JPS61232633A/ja
Publication of JPH0584674B2 publication Critical patent/JPH0584674B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP60074806A 1985-04-09 1985-04-09 半導体集積回路装置 Granted JPS61232633A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60074806A JPS61232633A (ja) 1985-04-09 1985-04-09 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60074806A JPS61232633A (ja) 1985-04-09 1985-04-09 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS61232633A JPS61232633A (ja) 1986-10-16
JPH0584674B2 true JPH0584674B2 (enExample) 1993-12-02

Family

ID=13557919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60074806A Granted JPS61232633A (ja) 1985-04-09 1985-04-09 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS61232633A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02201957A (ja) * 1989-01-30 1990-08-10 Nec Ic Microcomput Syst Ltd マスタースライス方式の半導体集積回路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57133712A (en) * 1981-02-12 1982-08-18 Fujitsu Ltd Constituting method of delay circuit in master slice ic
JPS59163837A (ja) * 1983-03-09 1984-09-14 Toshiba Corp 半導体集積回路

Also Published As

Publication number Publication date
JPS61232633A (ja) 1986-10-16

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees