JPH0574853A - Connecting structure of semiconductor device - Google Patents

Connecting structure of semiconductor device

Info

Publication number
JPH0574853A
JPH0574853A JP3236325A JP23632591A JPH0574853A JP H0574853 A JPH0574853 A JP H0574853A JP 3236325 A JP3236325 A JP 3236325A JP 23632591 A JP23632591 A JP 23632591A JP H0574853 A JPH0574853 A JP H0574853A
Authority
JP
Japan
Prior art keywords
lead
semiconductor device
lead frame
bumps
conventional cases
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3236325A
Other languages
Japanese (ja)
Inventor
Ryoichi Fujimori
良一 藤森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP3236325A priority Critical patent/JPH0574853A/en
Publication of JPH0574853A publication Critical patent/JPH0574853A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Abstract

PURPOSE:To reduce a strain to be caused in a thermocompression bonding operation and to obtain the bonding strength, of the structure, which is more than that in conventional cases by a method wherein the shape of a bump formed on an outer lead for a TAB-system semiconductor device is formed to be a peculiar shape. CONSTITUTION:Bumps 2 on an outer lead 3 are formed to be, e.g. trapezoidal shapes or conical shapes where the area of their tip becomes smaller than the cross-sectional area of formation parts of the bumps; their initial contact area with a lead frame 4 is reduced. Thereby, a load in a thermocompression bonding operation by means of a bonding tool 6 is suppressed to be lower than that in conventional cases, a strain caused in the operation is attenuated as compared with that in conventional cases and the bonding strength, of the structure, which is more than that in conventional cases can be obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に係わり、さ
らに詳しくは、半導体素子とリードフレームとの接続方
法を改良した半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an improved connection method between a semiconductor element and a lead frame.

【0002】[0002]

【従来の技術】最近の電子機器は、小型化、軽量化、高
機能化が著しく、これに伴って、半導体装置も、小形、
表面実装型、高密度実装の要求が強くなってきている。
このため、狭ピッチ、多リードの半導体装置を、キャリ
アフィルム上に形成した回路パターンに接続した半導体
素子をリードフレームに実装することにより実現してい
る。
2. Description of the Related Art Recent electronic devices are remarkably miniaturized, lightened, and highly functional, and accordingly, semiconductor devices are also small and compact.
The demands for surface mounting type and high density mounting are increasing.
Therefore, a narrow-pitch, multi-lead semiconductor device is realized by mounting a semiconductor element connected to a circuit pattern formed on a carrier film on a lead frame.

【0003】図2は、従来の半導体装置の例であり、キ
ャリアフィルムに設けられた回路パターンのインナーリ
ードに半導体素子を接続した半導体装置(以下TAB式
半導体装置と呼ぶ)で、図2(a)は平面図、図2
(b)はそのAA断面図である。上記装置はポリイミド
等の絶縁耐熱性を有するフィルムからなり、所定の間隔
で多数のデバイスホール10が設けられた例えば300
メートル位のキャリアフィルム7に、各デバイスホール
毎に銅箔等からなる多数の回路パターン16を形成して
その一端をデバイスホールに突出させ、インナーリード
8とする。そして、デバイスホールに半導体素子を配置
し、その各電極にボンディングツールによりインナーリ
ードを接続して回路パターンを一点鎖線の位置で11で
切断した物である。なお、回路パターンの下面には例え
ば金メッキが施してある。また、アウターリード3aに
はハーフエッチング等によりバンプが形成されており、
リードフレームのリードとの熱圧着による接合の際に、
その接合強度の増加の助けとなる。
FIG. 2 shows an example of a conventional semiconductor device, which is a semiconductor device (hereinafter referred to as a TAB type semiconductor device) in which a semiconductor element is connected to an inner lead of a circuit pattern provided on a carrier film. ) Is a plan view, FIG.
(B) is the AA sectional view. The apparatus is made of a film having insulation heat resistance such as polyimide, and is provided with a large number of device holes 10 at predetermined intervals, for example, 300.
A large number of circuit patterns 16 made of copper foil or the like are formed for each device hole on the carrier film 7 on the metric side, and one end of the circuit pattern 16 is projected into the device hole to form an inner lead 8. Then, the semiconductor element is arranged in the device hole, the inner lead is connected to each electrode of the semiconductor element by a bonding tool, and the circuit pattern is cut at 11 at the position of the alternate long and short dash line. The lower surface of the circuit pattern is plated with gold, for example. Further, bumps are formed on the outer leads 3a by half etching or the like,
When joining with the lead of the lead frame by thermocompression bonding,
It helps increase the bonding strength.

【0004】上記のようなTAB式半導体装置をリード
フレームに実装するには、リードフレームのデバイスホ
ールに上記装置を配置し、その各アウターリードをリー
ドフレームのリードに整合させる。なお、前記リードフ
レームのリード状には例えば銀メッキが施してある。そ
してヒーターを内蔵したボンディングツールによりアウ
ターリードを熱加圧すれば、それぞれのメッキが溶融
し、両者は強固に熱圧着される。
To mount the TAB type semiconductor device as described above on a lead frame, the device is placed in a device hole of the lead frame and each outer lead of the device is aligned with the lead of the lead frame. The lead shape of the lead frame is plated with silver, for example. Then, when the outer lead is thermally pressed by a bonding tool having a built-in heater, each plating is melted and both are firmly thermocompression bonded.

【0005】TAB式半導体装置を搭載したリードフレ
ームを、図3のようにリードフレームから内側を例えば
エポキシ樹脂14で封止して、リードフレームより切り
放し成形すれば、半導体装置の製造は終了する。
A lead frame having a TAB type semiconductor device mounted therein is sealed from the lead frame with, for example, an epoxy resin 14 as shown in FIG.

【0006】[0006]

【発明が解決しようとする課題】前述のようにTAB式
半導体装置の実装を行った場合、ボンディングツールの
熱加圧によって発生する伸縮等により生ずる歪は、前記
装置のインナーリード、アウターリード双方に悪影響を
与え、場合によっては接合時にアウターリード上のバン
プが形成部より折れたり、半導体素子からインナーリー
ドが外れてしまうという問題点を有する。
When the TAB type semiconductor device is mounted as described above, distortion caused by expansion and contraction caused by heat and pressure of the bonding tool is applied to both the inner lead and the outer lead of the device. There is a problem that the bumps on the outer leads may be broken from the formation portion or the inner leads may come off from the semiconductor element at the time of bonding.

【0007】そこで本発明は、上記の課題を解決すべく
なされたもので、TAB式半導体装置のアウターリード
に設けられたバンプを特異的な形状とすることにより、
十分な接合強度を得るために接合時に必要とされる熱加
圧を低荷重におさえ、接合時に発生する歪を低減させ、
かつ、従来以上の接合強度を得ることを目的としたもの
である。
Therefore, the present invention has been made to solve the above-mentioned problems, and the bumps provided on the outer leads of the TAB semiconductor device have a specific shape.
In order to obtain sufficient joint strength, the heat and pressure required at the time of joining are kept under a low load to reduce the strain generated at the time of joining,
In addition, the purpose is to obtain a bonding strength higher than the conventional one.

【0008】[0008]

【課題を解決するための手段】本発明に係わる半導体装
置は、半導体素子の電極に、絶縁性フィルムに形成した
回路パターンのインナーリードをそれぞれ接続して、外
形切断した、回路パターンのアウターリードにバンプを
有するTAB式半導体装置と、多数のリードを有するリ
ードフレームとからなり、前記装置のアウターリードを
バンプを介してリードフレームのリードにそれぞれ接続
して樹脂等により封止したものである。
A semiconductor device according to the present invention has an outer lead of a circuit pattern obtained by cutting the outer shape by connecting inner leads of a circuit pattern formed on an insulating film to electrodes of a semiconductor element. It is composed of a TAB type semiconductor device having bumps and a lead frame having a large number of leads. The outer leads of the device are respectively connected to the leads of the lead frame via the bumps and sealed with resin or the like.

【0009】[0009]

【作用】リードフレームのデバイスホールに、アウター
リードにバンプを有するTAB式半導体装置である半導
体素子を搭載し、各アウターリードをそれぞれのリード
と整合させ、ボンディングツールで熱加圧して両者を接
合する。ついで、前記素子及びリードフレームのインナ
ーリードを樹脂等により封止し、リードフレームから切
断し外形を成形する。
A semiconductor element, which is a TAB type semiconductor device having bumps on outer leads, is mounted in a device hole of a lead frame, each outer lead is aligned with each lead, and heat is applied by a bonding tool to join the two. .. Next, the element and the inner lead of the lead frame are sealed with a resin or the like, and cut from the lead frame to form the outer shape.

【0010】ここで使用されるTAB式半導体装置のア
ウターリードに設けられるバンプの形状を、アウターリ
ードにおける形成部の断面積より先端部の面積が小さく
なる例えば錐形や台形とし、接合の際にリードフレーム
のリードとの初期における接触面積を小さくすることに
より、従来より低荷重で両者をより強固に接合できる。
また、単純にバンプの先端面積を小さくした柱状のバン
プに比べ、アウターリードに対するバンプの形成部の強
度を減衰させることがない。
The shape of the bump provided on the outer lead of the TAB type semiconductor device used here is, for example, a pyramid or a trapezoid in which the tip area is smaller than the cross-sectional area of the forming portion of the outer lead, and at the time of joining. By reducing the contact area of the lead frame with the lead in the initial stage, the two can be bonded more firmly with a lower load than in the past.
Further, the strength of the bump forming portion with respect to the outer lead is not reduced as compared with the columnar bump in which the tip area of the bump is simply reduced.

【0011】[0011]

【実施例】図1は、本発明の実施例の要部を示すもので
図1(a)は側面図、図1(b)は平面図、図1(c)
は作用説明図である。TAB式半導体装置のアウターリ
ードに形成するバンプの形状を、バンプの形成部の断面
積より先端部の面積が小さくなる台形とすることによ
り、アウターリード3とリードフレームのリード4aと
の初期における接触面積を小さくすることができるの
で、両者を熱圧着する場合に従来必要とされたボンディ
ングツールによって与えられる荷重より小さくしても単
位面積当りに発生する加重は大きくなるために、接合を
する際に荷重によって発生する歪を減少させることがで
きる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the essential parts of an embodiment of the present invention. FIG. 1 (a) is a side view, FIG. 1 (b) is a plan view, and FIG. 1 (c).
FIG. By making the shape of the bump formed on the outer lead of the TAB semiconductor device into a trapezoid in which the area of the tip portion is smaller than the cross-sectional area of the bump forming portion, the outer lead 3 and the lead 4a of the lead frame are initially contacted. Since the area can be reduced, the weight generated per unit area will be large even if the load is smaller than the load applied by the bonding tool conventionally required when thermocompression bonding the both. The strain generated by the load can be reduced.

【0012】なお、バンプ2及びリードフレームのリー
ド4aの両者の表面を錫または錫と鉛の合金で予めメッ
キしておけば、図1(c)に示すように、熱圧着による
接合の際にフィレットが形成され、しかも従来に比べこ
のフィレットは容易に形成されるため、従来以上の接合
強度が得られる。
If the surfaces of both the bumps 2 and the leads 4a of the lead frame are pre-plated with tin or an alloy of tin and lead, as shown in FIG. 1 (c), when they are joined by thermocompression bonding. Since the fillet is formed and the fillet is formed more easily than in the conventional case, the bonding strength higher than that in the conventional case can be obtained.

【0013】図4から図7までは本発明の他の実施例の
要部を示すもので、(a)は側面図、(b)は平面図で
ある。これらはバンプの形状が錐形となっているため、
台形に比べさらにリードフレームのリードとの初期にお
ける接触面積が小さくなるので、熱圧着時に必要とされ
る荷重をさらに小さくしても、充分な単位面積当りの荷
重が得られるので、接合強度を減衰させることなくさら
に歪の発生を抑えることができる。
4 to 7 show the essential parts of another embodiment of the present invention, in which (a) is a side view and (b) is a plan view. Since the bump shape of these is conical,
Since the initial contact area with the lead of the lead frame is smaller than that of the trapezoid, a sufficient load per unit area can be obtained even if the load required for thermocompression bonding is further reduced. It is possible to further suppress the generation of distortion without causing the distortion.

【0014】[0014]

【発明の効果】以上述べたように本発明によれば、TA
B式半導体装置のアウターリードに設けられるバンプの
形状を、アウターリードにおける形成部の断面積より先
端部の面積が小さくなる例えば錐形や台形とすることに
より、バンプのアウターリードに対するバンプの形成部
の強度を減衰させることなく、従来に比べ低荷重の熱圧
着で、前記装置のアウターリードとリードフレームのリ
ードとの接合強度を従来以上得られるという効果を有す
る。
As described above, according to the present invention, TA
The bump formed on the outer lead of the B-type semiconductor device has a shape such as a pyramid or a trapezoid whose tip area is smaller than the cross-sectional area of the formed portion of the outer lead. It is possible to obtain the bonding strength between the outer lead of the apparatus and the lead of the lead frame more than ever before by thermocompression bonding with a lower load than before, without attenuating the strength.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例の要部を示す図。FIG. 1 is a diagram showing a main part of an embodiment of the present invention.

【図2】 従来のTAB式半導体装置の一例を示す図。FIG. 2 is a diagram showing an example of a conventional TAB semiconductor device.

【図3】 従来のTAB式半導体装置を半導体素子とし
て使用した半導体装置の一例を示す図。
FIG. 3 is a diagram showing an example of a semiconductor device using a conventional TAB type semiconductor device as a semiconductor element.

【図4】 本発明の他の実施例の要部を示す図。FIG. 4 is a diagram showing a main part of another embodiment of the present invention.

【図5】 本発明の他の実施例の要部を示す図。FIG. 5 is a diagram showing a main part of another embodiment of the present invention.

【図6】 本発明の他の実施例の要部を示す図。FIG. 6 is a diagram showing a main part of another embodiment of the present invention.

【図7】 本発明の他の実施例の要部を示す図。FIG. 7 is a diagram showing a main part of another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 回路パターン 2 バンプ 3、3a アウターリード 4、4a リードフレーム 5 フィレット 6 ボンディングツール 7 キャリアフィルム 8 インナーリード 9 半導体素子 10 デバイスホール 11 切断位置 12 テストパット 13 スプロケット穴 14 エポキシ樹脂 15 TAB式半導体装置 16 回路パターン 1 Circuit Pattern 2 Bumps 3, 3a Outer Leads 4, 4a Lead Frame 5 Fillet 6 Bonding Tool 7 Carrier Film 8 Inner Lead 9 Semiconductor Element 10 Device Hole 11 Cutting Position 12 Test Pad 13 Sprocket Hole 14 Epoxy Resin 15 TAB Type Semiconductor Device 16 Circuit pattern

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子の電極に絶縁性フィルムに形
成した回路パターンのインナーリードをそれぞれ接続し
たTAB式半導体装置と、多数のリードを有するリード
フレームからなり、前記装置のアウターリードと前記リ
ードフレームのリードとの接合部において、特異的な形
状を有するバンプを介して両者を接続することを特徴と
する半導体装置の接続構造。
1. A TAB type semiconductor device in which inner leads of a circuit pattern formed on an insulating film are connected to electrodes of a semiconductor element, and a lead frame having a large number of leads, and outer leads of the device and the lead frame. A semiconductor device connection structure characterized in that the two are connected to each other through a bump having a specific shape at a joint with the lead.
JP3236325A 1991-09-17 1991-09-17 Connecting structure of semiconductor device Pending JPH0574853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3236325A JPH0574853A (en) 1991-09-17 1991-09-17 Connecting structure of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3236325A JPH0574853A (en) 1991-09-17 1991-09-17 Connecting structure of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0574853A true JPH0574853A (en) 1993-03-26

Family

ID=16999135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3236325A Pending JPH0574853A (en) 1991-09-17 1991-09-17 Connecting structure of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0574853A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010165957A (en) * 2009-01-19 2010-07-29 Nichicon Corp Chip-like solid electrolytic capacitor
JP2012099762A (en) * 2010-11-05 2012-05-24 Nitto Denko Corp Wiring circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010165957A (en) * 2009-01-19 2010-07-29 Nichicon Corp Chip-like solid electrolytic capacitor
JP2012099762A (en) * 2010-11-05 2012-05-24 Nitto Denko Corp Wiring circuit board
US8658903B2 (en) 2010-11-05 2014-02-25 Nitto Denko Corporation Wired circuit board

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