JPH05144816A - Face-down bonding method - Google Patents

Face-down bonding method

Info

Publication number
JPH05144816A
JPH05144816A JP32683591A JP32683591A JPH05144816A JP H05144816 A JPH05144816 A JP H05144816A JP 32683591 A JP32683591 A JP 32683591A JP 32683591 A JP32683591 A JP 32683591A JP H05144816 A JPH05144816 A JP H05144816A
Authority
JP
Japan
Prior art keywords
semiconductor chip
substrate
conductor
electrode
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32683591A
Other languages
Japanese (ja)
Inventor
Osamu Kuwabara
治 桑原
Original Assignee
Casio Comput Co Ltd
カシオ計算機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Comput Co Ltd, カシオ計算機株式会社 filed Critical Casio Comput Co Ltd
Priority to JP32683591A priority Critical patent/JPH05144816A/en
Publication of JPH05144816A publication Critical patent/JPH05144816A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a face-down bonding method with which the flux washing of the connection part between a wiring substrate and a semiconductor chip can be conducted easily by increasing the gap between a wiring substrate and a semiconductor chip even when the height of the solder bump on the semiconductor chip side is low and also subsequent sealing of gap can be conducted easily. CONSTITUTION:A wiring substrate 10 is formed by providing the connection electrode 15 of a conductor 12, which is provided on a substrate 11 through bonding agent 30, in such a manner that the substrate 10 is protruding higher than the coating layer 14 of the solder resist formed on the above-mentioned conductor 12. A bump 22, which is formed protruding to the lower part of a semiconductor chip 20, is heat-welded to the connection electrode 15.

Description

【発明の詳細な説明】 Detailed Description of the Invention

【0001】 [0001]

【産業上の利用分野】この発明は、半導体チップの実装時におけるフラックス洗浄と封止工程に良好な効果が得られるフェイスダウンボンディング方法に関する。 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a face-down bonding method capable of obtaining favorable effects in a flux cleaning and sealing process when mounting a semiconductor chip.

【0002】 [0002]

【従来の技術】図4〜図6には、フェイスダウンボンデ
ィング方法の従来例を示す。それらのうち、図4は配線
基板の部分平面図、図5は配線基板の部分縦断側面図、
図6は半導体チップがボンディングされた配線基板の部分縦断側面図である。 FIG. 6 is a partial longitudinal side view of a wiring board to which a semiconductor chip is bonded. これらの図に基づいて、従来のフェイスダウンボンディング方法について説明すると、半導体チップ用配線基板100は、ガラスエポキシなどの硬質基板110上に導体120が接着剤130を介して配設され、該導体120上にソルダーレジスト140が形成されている。 The conventional face-down bonding method will be described based on these figures. In the semiconductor chip wiring board 100, a conductor 120 is arranged on a hard substrate 110 such as glass epoxy via an adhesive 130, and the conductor 120 is provided. A solder resist 140 is formed on the solder resist 140. そして、その導体120の接続用電極部121と対応するソルダーレジスト140部分には開口部141が形成されている。 An opening 141 is formed in the solder resist 140 portion corresponding to the connecting electrode portion 121 of the conductor 120. 一方、半導体チップ20 On the other hand, the semiconductor chip 20
0の下面側にはソルダーレジスト210が形成されるとともにハンダバンプ220が形成されている。 A solder resist 210 is formed and a solder bump 220 is formed on the lower surface side of 0. そして、 And
その半導体チップ200のハンダバンプ220が加熱処理されて半導体チップ用配線基板300の導体120の接続用電極部121に溶着されている。 The solder bump 220 of the semiconductor chip 200 is heat-treated and welded to the connecting electrode portion 121 of the conductor 120 of the wiring board 300 for the semiconductor chip. 2. Description of the Related Art FIGS. 4 to 6 show a conventional example of a face-down bonding method. Of these, FIG. 4 is a partial plan view of the wiring board, FIG. 5 is a partial vertical side view of the wiring board, 2. Description of the Related Art FIGS. 4 to 6 show a conventional example of a face-down bonding method. Of these, FIG. 4 is a partial plan view of the wiring board, FIG. 5 is a partial vertical side view of the wiring board,
FIG. 6 is a partial vertical cross-sectional side view of a wiring board to which a semiconductor chip is bonded. A conventional face-down bonding method will be described with reference to these drawings. In the semiconductor chip wiring board 100, a conductor 120 is arranged on a hard substrate 110 such as glass epoxy with an adhesive 130, and the conductor 120 is provided. A solder resist 140 is formed on top. An opening 141 is formed in the portion of the solder resist 140 corresponding to the connecting electrode portion 121 of the conductor 120. On the other hand, the semiconductor chip 20 FIG. 6 is a partial vertical cross-sectional side view of a wiring board to which a semiconductor chip is bonded. A conventional face-down bonding method will be described with reference to these drawings. In the semiconductor chip wiring board 100, a conductor 120 is arranged on a hard substrate 110 such as glass lithography with an adhesive 130, and the conductor 120 is provided. A solder resist 140 is formed on top. An opening 141 is formed in the portion of the solder resist 140 corresponding to the connecting electrode portion 121 of the conductor 120. On the other hand, the semiconductor chip 20
Solder resist 210 and solder bumps 220 are formed on the lower surface side of 0. And Solder resist 210 and solder bumps 220 are formed on the lower surface side of 0. And
The solder bump 220 of the semiconductor chip 200 is heat-treated and welded to the connecting electrode portion 121 of the conductor 120 of the semiconductor chip wiring board 300. The solder bump 220 of the semiconductor chip 200 is heat-treated and welded to the connecting electrode portion 121 of the conductor 120 of the semiconductor chip wiring board 300.

【0003】 [0003]

【発明が解決しようとする課題】しかし、上記従来のフ
ェイスダウンボンディング方法は、配線基板100の導
体120の接続用電極部121の上端面が図5に示すよ
うに導体120の上端面の高さと略同じでソルダーレジ
スト140の開口部141内に引込んでいて、その接続
用電極部121にハンダバンプ220を介して半導体チ
ップ200が取り付けられていた。そのため、半導体チ
ップ200側のハンダバンプ220の高さが小さい(例
えば、40〜50μm)ときには、接続した配線基板1
00と半導体チップ200との隙間の間隔aが小さくなってその接続部のフラックス洗浄ができず、また、その後の隙間の封止工程で封止用樹脂230がその隙間に入って行かないという欠点があった。 Disadvantages that the gap a between 00 and the semiconductor chip 200 becomes small and the flux cleaning of the connection portion cannot be performed, and the sealing resin 230 does not enter the gap in the subsequent gap sealing step. was there. この発明は、このような状況に鑑みてなされたもので、半導体チップ200 The present invention has been made in view of such a situation, and the semiconductor chip 200
側のハンダバンプ220の高さが小さいときであっても接続した配線基板100と半導体チップ200との隙間の間隔aを大きくさせて、その接続部のフラックス洗浄が容易で、かつ、その後の隙間の封止が容易なフェイスダウンボンディング方法を提供することを目的とする。 Even when the height of the solder bump 220 on the side is small, the gap a between the connected wiring board 100 and the semiconductor chip 200 is increased so that the flux cleaning of the connection portion can be easily performed, and the gap after that can be easily cleaned. An object of the present invention is to provide a face-down bonding method that can be easily sealed. However, in the above-described conventional face-down bonding method, the upper end surface of the connecting electrode portion 121 of the conductor 120 of the wiring board 100 has the same height as the upper end surface of the conductor 120 as shown in FIG. The semiconductor chip 200 is drawn in the opening 141 of the solder resist 140 in substantially the same manner, and the semiconductor chip 200 is attached to the connecting electrode portion 121 via the solder bump 220. Therefore, when the height of the solder bump 220 on the semiconductor chip 200 side is small (for example, 40 to 50 μm), the connected wiring board 1 is connected. However, in the above-described conventional face-down bonding method, the upper end surface of the connecting electrode portion 121 of the conductor 120 of the wiring board 100 has the same height as the upper end surface of the conductor 120 as shown in FIG. The semiconductor chip 200 is drawn in the opening 141 of the solder resist 140 in substantially the same manner, and the semiconductor chip 200 is attached to the connecting electrode portion 121 via the solder bump 220. Therefore, when the height of the solder bump 220 on the semiconductor chip 200 side is small (for example, 40 to 50 μm), the connected wiring board 1 is connected.
00 is a gap between the semiconductor chip 200 and the semiconductor chip 200, the flux cannot be washed at the connecting portion, and the sealing resin 230 does not enter the gap in the subsequent gap sealing step. was there. The present invention has been made in view of such circumstances, and the semiconductor chip 200 00 is a gap between the semiconductor chip 200 and the semiconductor chip 200, the flux cannot be washed at the connecting portion, and the sealing resin 230 does not enter the gap in the subsequent gap sealing step. Was there. The present invention has been made in view of such circumstances, and the semiconductor chip 200
Even when the height of the solder bumps 220 on the side is small, the gap a between the connected wiring board 100 and the semiconductor chip 200 is increased to facilitate flux cleaning of the connection portion and to reduce the gap after that. An object of the present invention is to provide a face-down bonding method that facilitates sealing. Even when the height of the solder bumps 220 on the side is small, the gap a between the connected wiring board 100 and the semiconductor chip 200 is increased to facilitate flux cleaning of the connection portion and to reduce the gap after that. An object of the present invention is to provide a face-down bonding method that facilitates sealing.

【0004】 [0004]

【課題を解決するための手段】この発明に係るフェイス
ダウンボンディング方法は、上記目的を達成するため
に、配線基板の基板上に配設された導体の接続用電極部
に、前記導体上のソルダーレジストの被覆層より高く突
出するパッドを形成する。その後、この配線基板の前記
パッドの上端部に、半導体チップの下方に突出して形成
されたバンプを熱溶着させるようにしている。前記パッ
ドは前記導体上にメッキを施すことによって形成しても
よい。また、前記基板は硬質基板により形成してもよ
い。
In order to achieve the above-mentioned object, a face-down bonding method according to the present invention has a structure in which a connecting electrode portion of a conductor arranged on a substrate of a wiring board is connected to a solder on the conductor. Pads are formed that project above the cover layer of resist. After that, a bump formed so as to protrude below the semiconductor chip is heat-welded to the upper end portion of the pad of the wiring board. The pads may be formed by plating the conductor. The substrate may be a hard substrate.

【0005】[0005]

【作用】この発明によれば、配線基板の導体の接続用電
極部を、ソルダーレジストの被覆層より高く突出した状
態に形成し、該接続用電極部の上端部に半導体チップの
下方に突出して形成されたバンプを熱溶着させて接続し
ているので、その接続した配線基板と半導体チップとの
隙間の間隔が、その導体上に突出した接続用電極部の高
さ分だけ大きくなって、半導体チップ側のバンプの高さ
が小さいときであっても、その隙間のフラックス洗浄が
容易で、かつ、その後、その隙間に封止材が入り易いフ
ェイスダウンボンディング方法となる。前記接続用電極
を、導体上へのメッキを施することにより形成すれば、
その形成が簡単にできる。 Its formation is easy. According to the present invention, the connecting electrode portion of the conductor of the wiring board is formed so as to project higher than the coating layer of the solder resist, and the upper end portion of the connecting electrode portion projects below the semiconductor chip. Since the formed bumps are connected by heat welding, the gap between the connected wiring board and the semiconductor chip is increased by the height of the connecting electrode portion protruding above the conductor, and Even when the height of the bumps on the chip side is small, the face-down bonding method is one in which flux cleaning of the gap is easy and the sealing material easily enters the gap thereafter. If the connection electrode is formed by plating a conductor, According to the present invention, the connecting electrode portion of the conductor of the wiring board is formed so as to project higher than the coating layer of the solder resist, and the upper end portion of the connecting electrode portion projects below the semiconductor chip. Since the formed bumps are connected by heat welding, the gap between the connected wiring board and the semiconductor chip is increased by the height of the connecting electrode portion portion above the conductor, and Even when the height of the bumps on the chip side is small, If the connection electrode is formed by plating a conductor, the face-down bonding method is one in which flux cleaning of the gap is easy and the sealing material easily enters the gap thereafter.
Its formation is easy. Its formation is easy.

【0006】 [0006]

【実施例】以下、この発明を図示する実施例に基づいて
説明する。図1〜図3にはこの発明の実施例を示す。そ
れらのうち、図1は配線基板への半導体チップの接続構
造を示す部分縦断側面図、図2は配線基板の部分平面
図、図3は配線基板の部分縦断側面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to illustrated embodiments. 1 to 3 show an embodiment of the present invention. Among them, FIG. 1 is a partial vertical sectional side view showing a connection structure of a semiconductor chip to a wiring substrate, FIG. 2 is a partial plan view of the wiring substrate, and FIG. 3 is a partial vertical sectional side view of the wiring substrate.

【0007】この実施例のフェイスダウンボンディング
方法は、基板11上に接着剤13を介して配設された導
体12の接続用電極部15を、同導体12上に形成され
たソルダーレジストの被覆層14より高く突出した状態
に形成して配線基板10を作る。そして、その接続用電
極部15の上端部に、半導体チップ20の下方に突出し
て形成されたバンプ22を熱溶着させている。
In the face-down bonding method of this embodiment, the connecting electrode portion 15 of the conductor 12 provided on the substrate 11 via the adhesive 13 is covered with the solder resist coating layer formed on the conductor 12. The wiring board 10 is formed by forming the wiring board 10 so as to project higher than 14. Then, a bump 22 formed so as to project downward from the semiconductor chip 20 is heat-welded to the upper end portion of the connecting electrode portion 15.

【0008】その各構成部分について、より詳しく説明
すれば、前記配線基板10の基板11は、例えば、ガラ
スなどの非導電性硬質基板により形成されている。この
基板11上に、図3に示すように接着剤13を介して銅
(Cu)箔などからなる導体12をラミネートしてパタ
ーン形成した上、その導体12の接続用電極部12aを
避けた状態でソルダーレジストの被膜層14が形成され
ている。ソルダーレジストの材料としては、例えば、エ
ポキシ系の樹脂が使われていて、メッキやハンダ付け時
のマスク材としての機能および耐絶縁層としての機能等
を奏する。
Each of the constituent parts will be described in more detail. The substrate 11 of the wiring board 10 is formed of a non-conductive hard substrate such as glass. As shown in FIG. 3, a conductor 12 made of a copper (Cu) foil or the like is laminated on the substrate 11 via an adhesive 13 to form a pattern, and the connecting electrode portion 12a of the conductor 12 is avoided. Thus, the coating layer 14 of the solder resist is formed. As a material of the solder resist, for example, an epoxy resin is used, and has a function as a mask material at the time of plating or soldering, a function as an insulating layer, and the like.

【0009】前記接続用電極部15は、例えばハンダメ
ッキ、或はニッケル・金メッキ(Ni・Auメッキ)な
どにより、ソルダーレジストの被覆層14より高く突出
した状態に形成されている。
The connecting electrode portion 15 is formed, for example, by solder plating or nickel / gold plating (Ni / Au plating) so as to project higher than the solder resist coating layer 14.

【0010】一方、前記半導体チップ20の下面部には、接続用電極部20aを除いた全面にソルダーレジストの被膜層21が形成され、接続用電極部20aにバンプ22が例えばハンダなどにより、下方に突出した状態で形成されている。 On the other hand, on the lower surface of the semiconductor chip 20, a coating layer 21 of solder resist is formed on the entire surface excluding the connecting electrode portion 20a, and the bump 22 is formed on the connecting electrode portion 20a by soldering or the like. It is formed in a protruding state.

【0011】配線基板10の接続用電極部15および半導体チップ20のバンプ22は上記のように構成され、
次のようにしてフェイスダウンボンディングがなされている。 Face-down bonding is performed as follows. The connecting electrode portion 15 of the wiring board 10 and the bumps 22 of the semiconductor chip 20 are constructed as described above, The connecting electrode portion 15 of the wiring board 10 and the bumps 22 of the semiconductor chip 20 are constructed as described above,
Face down bonding is performed as follows. Face down bonding is performed as follows.

【0012】即ち、半導体チップ20のバンプ22を熱圧着ヘッド等により加熱して、図1に示すように配線基板10の接続用電極部15に熱溶着させて接続する。 That is, the bumps 22 of the semiconductor chip 20 are heated by a thermocompression bonding head or the like to be heat-welded and connected to the connecting electrode portions 15 of the wiring board 10 as shown in FIG.

【0013】このように接続された状態において、配線
用基板10と半導体チップ20との隙間の間隔bが、そ
の接続用電極部12aがソルダーレジストの被覆層14
上に突出している分cだけ従来の間隔a(図6)より大
きくなる。
In such a connected state, the gap b between the wiring substrate 10 and the semiconductor chip 20 is such that the connecting electrode portion 12a is a solder resist coating layer 14
The amount c protruding upward becomes larger than the conventional interval a (FIG. 6).

【0014】その後、その隙間内のフラックスを洗浄し
てから、その隙間に封止用の樹脂30を注入して固めて
封止するのであるが、上記のように、配線用基板10と
半導体チップ20との隙間の間隔bが従来の間隔a(図
6)より大きくなっているので、その接続部のフラック
ス洗浄が容易で、かつ、その後の隙間の封止が容易とな
る。
After that, the flux in the gap is cleaned and then the sealing resin 30 is injected into the gap to be solidified and sealed. As described above, the wiring substrate 10 and the semiconductor chip are sealed. Since the gap b between the gap and the gap 20 is larger than the conventional gap a (FIG. 6), the flux cleaning of the connecting portion is easy and the gap is easily sealed thereafter.

【0015】[0015]

【発明の効果】この発明によれば、接続した配線用基板
と半導体チップとの隙間の間隔が、導体の続用電極部が
導体上に高く突出している分だけ大きくなって、半導体
チップ側のバンプの高さが小さいときであっても、その
接続用のフラックス洗浄が容易で、かつ、その後、その
隙間に封止材が入り易いフェイスダウンボンディング方
法となる。接続用電極を、導体上へのメッキを施して形
成すれば、その形成が簡単にできる。
According to the present invention, the gap between the connected wiring substrate and the semiconductor chip is increased by the amount that the connecting electrode portion of the conductor projects above the conductor. Even when the height of the bump is small, the flux cleaning for the connection can be easily performed, and the sealing material can easily enter the gap thereafter, which is a face-down bonding method. If the connection electrode is formed by plating on the conductor, the formation can be simplified.

【図面の簡単な説明】 [Brief description of drawings]

【図1】配線基板への半導体チップの接続構造を示す部分縦断側面図である。 FIG. 1 is a partial vertical sectional side view showing a connection structure of a semiconductor chip to a wiring board.

【図2】配線基板の部分平面図である。 FIG. 2 is a partial plan view of a wiring board.

【図3】配線基板の部分縦断側面図である。 FIG. 3 is a partial vertical cross-sectional side view of a wiring board.

【図4】従来の配線基板の部分平面図である。 FIG. 4 is a partial plan view of a conventional wiring board.

【図5】同配線基板の部分平面図である。 FIG. 5 is a partial plan view of the wiring board.

【図6】半導体チップがボンディングされた従来の配線基板の部分縦断側面図である。 FIG. 6 is a partial vertical cross-sectional side view of a conventional wiring board to which a semiconductor chip is bonded.

【符号の説明】 [Explanation of symbols]

10 配線基板 11 基板 12 導体 12a 接続用電極部 14 ソルダーレジストの被覆層 20 半導体チップ 21 ソルダーレジストの被覆層 22 バンプ DESCRIPTION OF SYMBOLS 10 Wiring board 11 Substrate 12 Conductor 12a Connection electrode portion 14 Solder resist coating layer 20 Semiconductor chip 21 Solder resist coating layer 22 Bump

Claims (3)

    【特許請求の範囲】[Claims]
  1. 【請求項1】 基板上に導体が配設され、該導体上に同
    導体の接続用電極部を残してソルダーレジストの被膜層
    が形成されてなる配線基板の前記接続用電極部を前記ソ
    ルダーレジストの被膜層より高く突出させて形成し、該
    接続用電極部の上端部に、半導体チップの下方に突出し
    て形成されたバンプを熱溶着させることを特徴とするフ
    ェイスダウンボンディング方法。
    1. A solder resist is provided on a wiring board, wherein a conductor is provided on a substrate, and a coating layer of a solder resist is formed on the conductor leaving a connection electrode portion of the conductor. The method of forming a face-down bond, wherein the bump is formed so as to protrude higher than the coating layer and the bump formed so as to protrude below the semiconductor chip is heat-welded to the upper end portion of the connecting electrode portion.
  2. 【請求項2】 請求項1記載のフェイスダウンボンディング方法において、前記接続用電極は、前記導体上にメッキを施すことにより形成したことを特徴とするフェイスダウンボンディング方法。 2. The face-down bonding method according to claim 1, wherein the connecting electrode is formed by plating the conductor.
  3. 【請求項3】 請求項1又は2記載のフェイスダウンボンディング方法において、前記基板を硬質基板により形成したことを特徴とするフェイスダウンボンディング方法。 3. The face-down bonding method according to claim 1 or 2, wherein the substrate is a hard substrate.
JP32683591A 1991-11-15 1991-11-15 Face-down bonding method Pending JPH05144816A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32683591A JPH05144816A (en) 1991-11-15 1991-11-15 Face-down bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32683591A JPH05144816A (en) 1991-11-15 1991-11-15 Face-down bonding method

Publications (1)

Publication Number Publication Date
JPH05144816A true JPH05144816A (en) 1993-06-11

Family

ID=18192246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32683591A Pending JPH05144816A (en) 1991-11-15 1991-11-15 Face-down bonding method

Country Status (1)

Country Link
JP (1) JPH05144816A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007251188A (en) * 2007-04-27 2007-09-27 Rohm Co Ltd Semiconductor device
JP2008028109A (en) * 2006-07-20 2008-02-07 Sony Corp Semiconductor device and manufacturing method therefor
US7538022B2 (en) 2005-10-07 2009-05-26 Nec Electronics Corporation Method of manufacturing electronic circuit device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7538022B2 (en) 2005-10-07 2009-05-26 Nec Electronics Corporation Method of manufacturing electronic circuit device
JP2008028109A (en) * 2006-07-20 2008-02-07 Sony Corp Semiconductor device and manufacturing method therefor
JP2007251188A (en) * 2007-04-27 2007-09-27 Rohm Co Ltd Semiconductor device
JP4495189B2 (en) * 2007-04-27 2010-06-30 ローム株式会社 Semiconductor device

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