JPH0571137B2 - - Google Patents

Info

Publication number
JPH0571137B2
JPH0571137B2 JP60188157A JP18815785A JPH0571137B2 JP H0571137 B2 JPH0571137 B2 JP H0571137B2 JP 60188157 A JP60188157 A JP 60188157A JP 18815785 A JP18815785 A JP 18815785A JP H0571137 B2 JPH0571137 B2 JP H0571137B2
Authority
JP
Japan
Prior art keywords
wiring
layer
cell
output
metal wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60188157A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6247148A (ja
Inventor
Akihiro Sueda
Hitoshi Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP60188157A priority Critical patent/JPS6247148A/ja
Publication of JPS6247148A publication Critical patent/JPS6247148A/ja
Publication of JPH0571137B2 publication Critical patent/JPH0571137B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP60188157A 1985-08-27 1985-08-27 半導体集積回路装置 Granted JPS6247148A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60188157A JPS6247148A (ja) 1985-08-27 1985-08-27 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60188157A JPS6247148A (ja) 1985-08-27 1985-08-27 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS6247148A JPS6247148A (ja) 1987-02-28
JPH0571137B2 true JPH0571137B2 (cg-RX-API-DMAC7.html) 1993-10-06

Family

ID=16218750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60188157A Granted JPS6247148A (ja) 1985-08-27 1985-08-27 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS6247148A (cg-RX-API-DMAC7.html)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007043049A (ja) 2004-12-20 2007-02-15 Matsushita Electric Ind Co Ltd セル、スタンダードセル、スタンダードセル配置方法、スタンダードセルライブラリ、ならびに半導体集積回路
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
KR101739709B1 (ko) 2008-07-16 2017-05-24 텔라 이노베이션스, 인코포레이티드 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현

Also Published As

Publication number Publication date
JPS6247148A (ja) 1987-02-28

Similar Documents

Publication Publication Date Title
US6870255B1 (en) Integrated circuit wiring architectures to support independent designs
US5977574A (en) High density gate array cell architecture with sharing of well taps between cells
JP4882455B2 (ja) 半導体集積回路のユニットセルおよびユニットセルを使用した配線方法および配線プログラム
EP0181059B1 (en) Semiconductor integrated circuit for clock distribution
JPH09162279A (ja) 半導体集積回路装置およびその製造方法
JPS59172250A (ja) 万能配列体
EP0026233B1 (en) Semiconductor integrated circuit and wiring method therefor
JPH0571137B2 (cg-RX-API-DMAC7.html)
US20030015800A1 (en) Semiconductor device having a multiple layer wiring structure, wiring method, wiring device, and recording medium
US4947229A (en) Semiconductor integrated circuit
US5111271A (en) Semiconductor device using standard cell system
US6900540B1 (en) Simulating diagonal wiring directions using Manhattan directional wires
JPH0750817B2 (ja) 配線相互接続構造体
JP2001127162A (ja) 半導体集積回路
JP3281234B2 (ja) 半導体集積回路装置及びその製造方法
US4746965A (en) Integrated semiconductor circuit device
JPH1041393A (ja) 半導体スタンダードセル及びその配置配線方法
JPH06326214A (ja) 多層配線構造及びその形成方法
US5917206A (en) Gate array system in which functional blocks are connected by fixed wiring
JPH05343653A (ja) 半導体集積回路装置及びその配線方法
JPH0555533A (ja) 半導体集積回路
JP2947219B2 (ja) スタンダードセル方式の半導体集積回路の配線構造
JPH06112450A (ja) 半導体集積回路のブロックレイアウト方法
EP0288688A2 (en) Porous circuit macro for semiconductor integrated circuits
JPH06216249A (ja) Ｉｃチップ自動レイアウト設計システム

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term