JPH0564479B2 - - Google Patents

Info

Publication number
JPH0564479B2
JPH0564479B2 JP17228484A JP17228484A JPH0564479B2 JP H0564479 B2 JPH0564479 B2 JP H0564479B2 JP 17228484 A JP17228484 A JP 17228484A JP 17228484 A JP17228484 A JP 17228484A JP H0564479 B2 JPH0564479 B2 JP H0564479B2
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
metal plate
circuit board
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP17228484A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6150350A (ja
Inventor
Norimichi Matsushita
Noryuki Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichikon KK
Original Assignee
Nichikon KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nichikon KK filed Critical Nichikon KK
Priority to JP17228484A priority Critical patent/JPS6150350A/ja
Publication of JPS6150350A publication Critical patent/JPS6150350A/ja
Publication of JPH0564479B2 publication Critical patent/JPH0564479B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142Metallic substrates having insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4871Bases, plates or heatsinks
    • H01L21/4878Mechanical treatment, e.g. deforming
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP17228484A 1984-08-18 1984-08-18 混成集積回路基板 Granted JPS6150350A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17228484A JPS6150350A (ja) 1984-08-18 1984-08-18 混成集積回路基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17228484A JPS6150350A (ja) 1984-08-18 1984-08-18 混成集積回路基板

Publications (2)

Publication Number Publication Date
JPS6150350A JPS6150350A (ja) 1986-03-12
JPH0564479B2 true JPH0564479B2 (zh) 1993-09-14

Family

ID=15939070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17228484A Granted JPS6150350A (ja) 1984-08-18 1984-08-18 混成集積回路基板

Country Status (1)

Country Link
JP (1) JPS6150350A (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01100995A (ja) * 1987-10-14 1989-04-19 Denki Kagaku Kogyo Kk 金属ベース回路基板の多量製造方法
JP2585643B2 (ja) * 1987-11-19 1997-02-26 電気化学工業株式会社 金属ベース回路基板の多量製造方法
FR2835690A1 (fr) * 2002-02-07 2003-08-08 Possehl Electronic France Sa Procede de realisation industrielle d'elements de dissipation thermique pour support de semi-conducteurs a partir d'une bande de metal
JP4488733B2 (ja) 2003-12-24 2010-06-23 三洋電機株式会社 回路基板の製造方法および混成集積回路装置の製造方法。
JP4845090B2 (ja) * 2005-07-28 2011-12-28 オンセミコンダクター・トレーディング・リミテッド 回路装置の製造方法
JP6581861B2 (ja) * 2015-09-18 2019-09-25 イビデン株式会社 電子部品搭載用基板の製造方法

Also Published As

Publication number Publication date
JPS6150350A (ja) 1986-03-12

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees