JPH0560136B2 - - Google Patents

Info

Publication number
JPH0560136B2
JPH0560136B2 JP58246278A JP24627883A JPH0560136B2 JP H0560136 B2 JPH0560136 B2 JP H0560136B2 JP 58246278 A JP58246278 A JP 58246278A JP 24627883 A JP24627883 A JP 24627883A JP H0560136 B2 JPH0560136 B2 JP H0560136B2
Authority
JP
Japan
Prior art keywords
signal
timing
control
common
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58246278A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60140455A (ja
Inventor
Seiji Kashioka
Hirotada Ueda
Kanji Kato
Masakazu Ejiri
Tetsuo Noguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58246278A priority Critical patent/JPS60140455A/ja
Publication of JPS60140455A publication Critical patent/JPS60140455A/ja
Publication of JPH0560136B2 publication Critical patent/JPH0560136B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP58246278A 1983-12-28 1983-12-28 複数の処理ブロツクの制御装置 Granted JPS60140455A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58246278A JPS60140455A (ja) 1983-12-28 1983-12-28 複数の処理ブロツクの制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58246278A JPS60140455A (ja) 1983-12-28 1983-12-28 複数の処理ブロツクの制御装置

Publications (2)

Publication Number Publication Date
JPS60140455A JPS60140455A (ja) 1985-07-25
JPH0560136B2 true JPH0560136B2 (enrdf_load_stackoverflow) 1993-09-01

Family

ID=17146156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58246278A Granted JPS60140455A (ja) 1983-12-28 1983-12-28 複数の処理ブロツクの制御装置

Country Status (1)

Country Link
JP (1) JPS60140455A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62118479A (ja) * 1985-11-19 1987-05-29 Sony Corp 情報処理システム

Also Published As

Publication number Publication date
JPS60140455A (ja) 1985-07-25

Similar Documents

Publication Publication Date Title
EP0135879B1 (en) Interface circuit and method for connecting a memory controller with a synchronous or an asynchronous bus system
JPS625406A (ja) 状態装置
US6628660B1 (en) Finite state machine with associated memory
KR930008042B1 (ko) 마이크로 콘트롤러 유닛
JPS6162963A (ja) 小さなレジスタから大きなレジスタにデータワードを転送するための方法と装置
US20040221078A1 (en) Programmable state machine interface
JPH0560136B2 (enrdf_load_stackoverflow)
JP2000099188A (ja) クロック切替回路
JP3159702B2 (ja) データワードの時間組込み処理方法及びその方法を実施する装置
US5826063A (en) Apparatus and method for programming the setup, command and recovery time periods within a transaction cycle
JP4438276B2 (ja) データ転送装置
JP2673145B2 (ja) コンピュータ制御によるパルス・インターバル・シーケンスの生成方法
JPH0736819A (ja) Dmaデータ転送装置
JPS63208905A (ja) シ−ケンス発生回路
EP1122733A1 (en) Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and relative circuit
JPH0690657B2 (ja) クロツク切替回路
JP3534915B2 (ja) パラレル入出力ポート
JP2867480B2 (ja) メモリ切替回路
JPS58119026A (ja) プログラマブル・コントロ−ラの入出力デ−タ伝送方式
JPH0344212A (ja) 論理パス多重化方式
JPH08329670A (ja) 半導体装置
JPS6068447A (ja) インタ−フエ−ス制御装置
JPH01251897A (ja) 時分割スイッチ回路
JPS6346509A (ja) シ−ケンス制御装置
JPH08106430A (ja) データ転送方法