JPH0550138B2 - - Google Patents
Info
- Publication number
- JPH0550138B2 JPH0550138B2 JP58225718A JP22571883A JPH0550138B2 JP H0550138 B2 JPH0550138 B2 JP H0550138B2 JP 58225718 A JP58225718 A JP 58225718A JP 22571883 A JP22571883 A JP 22571883A JP H0550138 B2 JPH0550138 B2 JP H0550138B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- spacer
- insulating film
- etching
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H10W10/0143—
-
- H10W10/17—
Landscapes
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58225718A JPS60117753A (ja) | 1983-11-30 | 1983-11-30 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58225718A JPS60117753A (ja) | 1983-11-30 | 1983-11-30 | 半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60117753A JPS60117753A (ja) | 1985-06-25 |
| JPH0550138B2 true JPH0550138B2 (enExample) | 1993-07-28 |
Family
ID=16833720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58225718A Granted JPS60117753A (ja) | 1983-11-30 | 1983-11-30 | 半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60117753A (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4876216A (en) * | 1988-03-07 | 1989-10-24 | Applied Micro Circuits Corporation | Semiconductor integrated circuit manufacturing process providing oxide-filled trench isolation of circuit devices |
| IT1236728B (it) * | 1989-10-24 | 1993-03-31 | Sgs Thomson Microelectronics | Procedimento per formare la struttura di isolamento e la struttura di gate di dispositivi integrati |
| US5077234A (en) * | 1990-06-29 | 1991-12-31 | Digital Equipment Corporation | Planarization process utilizing three resist layers |
-
1983
- 1983-11-30 JP JP58225718A patent/JPS60117753A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60117753A (ja) | 1985-06-25 |
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