IT1236728B - Procedimento per formare la struttura di isolamento e la struttura di gate di dispositivi integrati - Google Patents

Procedimento per formare la struttura di isolamento e la struttura di gate di dispositivi integrati

Info

Publication number
IT1236728B
IT1236728B IT08364389A IT8364389A IT1236728B IT 1236728 B IT1236728 B IT 1236728B IT 08364389 A IT08364389 A IT 08364389A IT 8364389 A IT8364389 A IT 8364389A IT 1236728 B IT1236728 B IT 1236728B
Authority
IT
Italy
Prior art keywords
procedure
forming
integrated devices
gate structure
insulation
Prior art date
Application number
IT08364389A
Other languages
English (en)
Other versions
IT8983643A1 (it
IT8983643A0 (it
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT08364389A priority Critical patent/IT1236728B/it
Publication of IT8983643A0 publication Critical patent/IT8983643A0/it
Priority to US07/596,301 priority patent/US5122473A/en
Priority to DE69027280T priority patent/DE69027280T2/de
Priority to EP90830470A priority patent/EP0429404B1/en
Priority to JP2286923A priority patent/JP3039978B2/ja
Publication of IT8983643A1 publication Critical patent/IT8983643A1/it
Application granted granted Critical
Publication of IT1236728B publication Critical patent/IT1236728B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Non-Volatile Memory (AREA)
IT08364389A 1989-10-24 1989-10-24 Procedimento per formare la struttura di isolamento e la struttura di gate di dispositivi integrati IT1236728B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT08364389A IT1236728B (it) 1989-10-24 1989-10-24 Procedimento per formare la struttura di isolamento e la struttura di gate di dispositivi integrati
US07/596,301 US5122473A (en) 1989-10-24 1990-10-12 Process for forming a field isolation structure and gate structures in integrated misfet devices
DE69027280T DE69027280T2 (de) 1989-10-24 1990-10-22 Verfahren zur Herstellung einer Feldisolationsstruktur und einer Gatestruktur für MISFET integrierte Schaltungen
EP90830470A EP0429404B1 (en) 1989-10-24 1990-10-22 A process for forming a field isolation structure and gate structure in integrated MISFET devices
JP2286923A JP3039978B2 (ja) 1989-10-24 1990-10-24 集積ｍｉｓｆｅｔデバイス中に電界分離構造及びゲート構造を形成する方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT08364389A IT1236728B (it) 1989-10-24 1989-10-24 Procedimento per formare la struttura di isolamento e la struttura di gate di dispositivi integrati

Publications (3)

Publication Number Publication Date
IT8983643A0 IT8983643A0 (it) 1989-10-24
IT8983643A1 IT8983643A1 (it) 1991-04-24
IT1236728B true IT1236728B (it) 1993-03-31

Family

ID=11323576

Family Applications (1)

Application Number Title Priority Date Filing Date
IT08364389A IT1236728B (it) 1989-10-24 1989-10-24 Procedimento per formare la struttura di isolamento e la struttura di gate di dispositivi integrati

Country Status (5)

Country Link
US (1) US5122473A (it)
EP (1) EP0429404B1 (it)
JP (1) JP3039978B2 (it)
DE (1) DE69027280T2 (it)
IT (1) IT1236728B (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5310692A (en) * 1992-05-29 1994-05-10 Sgs-Thomson Microelectronics, Inc. Method of forming a MOSFET structure with planar surface
US5346587A (en) * 1993-08-12 1994-09-13 Micron Semiconductor, Inc. Planarization of a gate electrode for improved gate patterning over non-planar active area isolation
US6034410A (en) * 1994-01-14 2000-03-07 Stmicroelectronics, Inc. MOSFET structure with planar surface
FR2728102A1 (fr) * 1994-12-08 1996-06-14 Sgs Thomson Microelectronics Procede de fabrication de transistors mos de circuit integre
US5606202A (en) * 1995-04-25 1997-02-25 International Business Machines, Corporation Planarized gate conductor on substrates with above-surface isolation
FR2735906B1 (fr) * 1995-06-21 1997-09-05 Sgs Thomson Microelectronics Procede de fabrication de dispositifs semiconducteurs, en particulier de transistors mos ou transistors mos/bipolaires
KR100401377B1 (ko) * 2001-07-09 2003-10-17 엘지.필립스 엘시디 주식회사 액정표시장치 및 그의 구동방법
US6504226B1 (en) 2001-12-20 2003-01-07 Stmicroelectronics, Inc. Thin-film transistor used as heating element for microreaction chamber
FR2839202A1 (fr) * 2002-04-26 2003-10-31 St Microelectronics Sa Zone active de circuit integre mos

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5681974A (en) * 1979-12-07 1981-07-04 Toshiba Corp Manufacture of mos type semiconductor device
JPS56137650A (en) * 1980-03-28 1981-10-27 Nec Corp Manufacture of semiconductor device
JPS5848936A (ja) * 1981-09-10 1983-03-23 Fujitsu Ltd 半導体装置の製造方法
JPS6054450A (ja) * 1983-09-05 1985-03-28 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPS60117391A (ja) * 1983-11-29 1985-06-24 グローリー工業株式会社 循環式自動入出金機
JPS60117753A (ja) * 1983-11-30 1985-06-25 Toshiba Corp 半導体装置の製造方法
US4543706A (en) * 1984-02-24 1985-10-01 Gte Laboratories Incorporated Fabrication of junction field effect transistor with filled grooves
JPS618945A (ja) * 1984-06-25 1986-01-16 Nec Corp 半導体集積回路装置
JPS61100944A (ja) * 1984-10-22 1986-05-19 Seiko Epson Corp 半導体装置の製造方法
US4829019A (en) * 1987-05-12 1989-05-09 Texas Instruments Incorporated Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment
US4876216A (en) * 1988-03-07 1989-10-24 Applied Micro Circuits Corporation Semiconductor integrated circuit manufacturing process providing oxide-filled trench isolation of circuit devices

Also Published As

Publication number Publication date
DE69027280T2 (de) 1996-12-05
EP0429404B1 (en) 1996-06-05
IT8983643A1 (it) 1991-04-24
EP0429404A2 (en) 1991-05-29
DE69027280D1 (de) 1996-07-11
EP0429404A3 (en) 1994-10-12
US5122473A (en) 1992-06-16
IT8983643A0 (it) 1989-10-24
JP3039978B2 (ja) 2000-05-08
JPH03152954A (ja) 1991-06-28

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971030