JPS56137650A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56137650A
JPS56137650A JP4090380A JP4090380A JPS56137650A JP S56137650 A JPS56137650 A JP S56137650A JP 4090380 A JP4090380 A JP 4090380A JP 4090380 A JP4090380 A JP 4090380A JP S56137650 A JPS56137650 A JP S56137650A
Authority
JP
Japan
Prior art keywords
silicon
tetranitride
mask
guard ring
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4090380A
Other languages
Japanese (ja)
Inventor
Kazuo Terada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4090380A priority Critical patent/JPS56137650A/en
Publication of JPS56137650A publication Critical patent/JPS56137650A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Abstract

PURPOSE:To easily house a guard ring under a field oxidation film by providing a dual mask of poly silicon and silicon dioxide on a silicon tetranitride film of a silicon substrate, injecting an ion after partial-oxidation process, forming a silicon tetranitride mask through removal of a silicon dioxide and then oxidizing the said mask. CONSTITUTION:A silicon tetranitride 22 is provided on a silicon substrate 21 to apply masks of polysilicon and 23 and silicon oxide 24. Following this process, they are thermally oxidized to provide a polysilicon 23' and a silicon dioxide 24', increasing the volume of the layer 24'. After providing an ion injection layer 25, the silicon dioxide 24' is removed and the silicon tetranitride 22 is etched by means of a mask 23'. Next, if a field oxidation film 26 is created through oxidation, the ion injection layer 25 becomes a guard ring 25'. Following this process, the silicon tetranitride 22'' is removed to create an impurity diffusion layer 27 in an active region. Under this constitution, it is possible to house a guard ring under a field oxidation film through a single photographic etching process, controlling a distance between the active region and the guard ring easily and minimizing the increase of an inactive layer.
JP4090380A 1980-03-28 1980-03-28 Manufacture of semiconductor device Pending JPS56137650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4090380A JPS56137650A (en) 1980-03-28 1980-03-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4090380A JPS56137650A (en) 1980-03-28 1980-03-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56137650A true JPS56137650A (en) 1981-10-27

Family

ID=12593460

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4090380A Pending JPS56137650A (en) 1980-03-28 1980-03-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56137650A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814290A (en) * 1987-10-30 1989-03-21 International Business Machines Corporation Method for providing increased dopant concentration in selected regions of semiconductor devices
US4829019A (en) * 1987-05-12 1989-05-09 Texas Instruments Incorporated Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment
US5122473A (en) * 1989-10-24 1992-06-16 Sgs-Thomson Microelectronics S.R.L. Process for forming a field isolation structure and gate structures in integrated misfet devices
US5208181A (en) * 1992-08-17 1993-05-04 Chartered Semiconductor Manufacturing Pte Ltd. Locos isolation scheme for small geometry or high voltage circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5342560A (en) * 1976-09-29 1978-04-18 Matsushita Electric Ind Co Ltd Production of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5342560A (en) * 1976-09-29 1978-04-18 Matsushita Electric Ind Co Ltd Production of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4829019A (en) * 1987-05-12 1989-05-09 Texas Instruments Incorporated Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment
US4814290A (en) * 1987-10-30 1989-03-21 International Business Machines Corporation Method for providing increased dopant concentration in selected regions of semiconductor devices
US5122473A (en) * 1989-10-24 1992-06-16 Sgs-Thomson Microelectronics S.R.L. Process for forming a field isolation structure and gate structures in integrated misfet devices
US5208181A (en) * 1992-08-17 1993-05-04 Chartered Semiconductor Manufacturing Pte Ltd. Locos isolation scheme for small geometry or high voltage circuit

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