JPH0542823B2 - - Google Patents
Info
- Publication number
- JPH0542823B2 JPH0542823B2 JP17859183A JP17859183A JPH0542823B2 JP H0542823 B2 JPH0542823 B2 JP H0542823B2 JP 17859183 A JP17859183 A JP 17859183A JP 17859183 A JP17859183 A JP 17859183A JP H0542823 B2 JPH0542823 B2 JP H0542823B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- output circuit
- circuit area
- area
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 description 6
- 238000003491 array Methods 0.000 description 5
- 238000006073 displacement reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17859183A JPS6070742A (ja) | 1983-09-27 | 1983-09-27 | マスタ・スライス型半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17859183A JPS6070742A (ja) | 1983-09-27 | 1983-09-27 | マスタ・スライス型半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6070742A JPS6070742A (ja) | 1985-04-22 |
JPH0542823B2 true JPH0542823B2 (de) | 1993-06-29 |
Family
ID=16051136
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17859183A Granted JPS6070742A (ja) | 1983-09-27 | 1983-09-27 | マスタ・スライス型半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6070742A (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02180049A (ja) * | 1989-01-04 | 1990-07-12 | Nec Corp | 半導体装置 |
US5216280A (en) * | 1989-12-02 | 1993-06-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device having pads at periphery of semiconductor chip |
JPH0327529A (ja) * | 1990-02-23 | 1991-02-05 | Seiko Epson Corp | 半導体集積回路装置 |
US5548135A (en) * | 1995-05-12 | 1996-08-20 | David Sarnoff Research Center, Inc. | Electrostatic discharge protection for an array of macro cells |
JP2006100436A (ja) | 2004-09-28 | 2006-04-13 | Toshiba Corp | 半導体装置 |
-
1983
- 1983-09-27 JP JP17859183A patent/JPS6070742A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6070742A (ja) | 1985-04-22 |
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