JPH0533535B2 - - Google Patents

Info

Publication number
JPH0533535B2
JPH0533535B2 JP60180901A JP18090185A JPH0533535B2 JP H0533535 B2 JPH0533535 B2 JP H0533535B2 JP 60180901 A JP60180901 A JP 60180901A JP 18090185 A JP18090185 A JP 18090185A JP H0533535 B2 JPH0533535 B2 JP H0533535B2
Authority
JP
Japan
Prior art keywords
wiring board
pin
heat sink
wiring
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60180901A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6240749A (ja
Inventor
Akira Konishi
Teruo Wakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
I Pex Inc
Original Assignee
Dai Ichi Seiko Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Ichi Seiko Co Ltd filed Critical Dai Ichi Seiko Co Ltd
Priority to JP60180901A priority Critical patent/JPS6240749A/ja
Priority to EP86108770A priority patent/EP0218796B1/en
Priority to DE8686108770T priority patent/DE3675321D1/de
Priority to US06/880,832 priority patent/US4823234A/en
Priority to KR1019860006161A priority patent/KR870002647A/ko
Priority to CN198686105249A priority patent/CN86105249A/zh
Publication of JPS6240749A publication Critical patent/JPS6240749A/ja
Publication of JPH0533535B2 publication Critical patent/JPH0533535B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP60180901A 1985-08-16 1985-08-16 ピングリツドアレイ Granted JPS6240749A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP60180901A JPS6240749A (ja) 1985-08-16 1985-08-16 ピングリツドアレイ
EP86108770A EP0218796B1 (en) 1985-08-16 1986-06-27 Semiconductor device comprising a plug-in-type package
DE8686108770T DE3675321D1 (de) 1985-08-16 1986-06-27 Halbleiteranordnung mit packung vom steckerstifttyp.
US06/880,832 US4823234A (en) 1985-08-16 1986-07-01 Semiconductor device and its manufacture
KR1019860006161A KR870002647A (ko) 1985-08-16 1986-07-28 반도체장치 및 그 제조방법
CN198686105249A CN86105249A (zh) 1985-08-16 1986-08-16 半导体器件及其制造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60180901A JPS6240749A (ja) 1985-08-16 1985-08-16 ピングリツドアレイ

Publications (2)

Publication Number Publication Date
JPS6240749A JPS6240749A (ja) 1987-02-21
JPH0533535B2 true JPH0533535B2 (enFirst) 1993-05-19

Family

ID=16091288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60180901A Granted JPS6240749A (ja) 1985-08-16 1985-08-16 ピングリツドアレイ

Country Status (1)

Country Link
JP (1) JPS6240749A (enFirst)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62189742A (ja) * 1986-02-14 1987-08-19 Matsushita Electric Works Ltd ピングリツドアレイ
JPS62189743A (ja) * 1986-02-14 1987-08-19 Matsushita Electric Works Ltd 配線回路体
JP2770947B2 (ja) * 1988-02-05 1998-07-02 シチズン時計株式会社 樹脂封止型半導体装置及びその製造方法

Also Published As

Publication number Publication date
JPS6240749A (ja) 1987-02-21

Similar Documents

Publication Publication Date Title
US4618739A (en) Plastic chip carrier package
JP3432982B2 (ja) 表面実装型半導体装置の製造方法
US6900535B2 (en) BGA/LGA with built in heat slug/spreader
US5557150A (en) Overmolded semiconductor package
KR960003766B1 (ko) 플래스틱 핀 그리드 어레이 패키지 제조 방법
US7323767B2 (en) Standoffs for centralizing internals in packaging process
US5241133A (en) Leadless pad array chip carrier
JPH09507344A (ja) ワイヤ・ボンディングの技術に基づくボール・グリッド・アレイの下に浅い空洞を持つパッケージ
US7176062B1 (en) Lead-frame method and assembly for interconnecting circuits within a circuit module
JPH113957A (ja) 薄型パワーテープボールグリッドアレイパッケージ
KR20010014882A (ko) 반도체 장치 및 그 제조 방법
EP0563264B1 (en) Leadless pad array chip carrier
KR19990083251A (ko) 얇은리세스부및두꺼운평면부를갖는반도체칩용패키지및그의제조방법
US6122172A (en) Polymer stud grid array
JP2770947B2 (ja) 樹脂封止型半導体装置及びその製造方法
JP3656861B2 (ja) 半導体集積回路装置及び半導体集積回路装置の製造方法
US6057594A (en) High power dissipating tape ball grid array package
JPH0533535B2 (enFirst)
KR19980068343A (ko) 가요성 회로 기판을 이용한 칩 스케일 반도체 패키지 및 그 제조 방법
JPH08279571A (ja) 半導体装置
JPH0553067B2 (enFirst)
JP3136274B2 (ja) 半導体装置
JPS60254646A (ja) 半導体装置
KR100216063B1 (ko) 메탈 볼 그리드 어레이 패키지
JPH10150065A (ja) チップサイズパッケージ