JPH053142B2 - - Google Patents

Info

Publication number
JPH053142B2
JPH053142B2 JP59181972A JP18197284A JPH053142B2 JP H053142 B2 JPH053142 B2 JP H053142B2 JP 59181972 A JP59181972 A JP 59181972A JP 18197284 A JP18197284 A JP 18197284A JP H053142 B2 JPH053142 B2 JP H053142B2
Authority
JP
Japan
Prior art keywords
wiring
chip
semiconductor device
package
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59181972A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6159862A (ja
Inventor
Junji Sakurai
Ryoichi Mukai
Tetsuo Izawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59181972A priority Critical patent/JPS6159862A/ja
Publication of JPS6159862A publication Critical patent/JPS6159862A/ja
Publication of JPH053142B2 publication Critical patent/JPH053142B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10W90/00—
    • H10W72/00—
    • H10W72/01—
    • H10W72/834—
    • H10W90/20—
    • H10W90/231—
    • H10W90/291—
    • H10W90/732—
    • H10W90/754—

Landscapes

  • Wire Bonding (AREA)
JP59181972A 1984-08-31 1984-08-31 半導体装置 Granted JPS6159862A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59181972A JPS6159862A (ja) 1984-08-31 1984-08-31 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59181972A JPS6159862A (ja) 1984-08-31 1984-08-31 半導体装置

Publications (2)

Publication Number Publication Date
JPS6159862A JPS6159862A (ja) 1986-03-27
JPH053142B2 true JPH053142B2 (enExample) 1993-01-14

Family

ID=16110083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59181972A Granted JPS6159862A (ja) 1984-08-31 1984-08-31 半導体装置

Country Status (1)

Country Link
JP (1) JPS6159862A (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4956695A (en) * 1989-05-12 1990-09-11 Rockwell International Corporation Three-dimensional packaging of focal plane assemblies using ceramic spacers
JPH04179263A (ja) * 1990-11-14 1992-06-25 Hitachi Ltd 樹脂封止型半導体装置とその製造方法
AU4242693A (en) * 1992-05-11 1993-12-13 Nchip, Inc. Stacked devices for multichip modules
JP3398721B2 (ja) 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
KR20010064907A (ko) 1999-12-20 2001-07-11 마이클 디. 오브라이언 와이어본딩 방법 및 이를 이용한 반도체패키지
US6452278B1 (en) 2000-06-30 2002-09-17 Amkor Technology, Inc. Low profile package for plural semiconductor dies
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US9466545B1 (en) * 2007-02-21 2016-10-11 Amkor Technology, Inc. Semiconductor package in package

Also Published As

Publication number Publication date
JPS6159862A (ja) 1986-03-27

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