JPH053142B2 - - Google Patents
Info
- Publication number
- JPH053142B2 JPH053142B2 JP59181972A JP18197284A JPH053142B2 JP H053142 B2 JPH053142 B2 JP H053142B2 JP 59181972 A JP59181972 A JP 59181972A JP 18197284 A JP18197284 A JP 18197284A JP H053142 B2 JPH053142 B2 JP H053142B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- chip
- semiconductor device
- package
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 35
- 230000002093 peripheral effect Effects 0.000 claims 1
- 239000002184 metal Substances 0.000 description 11
- 230000010354 integration Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000004033 plastic Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 230000035936 sexual power Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/63—Connectors not provided for in any of the groups H01L24/10 - H01L24/50 and subgroups; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06551—Conductive connections on the side of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の集積度を向上し製造歩留
りを向上する改良に関する。特に、複数の半導体
装置チツプを積層してなす、いわゆる、チツプオ
ンチツプ型構成を可能とする改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvements that improve the degree of integration of semiconductor devices and improve manufacturing yields. In particular, the present invention relates to improvements that enable a so-called chip-on-chip type structure in which a plurality of semiconductor device chips are stacked.
半導体装置において、集積度を向上し、さら
に、製造歩留りを向上するために、複数の半導体
装置チツプを積層して単一の半導体装置を構成す
るチツプオンチツプ型ICと呼ばれる半導体装置
がある。これは、半導体装置チツプを積層するこ
とにより単位平面積当りの素子数を増大して集積
度を向上するとともに、単一の半導体装置を複数
のチツプに分割して上記単一の半導体装置当りの
不良品発生確率を減少し製造歩留りを向上するも
のである。
In semiconductor devices, there is a semiconductor device called a chip-on-chip type IC in which a plurality of semiconductor device chips are stacked to form a single semiconductor device in order to improve the degree of integration and further improve manufacturing yield. This is achieved by stacking semiconductor device chips to increase the number of elements per unit area and improving the degree of integration, and by dividing a single semiconductor device into multiple chips. This reduces the probability of defective products and improves manufacturing yield.
複数の半導体装置チツプを使用して単一の半導
体装置を構成する場合、各チツプ相互間及び上記
単一の半導体装置全体としての外部引き出し端子
を設けることが必要である。かゝる接続を実現す
るために従来使用されている手段は、チツプ上に
ボンデイングパツドを設け、これに接続されるボ
ンデイングワイヤを使用してなすことである。
When constructing a single semiconductor device using a plurality of semiconductor device chips, it is necessary to provide external lead-out terminals between each chip and for the single semiconductor device as a whole. The means conventionally used to achieve such connections is through the use of bonding pads on the chip and bonding wires connected thereto.
たゞ、相互に積層される複数のチツプにボンデ
イングパツドを設けることとすると、例えば、第
７図に示すように、積層されるチツプ１の平面積
を、上段に行くにしたがつて減少する等の措置を
講ぜざるを得ず、十分に集積度を向上することが
できない。また、ボンデイングワイヤ１０相互間
の短絡を防ぐためにはワイヤボンデイング上の制
限が発生し、特に、外部引き出しボンデイングを
図示するように平面的になすこととすれば、パツ
ケージの面積は大幅に増大することとなり、集積
度の向上はあまり期待しえない。 However, if bonding pads are provided for a plurality of chips that are stacked on each other, for example, as shown in FIG. 7, the planar area of the stacked chips 1 decreases as one goes to the top. As a result, the density cannot be sufficiently increased. In addition, in order to prevent short circuits between the bonding wires 10, there are restrictions on wire bonding, and in particular, if the external bonding is made planar as shown in the figure, the area of the package will increase significantly. Therefore, we cannot expect much improvement in the degree of integration.
以上説明せるとおり、複数の半導体装置チツプ
を積層して単一の半導体装置を構成するチツプオ
ンチツプ型ICにおいては、チツプ相互間及びチ
ツプと外部との接続手段についてさらに改良すべ
き点がある。 As explained above, in a chip-on-chip type IC in which a plurality of semiconductor device chips are stacked to form a single semiconductor device, there are points that need to be further improved in connection means between the chips and between the chips and the outside.
本発明は、チツプ相互間及びチツプと外部との
接続手段に改良を加え、集積度が十分に向上し、
製造歩留りも十分に改良されたチツプオンチツプ
構造の半導体装置を提供するものであり、その手
段は、チツプの外周近傍に集端を有する第１の配
線が設けられた半導体装置チツプが複数個積層さ
れ、該半導体装置チツプの積層体はパツケージの
中に収容され、前記半導体装置チツプのそれぞれ
の側壁は前記パツケージの内面の対応する領域と
密着しており、前記パツケージには前記第１の配
線と接触するように第２の配線が設けられてなる
半導体装置にある。上記の構成において、各チツ
プ間に絶縁物層を介在させることは絶縁耐力を増
大し信頼性を向上するために有効である。また、
上記いづれの構成においても、第１の配線と第２
の配線のいづれかが、第２図に示すように、チツ
プとパツケージとの接合面すなわちチツプの側壁
より突出して凸状をなし他方がこれに対応するよ
うに凹状をなすと配線間の接続が確実になり、信
頼性向上に有効である。上記第１、第２の構成に
おいて、第１及び第２の配線が、第３図に示すよ
うに、チツプ側壁の１部分上まで延在するように
なすと配線間の接続が確実になり信頼性向上に有
効である。
The present invention improves the connection means between chips and between chips and the outside, and sufficiently increases the degree of integration.
The purpose of the present invention is to provide a semiconductor device having a chip-on-chip structure in which the manufacturing yield is sufficiently improved, and its means include stacking a plurality of semiconductor device chips each having a first wiring having a converging end near the outer periphery of the chip; The stack of semiconductor device chips is housed in a package, each side wall of the semiconductor device chip is in close contact with a corresponding area of the inner surface of the package, and the package is in contact with the first wiring. A semiconductor device is provided with a second wiring as shown in FIG. In the above structure, interposing an insulating layer between each chip is effective for increasing dielectric strength and improving reliability. Also,
In any of the above configurations, the first wiring and the second
As shown in Figure 2, if one of the wirings has a convex shape protruding from the joint surface of the chip and the package, that is, the side wall of the chip, and the other has a corresponding concave shape, the connection between the wirings will be ensured. This is effective in improving reliability. In the first and second configurations described above, if the first and second wirings extend above a portion of the chip sidewall as shown in FIG. 3, the connection between the wirings becomes reliable and reliable. It is effective in improving sexual performance.
チツプオンチツプ型ICを実現する上での妨げ
となる主たる要素は、その接続にボンデイングワ
イヤを利用しようとする点にあるから、本発明に
おいては、接続にボンデイングワイヤを使用する
ことを止め、厚さ10μm程度の金属層の先端部を
接触させて接続を実現したものである。そして、
この厚さ10μm程度の金属層を正確に接触させる
ために、半導体装置チツプをその外周が密着する
パツケージに収容し、このパツケージ内に、その
先端が露出している他方の配線を埋め込こんでお
き、半導体装置チツプの積層体をパツケージ中に
正確に組み込み上記の金属層同志を互いに接触さ
せて確実な接続を実現したものである。
The main obstacle to realizing a chip-on-chip type IC is the use of bonding wires for connection. Therefore, in the present invention, the use of bonding wires for connection is stopped, and a thickness of 10 μm is used. The connection is achieved by bringing the tips of the metal layers into contact. and,
In order to accurately contact this metal layer with a thickness of about 10 μm, the semiconductor device chip is housed in a package whose outer periphery is in close contact, and the other wiring whose tip is exposed is embedded within this package. Then, a stack of semiconductor device chips is accurately assembled into a package, and the metal layers mentioned above are brought into contact with each other to achieve a reliable connection.
以下、図面を参照しつゝ、本発明の一実施例に
係る半導体装置についてさらに説明する。
Hereinafter, a semiconductor device according to an embodiment of the present invention will be further described with reference to the drawings.
第４図参照
半導体装置チツプ製造工程の最終段階におい
て、それまでの工程で形成されている電極・配線
のうちの所望の電極・配線２に接続して、チツプ
１の側壁３の１部上まで延在するように厚さ
10μm程度の金属層よりなる第１の配線４をチツ
プ１上に形成する。この工程はリフトオフ法等を
使用すれば容易に実行しうる。Refer to Figure 4. At the final stage of the semiconductor device chip manufacturing process, a desired electrode/wiring 2 of the electrodes/wirings formed in the previous processes is connected to a part of the side wall 3 of the chip 1. Thickness to extend
A first wiring 4 made of a metal layer with a thickness of about 10 μm is formed on the chip 1. This step can be easily performed using a lift-off method or the like.
第５図参照
上記のチツプ１と絶縁板５とを交互に積層して
接着する。絶縁板５はセラミツク材であつてもプ
ラスチツク材であつてもさしつかえない。Refer to FIG. 5. The above chips 1 and insulating plates 5 are alternately laminated and bonded. The insulating plate 5 may be made of ceramic or plastic.
第６図参照
第１図の配線４に対応する位置に露出部６を有
する埋め込み金属層よりなる第２の配線７を有
し、半導体装置チツプ積層体の外形に対応する形
状の空洞８を有するパツケージ９を成形する。パ
ツケージ９は、セラミツク材であつても耐熱性プ
ラスチツク材であつてもよいが、埋め込み金属層
よりなる第２の配線を設ける必要があるので、セ
ラミツク材の場合は板状のグリーンシート上に所
望の金属パターンを形成した後このグリーンシー
トを複数枚組み合わせて焼成することが現実的で
あり、プラスチツク材の場合はプラスチツクシー
ト上に所望の金属パターンを形成した後、このプ
ラスチツクシートを複数枚貼り合わせることが現
実的である。See FIG. 6. It has a second wiring 7 made of a buried metal layer having an exposed portion 6 at a position corresponding to the wiring 4 in FIG. A package 9 is molded. The package 9 may be made of ceramic material or heat-resistant plastic material, but since it is necessary to provide a second wiring made of an embedded metal layer, if the package 9 is made of ceramic material, the desired wiring is placed on a plate-shaped green sheet. After forming a metal pattern, it is practical to combine and fire multiple green sheets.In the case of plastic materials, after forming a desired metal pattern on a plastic sheet, multiple sheets of this plastic are bonded together. That is realistic.
第１図、第３図参照
セラミツクパツケージの場合は、パツケージ９
を200度Ｃ程度に加熱して空洞８の１辺の長さを
10〜15μm膨脹させておき、上記の半導体装置積
層体を真空チヤツク等を使用して持ち上げ、上記
の膨脹した空洞８中に挿入し、第１の配線４と第
２の配線７の露出部６とを接触させ、パツケージ
９を徐冷する。See Figures 1 and 3. For ceramic packages, package 9
Heat it to about 200 degrees C and measure the length of one side of cavity 8.
After expanding by 10 to 15 μm, lift the semiconductor device stack using a vacuum chuck or the like, insert it into the expanded cavity 8, and remove the exposed portions 6 of the first wiring 4 and the second wiring 7. The package 9 is slowly cooled by contacting with the
プラスチツクパツケージの場合は、軟化はしな
いが十分に膨脹はする程度でプラスチツク材料に
よつて決まる温度に加熱して空洞８の１辺の長さ
を20μm膨脹させておき、上記の半導体装置積層
体を真空チヤツク等を使用して持ち上げ、上記の
膨脹した空洞８中に挿入し、第１の配線４と第２
の配線７の露出部６とを接触させ、パツケージ９
を徐冷する。 In the case of a plastic package, the above semiconductor device stack is heated to a temperature determined by the plastic material so that it does not soften but expands sufficiently to expand the length of one side of the cavity 8 by 20 μm. Lift it using a vacuum chuck or the like, insert it into the expanded cavity 8, and connect the first wiring 4 and the second wiring.
The exposed portion 6 of the wiring 7 is brought into contact with the package 9.
Cool slowly.
第２図参照
第１の配線２と第２の配線４との関係位置は、
その一方がチツプ１の側面３とパツケージ９の接
合面すなわちチツプの側壁から突出して凸状をな
しているか、または、その逆に凹状をなしてお
り、相互に嵌合しうるようにされていてもよい。See Figure 2 The relative position between the first wiring 2 and the second wiring 4 is as follows:
One of them has a convex shape protruding from the joint surface between the side surface 3 of the chip 1 and the package 9, that is, the side wall of the chip, or, conversely, has a concave shape so that they can fit together. Good too.
この嵌合構造の第１と第２の配線は、チツプと
パツケージとのうちの一方を、配線を残してエツ
チバツクし、他方は配線のみをエツチすることに
より容易に形成しうる。すなわち、まづ、チツプ
１上に突出した配線４を形成するには、チツプ１
上に第１の配線４を通常の手法により形成した
後、この第１の配線４の先端はエツチせず、チツ
プ１の側面のみをエツチバツクすればよい。ま
た、その先端がパツケージ９内に設けられた凹部
内にある配線７を形成刷るには、パツケージ９中
に埋め込み金属層として配線７を形成した後、金
属層のみをわづかにエツチすればよい。 The first and second wires of this mating structure can be easily formed by etching back one of the chip and the package, leaving the wires behind, and etching only the wires on the other. That is, first, in order to form the wiring 4 protruding on the chip 1,
After forming the first wiring 4 thereon by a conventional method, only the side surface of the chip 1 needs to be etched back without etching the tip of the first wiring 4. Furthermore, in order to form the wiring 7 whose tip is located in the recess provided in the package 9, it is sufficient to form the wiring 7 as a metal layer buried in the package 9 and then slightly etch only the metal layer. .
以上説明せるとおり、本発明によれば、複数の
半導体装置チツプが相互に積層され、この積層体
はパツケージ中に収容され、この積層体の外周は
パツケージの内面に密着し、各チツプの表面周辺
部と、パツケージの対応する領域とには、金属層
よりなる第１と第２の配線が設けられており、チ
ツプ積層体がパツケージ中に組み込まれた状態に
おいて、第１と第２の配線が接触圧着されて接続
を実現しているので、上段に行くにしたがつてチ
ツプ面積を減少させる必要はなく、すべてのチツ
プは十分大きな面積を有することができ、ボンデ
イングワイヤを平面的に張る必要がないためパツ
ケージの平面も小さくてよく、十分に集積度が高
くなり、期待しうる機能を十分に発揮しうるチツ
プオンチツプ構造の半導体装置を提供することが
できる。なお、動作時にはチツプに設けられた要
素が発熱してチツプはいくらか膨脹するが、第１
と第２の配線はさらに圧着されることになり、接
続はさらに良好になる。さらに、かゝる構造にお
いては、その組み立ての機械化が容易であるとい
う利点もある。
As explained above, according to the present invention, a plurality of semiconductor device chips are stacked on each other, this stacked body is housed in a package, the outer periphery of this stacked body is in close contact with the inner surface of the package, and the periphery of the surface of each chip is First and second wirings made of a metal layer are provided in the corresponding area of the package, and when the chip stack is assembled in the package, the first and second wirings are connected to each other. Since the connection is achieved by contact crimping, there is no need to reduce the chip area as you move up the stack, and all chips can have a sufficiently large area, so there is no need to stretch the bonding wire flat. Therefore, the plane of the package can be small, and a semiconductor device with a chip-on-chip structure can be provided which has a sufficiently high degree of integration and can fully exhibit the expected functions. During operation, the elements provided on the chip generate heat and the chip expands to some extent, but the first
The second wiring is further crimped, and the connection becomes even better. Furthermore, such a structure has the advantage that its assembly can be easily mechanized.
第１図は、本発明の一実施例に係る半導体装置
の断面図である。第２図、第３図は、本発明の要
旨に係る第１と第２の配線の構造と接触状態を示
す断面図である。第４図、第５図、第６図は、本
発明の一実施例に係る半導体装置の主要製造工程
完了後の断面図である。第７図は従来技術に係る
チツプオンチツプ型ICの断面図である。
１……チツプ、２……電極・配線、３……チツ
プの側面、４……第１の配線、５……絶縁板、６
……露出部、７……第２の配線、８……空洞、９
……パツケージ、１０……ボンデイングワイヤ。
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. FIGS. 2 and 3 are cross-sectional views showing the structure and contact state of first and second wiring lines according to the gist of the present invention. FIG. 4, FIG. 5, and FIG. 6 are cross-sectional views of a semiconductor device according to an embodiment of the present invention after completion of the main manufacturing steps. FIG. 7 is a sectional view of a chip-on-chip type IC according to the prior art. DESCRIPTION OF SYMBOLS 1... Chip, 2... Electrode/wiring, 3... Side surface of chip, 4... First wiring, 5... Insulating plate, 6
...Exposed part, 7...Second wiring, 8...Cavity, 9
...Package, 10...Bonding wire.
Claims (1)
が設けられた半導体装置チツプが複数個積層さ
れ、該半導体装置チツプの積層体はパツケージの
中に収容され、前記半導体装置チツプのそれぞれ
の側壁は前記パツケージの内面の対応する領域と
密着しており、前記パツケージには前記第１の配
線と接触するように第２の配線が設けられてなる
ことを特徴とする半導体装置。 ２ 前記半導体装置チツプ相互間には絶縁物層が
介在してなることを特徴とする特許請求の範囲第
１項記載の半導体装置。 ３ 前記第１の配線と前記第２の配線とのいづれ
かは、前記チツプと前記パツケージとの接合面よ
り突出して凸状をなし、他方は凹状をなすことを
特徴とする特許請求の範囲第１項または第２項記
載の半導体装置。 ４ 前記第１の配線と第２の配線とは前記チツプ
の側壁の１部分上まで延在してなることを特徴と
する特許請求の範囲第１項または第２項記載の半
導体装置。[Scope of Claims] 1. A plurality of semiconductor device chips each having a first wiring having a peripheral end near the outer periphery of the chip are stacked, the stack of semiconductor device chips is housed in a package, and the semiconductor device chips are stacked together. Each side wall of the device chip is in close contact with a corresponding area of the inner surface of the package, and the package is provided with a second wiring so as to be in contact with the first wiring. Device. 2. The semiconductor device according to claim 1, wherein an insulating layer is interposed between the semiconductor device chips. 3. Claim 1, characterized in that one of the first wiring and the second wiring has a convex shape protruding from the bonding surface of the chip and the package, and the other has a concave shape. 3. The semiconductor device according to item 1 or 2. 4. The semiconductor device according to claim 1 or 2, wherein the first wiring and the second wiring extend above a portion of a side wall of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59181972A JPS6159862A (en) | 1984-08-31 | 1984-08-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59181972A JPS6159862A (en) | 1984-08-31 | 1984-08-31 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6159862A JPS6159862A (en) | 1986-03-27 |
| JPH053142B2 true JPH053142B2 (en) | 1993-01-14 |
Family
ID=16110083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59181972A Granted JPS6159862A (en) | 1984-08-31 | 1984-08-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6159862A (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4956695A (en) * | 1989-05-12 | 1990-09-11 | Rockwell International Corporation | Three-dimensional packaging of focal plane assemblies using ceramic spacers |
| JPH04179263A (en) * | 1990-11-14 | 1992-06-25 | Hitachi Ltd | Resin-sealed semiconductor device, and manufacture thereof |
| AU4242693A (en) * | 1992-05-11 | 1993-12-13 | Nchip, Inc. | Stacked devices for multichip modules |
| JP3398721B2 (en) | 1999-05-20 | 2003-04-21 | アムコー テクノロジー コリア インコーポレーティド | Semiconductor package and manufacturing method thereof |
| KR20010064907A (en) | 1999-12-20 | 2001-07-11 | 마이클 디. 오브라이언 | wire bonding method and semiconductor package using it |
| US6452278B1 (en) | 2000-06-30 | 2002-09-17 | Amkor Technology, Inc. | Low profile package for plural semiconductor dies |
| US6472758B1 (en) | 2000-07-20 | 2002-10-29 | Amkor Technology, Inc. | Semiconductor package including stacked semiconductor dies and bond wires |
| US6577013B1 (en) | 2000-09-05 | 2003-06-10 | Amkor Technology, Inc. | Chip size semiconductor packages with stacked dies |
| US6552416B1 (en) | 2000-09-08 | 2003-04-22 | Amkor Technology, Inc. | Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring |
| US6340846B1 (en) | 2000-12-06 | 2002-01-22 | Amkor Technology, Inc. | Making semiconductor packages with stacked dies and reinforced wire bonds |
| US9466545B1 (en) * | 2007-02-21 | 2016-10-11 | Amkor Technology, Inc. | Semiconductor package in package |
-
1984
- 1984-08-31 JP JP59181972A patent/JPS6159862A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6159862A (en) | 1986-03-27 |
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