JPS63289844A - Bump electrode of semiconductor device - Google Patents
Bump electrode of semiconductor deviceInfo
- Publication number
- JPS63289844A JPS63289844A JP62124509A JP12450987A JPS63289844A JP S63289844 A JPS63289844 A JP S63289844A JP 62124509 A JP62124509 A JP 62124509A JP 12450987 A JP12450987 A JP 12450987A JP S63289844 A JPS63289844 A JP S63289844A
- Authority
- JP
- Japan
- Prior art keywords
- bump electrode
- bump
- semiconductor device
- height
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 239000004020 conductor Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000002131 composite material Substances 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005489 elastic deformation Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1413—Square or rectangular array
- H01L2224/14133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置を配線基板上に実装するために設け
られるバンプ電極であって、半導体装置の基板面から突
出して複数個設けられ配線基板上の対応する導体にそれ
ぞれ押し付けられた状態で導電的に接合されるものに関
する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a bump electrode provided for mounting a semiconductor device on a wiring board, in which a plurality of bump electrodes are provided protruding from the substrate surface of the semiconductor device. It relates to something that is electrically connected to the corresponding conductor above in a pressed state.
よく知られているように集積回路等の半導体装置を配線
基板に実装する最も普通の手段は、半導体装置をＤＩＰ
方式などのパンケージに一旦収納し、リードをプリント
配線基板のスルーホールに挿入した上で配線基板上の導
体とはんだ付けすることである。しかし、この実装構造
では実装密度を高める上で不利であるため、半導体装置
をチップのままで例えばセラミックの配線基板上に直接
に取り付け、半導体装置と配＆！基板の導体との接続を
ボンディング線ですることも広く行なわれている。この
実装構造では前の構造よりも実装密度をかなり高めるこ
とができるが、なお配線基板のチップを取り付けた場所
のほかにそのまわりにもボンディング線用の場所が必要
なので、配線基板のもつ面積を充分有効に利用している
とはいい難い、また、ボンディング作業用の工具のつご
うでボンディング線の相互間隔を２００−程度以上取ら
なければならないので、１チツプあたりの接続点数に上
限があり、接続点数が増えるとチップを２個以上に分割
してやらなければならないことになり、このために実装
密度がさらに下がってしまう。As is well known, the most common means of mounting semiconductor devices such as integrated circuits on wiring boards is DIP.
The method is to temporarily store the lead in a pan cage such as a printed wiring board, insert the lead into the through hole of the printed wiring board, and then solder it to the conductor on the wiring board. However, this mounting structure is disadvantageous in terms of increasing the packaging density, so the semiconductor device is directly mounted as a chip on, for example, a ceramic wiring board, and the semiconductor device and the wiring are connected. It is also widely used to connect the conductors of the substrate with bonding wires. Although this mounting structure can significantly increase the packaging density compared to the previous structure, it still requires space for bonding wires in addition to the area where the chip is mounted on the wiring board, so it reduces the area of the wiring board. It cannot be said that they are used effectively enough, and since the bonding wires must be spaced at least 200 mm apart due to the use of tools for bonding work, there is an upper limit to the number of connection points per chip. As the number of connection points increases, the chip must be divided into two or more pieces, which further reduces packaging density.
半導体基板から突出したバンプ電極を備えるいわゆるフ
リップチップは、バンプ電極を配線基板上の導体とフェ
ースダウン式に直接に接合するので、チップのもつ面積
内で接続をすませることができ、かつバンプ電極の相互
間隔も１００−以下に減らせるので、現在の技術でも１
チツプあたり１００〜２００に接続点数を増やすことが
できる。第６図はかかる実装構造の概要を示すものであ
る。The so-called flip chip, which has bump electrodes protruding from the semiconductor substrate, connects the bump electrodes directly to the conductors on the wiring board in a face-down manner, making it possible to complete the connection within the area of the chip. Since the mutual spacing can be reduced to less than 100, even with current technology
The number of connection points can be increased to 100-200 per chip. FIG. 6 shows an outline of such a mounting structure.
図の上半分が半導体装１であって、その基板１０から図
の下方に向けて突出するバンプ電極２０が設けられてい
る。バンプ電極２０は例えば金やはんだであって、ふつ
うは円形や細長の方形の断面をもち、その図の幅Ｗが数
十−程度で高さｈが２０ｆ１前後のものである。このバ
ンプ電極２０が接続される相手は図の下半分のふつうは
セラミックの配線基板３０であって、その上の導体３１
には例えばニッケルめっきが施されている。接続に当た
っては半導体装置はそのバンプ電極を下にして図示のよ
うに配ｖＡ基板に乗せた上で、加圧かつ加熱下でバンプ
電極２０を導体３１と接合する。金バンプ電極の場合の
加熱は４５０℃前後であって、加圧は図の左右のバンプ
電極に見られるようにその先端がやや膨出する程度にな
され、これによってバンプ電極の金と導体上のニッケル
とが合金化して強い導電接合が形成される。この接合方
法はもちろんバンプ電極の材料によって異なり、最近で
は紫外線硬化樹脂を利用した接合方式も開発されている
。The upper half of the figure is a semiconductor device 1, and bump electrodes 20 are provided that protrude downward from the substrate 10 of the figure. The bump electrodes 20 are made of gold or solder, for example, and usually have a circular or elongated rectangular cross section, with a width W of about several tens of meters and a height h of about 20 f1. This bump electrode 20 is connected to a wiring board 30, usually made of ceramic, in the lower half of the figure, and a conductor 31 thereon.
For example, it is plated with nickel. For connection, the semiconductor device is placed on the wiring board A as shown in the figure with its bump electrode facing down, and the bump electrode 20 is bonded to the conductor 31 under pressure and heat. In the case of gold bump electrodes, the heating is around 450°C, and the pressure is applied to such an extent that the tips of the bump electrodes swell slightly, as seen in the bump electrodes on the left and right sides of the figure. It alloys with nickel to form a strong conductive bond. This bonding method naturally depends on the material of the bump electrode, and recently a bonding method using ultraviolet curing resin has been developed.
前述のフリップチップにおけるバンプ電極を介する接続
方式は実装密度が最も高く接続点数も大きくできる特長
を有するが、半導体装置のバンプ電極と配線基板の導体
との接合が不充分であると、接続不良が生じたり使用中
に接触不良になるなどの問題が起きやすい、この接合が
不良ないしは不充分になる最大の原因は、第６図のバン
プ電８ｉ２０の高さｈにばらつきが生じやすいことであ
って、図の中央のバンプ電極のように高さの低いものが
あって接合後にも導体との隙間δが残るようであればも
ちろん接続不良が発生する。また配線基板の導体の表面
も必ずしも均一に揃っているとはいい切れない、バンプ
電極はその高さが前述のように２０１ｒｍと比較的大き
いのでふつうは電解めっき法で成長されるが、現在の最
高の電解めっき技術によっても高さ寸法には数％のばら
つきが発生することは不可避で、高さ寸法のばらつきを
±１μ烏以内にすることは実際上困難である。つまり、
バンプ電極の高さにはその最大、！！に小値間で約２μ
の差が出るわけで、この高さ寸法のばらつきを吸収して
充分な接合を遂げる一つの方法は、加熱下でバンプ電極
２０が２Ｘｌ１以上沈むように半導体基板１０を強く配
線基板３０に聞けて加圧してやることである。The above-mentioned connection method using bump electrodes in flip chips has the advantage of having the highest packaging density and the ability to increase the number of connection points, but if the bonding between the bump electrodes of the semiconductor device and the conductor of the wiring board is insufficient, connection failures may occur. The biggest cause of poor or insufficient bonding, which tends to cause problems such as poor contact during use, is that the height h of the bump electrode 8i20 shown in Fig. 6 tends to vary. If there is a bump electrode with a low height, such as the bump electrode in the center of the figure, and a gap δ between the conductor and the conductor remains even after bonding, a connection failure will of course occur. Also, the surface of the conductor on the wiring board is not necessarily uniform, and the height of the bump electrode is relatively large at 201 rm as mentioned above, so it is usually grown by electrolytic plating, but the current Even with the best electrolytic plating technology, it is inevitable that the height dimension will vary by several percent, and it is practically difficult to reduce the height variation to within ±1 μm. In other words,
The height of the bump electrode is its maximum! ! Approximately 2μ between small values
Therefore, one method to absorb this variation in height dimension and achieve sufficient bonding is to press the semiconductor substrate 10 strongly against the wiring board 30 so that the bump electrode 20 sinks by 2Xl1 or more under heating. It is a matter of pressure.
しかし、容易に電解されるように、このいわば強圧法は
微妙な特性をもつ半導体装置にとって望ましい手段では
なく、またチップあたりの接続点数つまりバンプ電極の
数が２００個以上にもなると強圧だけではバンプ電極間
の高さの差を吸収することかむつかしくなって来る。チ
ップのサイズは高々Ｉｏｔｍ角程度の小さなものである
が、バンプ電極数が数百にもなるとそのすべてに均一な
加圧力を掛けることが非常に困難になるからである。However, this so-called strong pressure method is not a desirable method for semiconductor devices with delicate characteristics, as electrolysis is easily carried out, and when the number of connection points per chip, that is, the number of bump electrodes, exceeds 200, strong pressure alone is not enough to remove bumps. It becomes difficult to absorb the difference in height between the electrodes. The size of the chip is as small as Iotm square at most, but when the number of bump electrodes increases to several hundreds, it becomes extremely difficult to apply uniform pressing force to all of them.
本発明にかかる現状に立脚して、バンプ電極の高さ寸法
にばらつきがあっても大きな加圧力を加える要なく確実
にバンプ電極を配線基板上の導体に接合できるようにす
ることを目的ないしは課題とする。Based on the current status of the present invention, an object or problem is to enable a bump electrode to be reliably joined to a conductor on a wiring board without the need to apply a large pressing force even if there is variation in the height dimension of the bump electrode. shall be.
この目的は本発明により、バンプ電極の半導体基板面に
平行な方向の断面形状におけるバンプ電極がもつ厚みを
バンプ電極の半導体基板面に垂直な方向の高さ寸法より
も小にすることにより達成される。This object is achieved according to the present invention by making the thickness of the bump electrode in the cross-sectional shape of the bump electrode in the direction parallel to the semiconductor substrate surface smaller than the height dimension of the bump electrode in the direction perpendicular to the semiconductor substrate surface. Ru.
上記の構成にいうバンプ電極の断面形状は前述のように
ふつうは円形や細長の方形であって、その断面の外形輪
郭を示す寸法は数十−程度でふつうは２０Ｄ前後のバン
プ電極の高さよりも大きい。As mentioned above, the cross-sectional shape of the bump electrode in the above configuration is usually a circle or an elongated rectangle, and the dimension indicating the outline of the cross section is about several tens of meters, and is usually about 20D higher than the height of the bump electrode. It's also big.
しかし、本発明ではバンプ電極がこの断面形状において
もつ厚みを半導体装置の高さより小に選定する。このた
めには、例えばバンプ電極を筒状体に形成してその筒の
壁の厚みを薄くしてやればよい、あるいはバンプ電極を
複合構造にしてその断面を複数個の断面部分に分割し、
各断面部分の厚みを薄くすることができる。このように
バンプ電極の実賞的な厚みをその高さより小とすること
により、バンプ電極を配線基板の導体に通常の加圧力で
押し付けたとき、バンプ電極は容易に変形して半導体装
置の高さのばらつきを吸収する。このバンプ電極の変形
は複合した形で生じうる。まずバンプ電極の導体との接
触面付近ではバンプ電極の厚みの広がり変形が永久変形
の形で生じる。つぎに加圧力によってバンプ電極の高さ
寸法の永久変形が生じる。さらに、バンプ電極の断面形
状によっても異なるがバンプ電極の撓みの弾性変形ない
しは永久変形が生じる。バンプ電極にこのような永久変
形ないしは一時的な弾性変形を有効に発生させて、その
高さ寸法のばらつきを完全に吸収しながら良好な導電接
合を得るには、バンプ電極が電解めっきにより成長され
たものである場合、その厚みを１０〜３０−程度量も望
ましくは２０−前後にするのがよい。However, in the present invention, the thickness of the bump electrode in this cross-sectional shape is selected to be smaller than the height of the semiconductor device. For this purpose, for example, the bump electrode may be formed into a cylindrical body and the thickness of the wall of the cylinder may be made thin, or the bump electrode may be made into a composite structure and its cross section may be divided into a plurality of cross-sectional parts.
The thickness of each cross-sectional portion can be reduced. In this way, by making the practical thickness of the bump electrode smaller than its height, when the bump electrode is pressed against the conductor of the wiring board with normal pressing force, the bump electrode is easily deformed and the height of the semiconductor device is increased. Absorbs variations in height. This deformation of the bump electrode can occur in a complex manner. First, near the contact surface of the bump electrode with the conductor, the thickness of the bump electrode is expanded and deformed in the form of permanent deformation. Next, the height of the bump electrode is permanently deformed by the applied force. Further, elastic deformation or permanent deformation occurs when the bump electrode is bent, although this varies depending on the cross-sectional shape of the bump electrode. In order to effectively generate such permanent deformation or temporary elastic deformation in the bump electrode and obtain a good conductive bond while completely absorbing variations in the height dimension, the bump electrode is grown by electrolytic plating. In the case where the material has a thickness of about 10 to 30, the thickness is desirably about 20 to about 20.
以上のように本発明の構成によれば、半導体装置の配線
基板への実装時に通常の加圧力でバンプ電極を導体に押
し付けた際、バンプ電極は容易に変形してその高さのば
らつきを吸収しながら導体に導電接合され、これによっ
て前述の課題が解決される。As described above, according to the configuration of the present invention, when a bump electrode is pressed against a conductor with a normal pressure when mounting a semiconductor device on a wiring board, the bump electrode easily deforms to absorb variations in height. while being electrically conductively bonded to the conductor, thereby solving the aforementioned problem.
以下、図を参照しながら本発明の詳細な説明する。第１
図はバンプ電極を細長な方形の断面をもつ筒状体として
形成した実施例を示すものである。Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figure shows an embodiment in which the bump electrode is formed as a cylindrical body with an elongated rectangular cross section.
第１図ｆａ）は半導体装置の基板１０の周縁部の掻く一
部を示すもので、図では３個のバンプ電極２０が示され
ており、これらのバンプ電極はそのＡ−Ａ矢視断面であ
る同図（′ｂ）かられかるように基板１０の表面に立設
されている。半導体基板１０は基板素体１１ないしはそ
の上に成長されたエピタキシャル層に強いｐ形で拡散さ
れた分離領域に強いｎ形で接続層１２が拡散されたもの
で、この接続層１２が一種の導体となって図示しないト
ランジスタ等の回路要素と接続されている。半導体基板
１０の表面はいわゆる窒化膜等の保護１１１３により覆
われており、この保護膜１３に明けた窓部に接続層１２
と導電接触するようにバンプ電極２０が設けられる。こ
の窓は同図（ａｌに見られるように細長な方形の環にな
っており、バンプ電極を成長させる前に一種の下地層２
０ａとして例えばチタニウムと白金が全体で数千人の厚
みに例えばスパッタ法によって順次被着される。この実
施例におけるバンプ電極２０は例えば金であって、下地
層２０ａの上に電解めっき法によって成長される。ふつ
うこのバンプ電極の高さは１０〜２０μとされるが、本
発明の実施上は２０ｉｎａないしはそれよりやや大きい
目に成長させることが望ましい、前述の保護膜１３に明
けた窓が環状なので、このバンプ電極２０は筒状体とな
り、その壁の厚みｔは前述のように１０〜３０−がよい
が、この実施例の場合は１５〜２０ｎとされる。前述の
ようにバンプ電極２０の高さｈには±１μ程度のばらつ
きが生じ、図では左のバンプ電極が正規の高さｈをもち
、中央のバンプ電極の高さが小で右のバンプ電極の高さ
が大なものとして示されている。Fig. 1 fa) shows a part of the peripheral edge of the substrate 10 of a semiconductor device, and the figure shows three bump electrodes 20, and these bump electrodes are shown in the cross section taken along the line A-A. As shown in FIG. 2('b), it is erected on the surface of the substrate 10. The semiconductor substrate 10 has a connection layer 12 in which strong p-type is diffused into the substrate body 11 or an epitaxial layer grown thereon, and strong n-type is diffused into the isolation region.This connection layer 12 is a kind of conductor. and is connected to circuit elements such as transistors (not shown). The surface of the semiconductor substrate 10 is covered with a protection film 1113 such as a so-called nitride film, and a connection layer 12 is formed in the window formed in the protection film 13.
A bump electrode 20 is provided so as to be in conductive contact with. This window is in the form of an elongated rectangular ring as seen in the same figure (al), and is a type of underlayer layer that is used before growing the bump electrode.
For example, titanium and platinum are sequentially deposited as Oa to a total thickness of several thousand layers by, for example, sputtering. The bump electrode 20 in this embodiment is made of gold, for example, and is grown on the base layer 20a by electrolytic plating. Normally, the height of this bump electrode is 10 to 20 μm, but in the practice of the present invention, it is desirable to grow it to a size of 20 ina or slightly larger. The bump electrode 20 is a cylindrical body, and the wall thickness t is preferably 10 to 30 nm as described above, but in this embodiment, it is 15 to 20 nm. As mentioned above, the height h of the bump electrodes 20 varies by about ±1μ, and in the figure, the left bump electrode has the normal height h, the center bump electrode has a small height, and the right bump electrode has a small height. The height of is shown as being large.
第１図ｔｅｌはこの半導体装置をバンプ電極２０を介し
て配線基板３０上の導体３１に接合した状態を示すもの
で、半導体装置は今までとはその上下が逆になっている
。バンプ電極の接合相手である導体３１は、例えばセラ
ミックの配線基板３０の表面にいわゆるグレーズ材とし
て薄いガラス層を焼き付けて表面を平坦にした後、クロ
ムと金をスパッタ法で合わせて数千λ程度の厚みに被着
して所定のバターニングを行った後、その上に３μ前後
の厚みに金をめっきすることにより形成され、その表面
に薄く錫めっきを施しておくのが望ましい、バターニン
グ２０と導体３１の接合は例えば熱圧着法により行なわ
れ、４５０℃前後の温度下でバンプ電極の先端を図示の
ようにやや広がる程度に導体３１に押し付けることによ
り短時間内に接合が完了する。この接合は２００℃前後
の比較的低温下で超音波を掛けながら圧着することによ
って行なってもよい。FIG. 1 shows a state in which this semiconductor device is bonded to a conductor 31 on a wiring board 30 via a bump electrode 20, and the semiconductor device is upside down from the previous one. The conductor 31, which is the bonding partner of the bump electrode, is made by baking a thin glass layer as a so-called glaze material on the surface of the ceramic wiring board 30 to make the surface flat, and then sputtering chromium and gold together, which is about several thousand λ. Buttering 20 is formed by applying gold to a thickness of about 3 μm and performing predetermined buttering, and then plating gold to a thickness of about 3μ, and it is desirable to apply a thin tin plating to the surface. The bonding between the bump electrode and the conductor 31 is performed, for example, by thermocompression bonding, and the bonding is completed within a short time by pressing the tip of the bump electrode against the conductor 31 at a temperature of around 450° C. to the extent that it is slightly expanded as shown. This bonding may be performed by pressure bonding while applying ultrasonic waves at a relatively low temperature of about 200°C.
接合完了後のバンプ電極２０の形状は同図（ｃ）に見ら
れるように、正規の高さの左のバンプｔ８ｉｌは加圧時
のやや側方に膨出する変形が残った形状をもち、高さが
小であうた中央のバンプ電極は膨出がほとんどなく、高
さが大であった右のバンプ電極は膨出が最も大きい、な
お、接合前後のバンプ電極の平均高さの差は３〜５−で
ある。The shape of the bump electrode 20 after the completion of bonding is as shown in FIG. 3(c). The left bump t8il, which has a normal height, has a shape that bulges slightly laterally when pressurized. The middle bump electrode, which has a small height, has almost no bulge, and the right bump electrode, which has a large height, has the largest bulge.The difference in average height of the bump electrodes before and after bonding is 3 ~5-.
第２図から第５図までは、本発明の実施に適するバンプ
電極の形状例を示すものである。第２図に示されたバン
プ電極２１は円筒形状をもっており前の第１図の実施例
と類似であるが、その上に示されたバンプ電極２１は加
圧時の変形を起こりやすくするため円筒が複数個９図で
は４個に分割された複合構造になっている。第３図に示
されたバンプ電極２３および２４はいずれもこの複合構
造のもので、細長の方形断面の部分バンプ電極が前者で
は３個、後者では２個集まって１個のバンプ電極が構成
されている。これらの複合バンプ電極２２〜２３では、
部分バンプ電極は同時にただし相互に独立に例えば電解
めつきによって成長されるので、それらの高さにばらつ
きが発生しうるが、逆に１個のバンプ電極の内のどれか
の部分バンプ電極が正規の高さをもつ確率が高くなるの
で、配線基板の導体とそのバンプ電極との接合をより確
実に果たしうる利点がある。もちろん、各部分バンプ電
極が加圧時に変化しやすい長所をも備える。なお、第２
図および第３図のいずれにおいてもバンプ電極は二重配
列されており、半導体基板面たりのバンプ電極数が多い
ときこのようにバンプ電極を多重配列にするのがチップ
面積の縮少上有利になる。2 to 5 show examples of shapes of bump electrodes suitable for implementing the present invention. The bump electrode 21 shown in FIG. 2 has a cylindrical shape and is similar to the previous embodiment shown in FIG. In Figure 9, there is a composite structure in which it is divided into four parts. Both of the bump electrodes 23 and 24 shown in FIG. 3 have this composite structure; the former has three partial bump electrodes with a rectangular cross section, and the latter has two partial bump electrodes that make up one bump electrode. ing. In these composite bump electrodes 22 to 23,
Since the partial bump electrodes are grown simultaneously but independently of each other, for example by electrolytic plating, variations in their height may occur, but conversely, if any partial bump electrode among one bump electrode Since the probability of having a height of 1 is increased, there is an advantage that the conductor of the wiring board and its bump electrode can be more reliably bonded. Of course, each partial bump electrode also has the advantage of being easily changed when pressurized. In addition, the second
In both the figure and Fig. 3, the bump electrodes are arranged in double arrangement, and when there are many bump electrodes per semiconductor substrate surface, it is advantageous to arrange the bump electrodes in multiple ways in order to reduce the chip area. Become.
第４図および第５図は第１図の筒状バンプ電極の変形例
を示すもので、第４図のバンプ電極２５は細長いコの字
状断面をもち、第５図のバンプ電極２６はＬ字状断面の
部分バンプ電極を２個組み合わせた複合構造になってい
る。筒状体構造のバンプ電極は加圧時の変形が比較的小
さく、複合バンプ電極は変形が大きいから、これらのバ
ンプ電極２５゜２６は変形の難易に関して両極端の中間
的な特性をもっている。このように、バンプを橿の厚み
の選択のほかにその形状や構成を工夫することにより、
用途に適合した変形の度合いをバンプ電極に持たせるこ
とができる。4 and 5 show modified examples of the cylindrical bump electrode in FIG. 1. The bump electrode 25 in FIG. 4 has an elongated U-shaped cross section, and the bump electrode 26 in FIG. It has a composite structure that combines two partial bump electrodes with a letter-shaped cross section. Since the bump electrode having a cylindrical body structure deforms relatively little when pressurized, and the composite bump electrode deforms largely, these bump electrodes 25 and 26 have characteristics intermediate between the two extremes in terms of difficulty of deformation. In this way, in addition to selecting the thickness of the bump, by devising its shape and configuration,
The bump electrode can be given a degree of deformation that is suitable for the intended use.
以上説明した実施例からもわかるように、本発明は種々
の態様で実施をすることができる。とくにバンプ電極の
厚み、断面形状および複合構造の選択により加圧接合時
のバンプ電極の変形の度合を自由に選択することができ
る。なお、実施例ではバンプ電極を金バンプ電極とした
が、このほかにその材料としてｍ、 １ｉ！、各種のは
んだ等を用いることができる。As can be seen from the embodiments described above, the present invention can be implemented in various ways. In particular, the degree of deformation of the bump electrode during pressure bonding can be freely selected by selecting the thickness, cross-sectional shape, and composite structure of the bump electrode. In the examples, gold bump electrodes were used as the bump electrodes, but other materials include m, 1i! , various solders, etc. can be used.
以上の説明からすでに明らかなように、本発明では半導
体装置の基板面から突出して複数個設けられ配線基板上
の対応する導体にそれぞれ押し付けられた状態で導電的
に接合されるバンプ電極において、バンプ電極の半導体
基板面に平行な方向の断面形状におけるバンプ電極がも
つ厚みをバンプ電極の半導体基板面に垂直な方向の高さ
寸法よりも小にすることにより、バンプ電極の導体への
加圧接合時にバンプ電極に適宜な度合いの変形を生じさ
せて、バンプ電極の高さにかなりのばらつきがあっても
導電接合を容易にかつ確実にすることができる。これに
よってバンプ電極を備えるフリップチップがもつ長所を
生かして半導体装置の配線基板への実装密度を一層向上
することができる。As is already clear from the above description, in the present invention, in a plurality of bump electrodes that are provided protruding from the substrate surface of a semiconductor device and are electrically connected to the corresponding conductor on the wiring board while being pressed, the bump By making the thickness of the bump electrode in the cross-sectional shape parallel to the semiconductor substrate surface of the electrode smaller than the height dimension of the bump electrode in the direction perpendicular to the semiconductor substrate surface, pressure bonding of the bump electrode to the conductor can be achieved. At times, by causing the bump electrode to deform to an appropriate degree, conductive bonding can be easily and reliably achieved even if there is considerable variation in the height of the bump electrode. This makes it possible to further improve the packaging density of semiconductor devices on wiring boards by taking advantage of the advantages of flip chips equipped with bump electrodes.
本発明のこのような特長はとくに接続点数が数百個程度
に大な半導体装置の実装用に適し、今後集積回路装置の
複雑度が増すとともに本発明の真価が発揮されて来るも
のと考えられる。These features of the present invention are particularly suitable for mounting semiconductor devices with a large number of connection points, on the order of several hundred, and it is believed that the true value of the present invention will be demonstrated as the complexity of integrated circuit devices increases in the future. .
第１図から第５図までが本発明に関し、第１図は本発明
による半導体装置のバンプ電極の代表的な実施例を示す
半導体装置の一部を拡大した平面図と断面図、および配
線基板への実装状態を示す側面図、第２図および第３図
は本発明のそれぞれ異なる実施例を示す半導体装置の一
部の平面図および側面図、第４図および第５図は本発明
のそれぞれさらに異なる実施例を示す半導体装置の一部
の平面図である。第６図は従来のバンプ電極を用いた半
導体装置の配線基板への実装状態を示す側面図である０
図において、
１０：半導体基板、１１：基板素体、１２：接読層、２
０〜２６：バンプ電極、２０ａ：バンプ電極用下地層、
３０：配線基板、３１：配線基板の導体、ｈ：バンプ電
極の高さ、ｔ：バンプ電極の厚み、である。
第 １ 図
第４図 第５図
第６ 図1 to 5 relate to the present invention, and FIG. 1 is an enlarged plan view and cross-sectional view of a part of a semiconductor device showing a typical embodiment of a bump electrode of a semiconductor device according to the present invention, and a wiring board. 2 and 3 are plan views and side views of a part of a semiconductor device showing different embodiments of the present invention, respectively. FIG. 7 is a plan view of a portion of a semiconductor device showing a further different embodiment. FIG. 6 is a side view showing a state in which a semiconductor device using conventional bump electrodes is mounted on a wiring board.
In the figure, 10: semiconductor substrate, 11: substrate body, 12: close reading layer, 2
0 to 26: bump electrode, 20a: base layer for bump electrode,
30: wiring board, 31: conductor of wiring board, h: height of bump electrode, t: thickness of bump electrode. Figure 1 Figure 4 Figure 5 Figure 6
Claims (1)
線基板上の対応する導体にそれぞれ押し付けられた状態
で導電的に接合されるバンプ電極であって、バンプ電極
の半導体基板面に平行な方向の断面形状におけるバンプ
電極がもつ厚みをバンプ電極の半導体基板面に垂直な方
向の高さ寸法よりも小にしたことを特徴とする半導体装
置のバンプ電極。 ２）特許請求の範囲第１項記載のバンプ電極において、
バンプ電極が電解めっきされたバンプ電極であることを
特徴とする半導体装置のバンプ電極。 ３）特許請求の範囲第２項記載のバンプ電極において、
バンプ電極の断面形状における厚みが１０〜３０μｍ程
度とされることを特徴とする半導体装置のバンプ電極。 ４）特許請求の範囲第３項記載のバンプ電極において、
バンプ電極の断面形状における厚みが２０μｍ程度とさ
れることを特徴とする半導体装置のバンプ電極。 ５）特許請求の範囲第１項記載のバンプ電極において、
バンプ電極が金バンプ電極であることを特徴とする半導
体装置のバンプ電極。 ６）特許請求の範囲第１項記載のバンプ電極において、
バンプ電極が筒状体として形成されたことを特徴とする
半導体装置のバンプ電極。 ７）特許請求の範囲第１項記載のバンプ電極において、
バンプ電極が断面形状において複数個の断面部分を有す
る複合バンプ電極として形成されたことを特徴とする半
導体装置のバンプ電極。[Scope of Claims] 1) A plurality of bump electrodes protruding from the substrate surface of a semiconductor device and electrically connected to the corresponding conductors on the wiring board while being pressed, the bump electrodes comprising: A bump electrode for a semiconductor device, characterized in that the thickness of the bump electrode in a cross-sectional shape in a direction parallel to a substrate surface is smaller than the height dimension of the bump electrode in a direction perpendicular to a semiconductor substrate surface. 2) In the bump electrode according to claim 1,
A bump electrode for a semiconductor device, characterized in that the bump electrode is an electrolytically plated bump electrode. 3) In the bump electrode according to claim 2,
A bump electrode for a semiconductor device, characterized in that the thickness of the bump electrode in a cross-sectional shape is about 10 to 30 μm. 4) In the bump electrode according to claim 3,
A bump electrode for a semiconductor device, characterized in that the thickness of the bump electrode in a cross-sectional shape is approximately 20 μm. 5) In the bump electrode according to claim 1,
A bump electrode for a semiconductor device, characterized in that the bump electrode is a gold bump electrode. 6) In the bump electrode according to claim 1,
A bump electrode for a semiconductor device, characterized in that the bump electrode is formed as a cylindrical body. 7) In the bump electrode according to claim 1,
1. A bump electrode for a semiconductor device, characterized in that the bump electrode is formed as a composite bump electrode having a plurality of cross-sectional sections.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62124509A JPS63289844A (en) | 1987-05-21 | 1987-05-21 | Bump electrode of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62124509A JPS63289844A (en) | 1987-05-21 | 1987-05-21 | Bump electrode of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63289844A true JPS63289844A (en) | 1988-11-28 |
Family
ID=14887246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62124509A Pending JPS63289844A (en) | 1987-05-21 | 1987-05-21 | Bump electrode of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63289844A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02297744A (en) * | 1989-05-11 | 1990-12-10 | Chiyuunaa Kk | Tape player |
| JPH0356136U (en) * | 1989-10-02 | 1991-05-30 | ||
| US6121062A (en) * | 1993-08-13 | 2000-09-19 | Fujitsu Limited | Process of fabricating semiconductor unit employing bumps to bond two components |
| JP2010272818A (en) * | 2009-05-25 | 2010-12-02 | Panasonic Corp | Mounting structure, and method of manufacturing the same |
| JP2018190775A (en) * | 2017-04-28 | 2018-11-29 | 東北マイクロテック株式会社 | Solid-state imaging apparatus |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5494872A (en) * | 1978-01-11 | 1979-07-26 | Cho Lsi Gijutsu Kenkyu Kumiai | Semiconductor device |
-
1987
- 1987-05-21 JP JP62124509A patent/JPS63289844A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5494872A (en) * | 1978-01-11 | 1979-07-26 | Cho Lsi Gijutsu Kenkyu Kumiai | Semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02297744A (en) * | 1989-05-11 | 1990-12-10 | Chiyuunaa Kk | Tape player |
| JPH0356136U (en) * | 1989-10-02 | 1991-05-30 | ||
| US6121062A (en) * | 1993-08-13 | 2000-09-19 | Fujitsu Limited | Process of fabricating semiconductor unit employing bumps to bond two components |
| JP2010272818A (en) * | 2009-05-25 | 2010-12-02 | Panasonic Corp | Mounting structure, and method of manufacturing the same |
| JP2018190775A (en) * | 2017-04-28 | 2018-11-29 | 東北マイクロテック株式会社 | Solid-state imaging apparatus |
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