JP2010272818A - Mounting structure, and method of manufacturing the same - Google Patents

Mounting structure, and method of manufacturing the same Download PDF

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JP2010272818A
JP2010272818A JP2009125678A JP2009125678A JP2010272818A JP 2010272818 A JP2010272818 A JP 2010272818A JP 2009125678 A JP2009125678 A JP 2009125678A JP 2009125678 A JP2009125678 A JP 2009125678A JP 2010272818 A JP2010272818 A JP 2010272818A
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semiconductor element
substrate
bump
mounting structure
terminal
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JP5322774B2 (en
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Kaori Yano
かおり 矢野
Takeshi Kawabata
毅 川端
Tatsuo Sasaoka
達雄 笹岡
Tomonori Ito
知規 伊藤
Hiroki Ikeuchi
宏樹 池内
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Panasonic Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/06102—Disposition the bonding areas being at different heights
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8184—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a mounting structure capable of achieving high heat radiation capability and strong joining capability from a semiconductor element to a substrate while suppressing damage of the semiconductor element in joining the semiconductor element to the substrate, and to provide a method of manufacturing the same. <P>SOLUTION: A terminal 5 of a semiconductor element 4 is joined to an electrode 3 of a substrate 2 by a joining part 6 in a state facing to each other, and the semiconductor element 4 is mounted on the substrate 2. The joining part 6 is composed of a bump 8 formed of a bulk metal material, and a sintered body 12 of metal particles 16. Each of the terminal 5 and the electrode 3 directly contacts both the bump 8 and the sintered body 12, and heat radiation from the semiconductor element 4 to the substrate 2 through both of them is enabled. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、実装構造体、およびその製造方法に関し、特に実装構造体を構成する半導体素子と基板とを接合する接合構造の改良に関する。   The present invention relates to a mounting structure and a method for manufacturing the same, and more particularly to an improvement in a bonding structure for bonding a semiconductor element and a substrate constituting the mounting structure.

半導体素子などの電子部品を、セラミックやポリイミド等の基板上に実装する方法として、金属ナノ粒子を接合材料として用いた方法が注目されている。金属ナノ粒子とはＡｕ、Ａｇ、Ｃｕ、Ｓｎ等の１００ｎｍ未満のサイズの金属粒子である。この金属ナノ粒子は、微細化により、表面活性度が高く且つ融点が低くなっており、低温（例えば１５０〜３５０℃）での焼結が可能である。   As a method for mounting an electronic component such as a semiconductor element on a substrate such as ceramic or polyimide, a method using metal nanoparticles as a bonding material has attracted attention. Metal nanoparticles are metal particles having a size of less than 100 nm, such as Au, Ag, Cu, and Sn. The metal nanoparticles have high surface activity and low melting point due to miniaturization, and can be sintered at a low temperature (for example, 150 to 350 ° C.).

また、金属ナノ粒子は、互いに結合してサイズが大きくなると、厚みがミリメートル単位以上である通常サイズの金属材料（以下、バルク金属材料という）と同等の高い融点となる。このため、電子部品の実装時の熱ストレスの低減および実装後の耐熱温度の向上が要求される幅広い製品への適用に好適である。また、導電ペースト（例えば、エポキシ系導電性接着剤）を使用して接合する場合と比較して、金属ナノ粒子を使用しての接合は、樹脂ではなく金属を溶融して接合が行われる。したがって、抵抗率が低く、接合強度の大きい、より優れた接合が実現される。   Further, when the metal nanoparticles are bonded to each other to increase in size, the metal nanoparticles have a high melting point equivalent to that of a metal material of normal size (hereinafter referred to as a bulk metal material) having a thickness of millimeter units or more. For this reason, it is suitable for application to a wide range of products that require reduction of thermal stress during mounting of electronic components and improvement of heat-resistant temperature after mounting. Moreover, compared with the case where it joins using an electrically conductive paste (for example, epoxy-type conductive adhesive), joining using a metal nanoparticle melt | dissolves a metal instead of resin, and joining is performed. Therefore, a more excellent bonding with a low resistivity and a high bonding strength is realized.

特許文献１に、金属ナノ粒子を接合材料として使用して、半導体素子を基板に実装した実装構造の一例が示されている。特許文献１の実装構造においては、半導体素子の端子に設けられたバンプと、基板の電極との間に金属ナノ粒子を介在させ、その金属ナノ粒子を焼結して半導体素子の端子と基板の電極とを接合している（特許文献１の図１参照）。   Patent Document 1 discloses an example of a mounting structure in which a semiconductor element is mounted on a substrate using metal nanoparticles as a bonding material. In the mounting structure of Patent Document 1, metal nanoparticles are interposed between the bumps provided on the terminals of the semiconductor element and the electrodes of the substrate, and the metal nanoparticles are sintered to sinter the terminals of the semiconductor element and the substrate. The electrode is joined (see FIG. 1 of Patent Document 1).

特開２００７−２０８０８２号公報JP 2007-208082 A

しかしながら、金属ナノ粒子を焼結して形成される層は熱伝導率がバルク金属材料よりも小さい。このため、半導体素子のバンプと基板の電極との間に金属ナノ粒子が介在している上記従来技術においては、半導体素子が発生した熱を基板に効果的に放熱することが困難となる。その結果、半導体素子の発熱量が大きい場合には十分な放熱を行うことができず、半導体素子の動作が不安定になる等の様々な不具合が生じる。また、半導体素子がＬＥＤ（Light Emitting Diode：発光ダイオード）素子である場合には、発光効率が著しく低下したりする等の不具合が生じる。   However, the layer formed by sintering metal nanoparticles has a lower thermal conductivity than the bulk metal material. For this reason, in the prior art in which metal nanoparticles are interposed between the bumps of the semiconductor element and the electrodes of the substrate, it is difficult to effectively dissipate the heat generated by the semiconductor element to the substrate. As a result, when the heat generation amount of the semiconductor element is large, sufficient heat dissipation cannot be performed, and various problems such as an unstable operation of the semiconductor element occur. In addition, when the semiconductor element is an LED (Light Emitting Diode) element, problems such as a significant decrease in light emission efficiency occur.

さらには、近年、半導体素子の処理能力はますます向上し、その発熱量もますます大きくなる傾向にあることから、半導体素子から基板への良好な放熱性が求められている。そのためには、半導体素子の端子または基板の電極と、これらを接合する接合部（バンプ等）との接触面積を大きくするのが効果的である。しかしながら、放熱性を良好とするためにバンプの面積を大きくすると、接合のために、より大きな荷重を与えたり、より高温に加熱したりするなどの必要があり、半導体素子を損傷する危険性が増大する。   Furthermore, in recent years, the processing capability of semiconductor elements has been further improved, and the amount of heat generated has also been increasing. Therefore, good heat dissipation from the semiconductor elements to the substrate is required. For this purpose, it is effective to increase the contact area between the terminal of the semiconductor element or the electrode of the substrate and the joint (bump or the like) for joining them. However, if the bump area is increased in order to improve heat dissipation, it is necessary to apply a larger load or heat to a higher temperature for bonding, which may damage the semiconductor element. Increase.

本発明は、上記問題点に鑑みてなされたものであり、半導体素子を基板に接合する際の半導体素子の損傷を抑えながら、半導体素子から基板への高い放熱性と、強固な接合性とを達成することができる実装構造体、およびその製造方法を提供することを目的とする。   The present invention has been made in view of the above problems, and has high heat dissipation from the semiconductor element to the substrate and strong bondability while suppressing damage to the semiconductor element when the semiconductor element is bonded to the substrate. It is an object of the present invention to provide a mounting structure that can be achieved and a method for manufacturing the same.

上記目的を達成するために、本発明は、半導体素子と基板とを備え、前記半導体素子の端子と前記基板の電極とを対向させるとともに、導体からなる接合部により接合して、前記半導体素子を前記基板に実装した実装構造体であって、
前記接合部は、バルク金属材料よりなるバンプと、その周囲に配された、金属粒子を焼結した焼結体とを含み、
前記バンプと前記焼結体とがそれぞれ独立に、前記半導体素子の端子と前記基板の電極とを電気的に接続している実装構造体を提供する。 In order to achieve the above object, the present invention comprises a semiconductor element and a substrate, the terminal of the semiconductor element and the electrode of the substrate are opposed to each other, and the semiconductor element is bonded by a bonding portion made of a conductor. A mounting structure mounted on the substrate,
The joint includes a bump made of a bulk metal material, and a sintered body that is disposed around the bump and sinters metal particles,
Provided is a mounting structure in which the bump and the sintered body electrically connect the terminal of the semiconductor element and the electrode of the substrate independently.

ここで、バルク金属材料とは、目視により形が判別し得る程度の大きさ、つまり厚みがマイクロメートル単位以上の通常の大きさの金属材料をいう。   Here, the bulk metal material refers to a metal material having a size that can be visually discriminated, that is, a normal size having a thickness of a micrometer unit or more.

本発明の好ましい形態の実装構造体においては、前記金属粒子は、平均粒径が０．５ｎｍ以上且つ１００ｎｍ以下の金属ナノ粒子である。   In a mounting structure according to a preferred embodiment of the present invention, the metal particles are metal nanoparticles having an average particle diameter of 0.5 nm or more and 100 nm or less.

本発明の別の好ましい形態の実装構造体においては、前記半導体素子の端子または前記基板の電極は、前記バンプとの接触面積が、前記焼結体との接触面積よりも大きい。   In another preferred embodiment of the mounting structure of the present invention, the contact area of the terminal of the semiconductor element or the electrode of the substrate with the bump is larger than the contact area with the sintered body.

本発明の別の好ましい形態の実装構造体においては、前記半導体素子は、少なくとも１つの端子が、複数個の前記バンプを含む接合部により前記基板の電極と接合されている。   In another preferred form of the mounting structure of the present invention, at least one terminal of the semiconductor element is bonded to the electrode of the substrate by a bonding portion including a plurality of the bumps.

本発明の別の好ましい形態の実装構造体においては、前記半導体素子の端子は、略全面が前記接合部と接触しており、その中央部における前記バンプとの接触面積の比率が、その周辺部における前記バンプとの接触面積の比率よりも大きい。   In another preferred embodiment of the mounting structure of the present invention, the entire surface of the terminal of the semiconductor element is in contact with the bonding portion, and the ratio of the contact area with the bump in the central portion is the peripheral portion. Is larger than the ratio of the contact area with the bump.

本発明の別の好ましい形態の実装構造体においては、前記バンプが所定の間隔をおいて互いに平行に並ぶ複数の列をなすように形成されている。   In another preferred embodiment of the mounting structure of the present invention, the bumps are formed in a plurality of rows arranged in parallel with each other at a predetermined interval.

本発明の別の好ましい形態の実装構造体においては、前記金属粒子が、金、銀および銅、並びにそれらの合金よりなる群から選択される少なくとも１種を含む。   In another preferred embodiment of the mounting structure of the present invention, the metal particles include at least one selected from the group consisting of gold, silver and copper, and alloys thereof.

本発明の別の好ましい形態の実装構造体においては、前記バンプが、金、銀および銅、並びにそれらの合金よりなる群から選択される少なくとも１種を含む。   In another preferred embodiment of the mounting structure of the present invention, the bump includes at least one selected from the group consisting of gold, silver and copper, and alloys thereof.

本発明の別の好ましい形態の実装構造体においては、前記半導体素子の端子または前記基板の電極が、金または金合金を含み、または表面が金または金合金によりコーティングされた導体から構成されている。   In another preferred embodiment of the mounting structure of the present invention, the terminal of the semiconductor element or the electrode of the substrate is made of a conductor containing gold or a gold alloy or having a surface coated with gold or a gold alloy. .

本発明の別の好ましい形態の実装構造体においては、前記半導体素子がＬＥＤ素子である。   In another preferred embodiment of the mounting structure of the present invention, the semiconductor element is an LED element.

また、本発明は、半導体素子と基板とを備え、前記半導体素子の端子と前記基板の電極とを対向させるとともに、導体からなる接合部により接合して、前記半導体素子を前記基板に実装した実装構造体であって、
前記接合部の少なくとも１つが、バルク金属材料よりなるバンプと、その周囲に配された、金属粒子を焼結した焼結体とを含み、当該接合部は、前記バンプと前記焼結体とがそれぞれ独立に、前記半導体素子の端子と前記基板の電極とを電気的に接続しているとともに、
前記接合部の他の少なくとも１つが、前記バンプのみからなる実装構造体を提供する。 In addition, the present invention includes a semiconductor element and a substrate, the terminal of the semiconductor element and the electrode of the substrate are opposed to each other, and the semiconductor element is mounted on the substrate by bonding with a bonding portion made of a conductor. A structure,
At least one of the joint portions includes a bump made of a bulk metal material and a sintered body that is disposed around the bump and is sintered with metal particles, and the joint portion includes the bump and the sintered body. Independently, while electrically connecting the terminal of the semiconductor element and the electrode of the substrate,
A mounting structure is provided in which at least one of the joints is composed only of the bumps.

さらに、本発明は、半導体素子の端子および基板の電極の少なくとも一方に、バルク金属材料からなるバンプを形成する工程ａ、
前記半導体素子の端子および前記基板の電極の他方に金属粒子を含むペーストを供給する工程ｂ、
前記半導体素子の端子と前記基板の電極とを対向させ、前記バンプにより前記半導体素子の端子と前記基板の電極とを接合する工程ｃ、並びに
前記バンプの周囲に配された前記金属粒子を含むペーストを加熱して、前記半導体素子の端子と前記基板の電極とをさらに接合するように、前記金属粒子の焼結体を形成する工程ｄ、
を含む実装構造体の製造方法を提供する。 Furthermore, the present invention provides a step a for forming a bump made of a bulk metal material on at least one of a terminal of a semiconductor element and an electrode of a substrate,
Supplying a paste containing metal particles to the other of the terminal of the semiconductor element and the electrode of the substrate b;
A step c in which the terminal of the semiconductor element and the electrode of the substrate are made to face each other, and the terminal of the semiconductor element and the electrode of the substrate are joined by the bump; and a paste containing the metal particles arranged around the bump Forming a sintered body of the metal particles so as to further bond the terminal of the semiconductor element and the electrode of the substrate,
The manufacturing method of the mounting structure containing is provided.

本発明の好ましい形態の製造方法は、さらに、前記形成されたバンプをレベリングする工程ｅを含む。   The manufacturing method according to a preferred embodiment of the present invention further includes a step e of leveling the formed bump.

本発明の別の好ましい形態の製造方法においては、前記工程ｃが、前記バンプに超音波振動を付与して行われる。   In another preferable embodiment of the manufacturing method of the present invention, the step c is performed by applying ultrasonic vibration to the bump.

本発明の別の好ましい形態の製造方法においては、前記工程ｂにおいて、前記ペーストを、前記半導体素子の端子または前記基板の電極の他方の、前記バンプと対向する部分を除いた部分に供給する。   In the manufacturing method according to another preferred embodiment of the present invention, in the step b, the paste is supplied to a portion of the terminal of the semiconductor element or the electrode of the substrate other than the portion facing the bump.

本発明の実装構造体によれば、接合部を構成するバンプおよび金属粒子の焼結体の両方が、直接的に半導体素子の端子および基板の電極と接触して、それらを接合するので、半導体素子が発生した熱を基板へ効果的に放熱することができる。
また、より大きな放熱性およびより強固な接合性を得るために、接合部の接合面積を大きくする場合にも、金属粒子の焼結体の接合面積を大きくすることで、大きな荷重をかけたり、高温に加熱したりすることなしに、半導体素子の端子と基板の電極とを接合することができる。 According to the mounting structure of the present invention, both the bumps constituting the joint and the sintered body of the metal particles are in direct contact with the terminals of the semiconductor element and the electrodes of the substrate to join them. The heat generated by the element can be effectively radiated to the substrate.
Also, in order to obtain greater heat dissipation and stronger bondability, even when increasing the bonded area of the bonded portion, by increasing the bonded area of the sintered body of metal particles, a large load can be applied, The terminal of the semiconductor element and the electrode of the substrate can be joined without heating to a high temperature.

本発明の実施の形態１に係る実装構造体の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of the mounting structure which concerns on Embodiment 1 of this invention. 金属粒子を含むペーストの概略構成を示す模式図である。It is a schematic diagram which shows schematic structure of the paste containing a metal particle. 本発明の実装構造体の製造方法の最初の手順を示す、半導体素子の一部の断面図である。It is sectional drawing of a part of semiconductor element which shows the first procedure of the manufacturing method of the mounting structure of this invention. 本発明の実装構造体の製造方法の次の手順を示す、基板の断面図である。It is sectional drawing of a board | substrate which shows the next procedure of the manufacturing method of the mounting structure of this invention. 本発明の実装構造体の製造方法のさらに次の手順を示す、半導体素子および基板の一部の断面図である。It is sectional drawing of a part of a semiconductor element and a board | substrate which shows the further next procedure of the manufacturing method of the mounting structure of this invention. 本発明の実装構造体の製造方法のさらに次の手順を示す、完成した実装構造体の一部の断面図である。It is a sectional view of a part of the completed mounting structure showing the following procedure of the manufacturing method of the mounting structure of the present invention. 上記実施の形態１のより好ましい形態に係る実装構造体の半導体素子の底面図である。It is a bottom view of the semiconductor element of the mounting structure which concerns on the more preferable form of the said Embodiment 1. FIG. 上記実施の形態１の別のより好ましい形態に係る実装構造体の半導体素子の底面図である。It is a bottom view of the semiconductor element of the mounting structure which concerns on another more preferable form of the said Embodiment 1. FIG. 上記実施の形態１のさらに別のより好ましい形態に係る実装構造体の半導体素子の底面図である。It is a bottom view of the semiconductor element of the mounting structure which concerns on another more preferable form of the said Embodiment 1. FIG. 上記実施の形態１のさらに別のより好ましい形態に係る実装構造体の半導体素子の底面図である。It is a bottom view of the semiconductor element of the mounting structure which concerns on another more preferable form of the said Embodiment 1. FIG. 本発明の実施の形態２に係る実装構造体の製造方法の手順を示す半導体および基板の一部の断面図である。It is sectional drawing of a part of semiconductor and board | substrate which shows the procedure of the manufacturing method of the mounting structure which concerns on Embodiment 2 of this invention.

以下本発明の実施の形態について、図面を参照しながら説明する。
（実施の形態１）
図１に、本発明の実施の形態１に係る実装構造体の概略構成を、一部を断面にした横断面図により示す。図示例の実装構造体１０は、基板２と、基板２に実装される半導体素子４とを含んでいる。基板２の表面には、半導体素子４の端子５と接続される電極３が形成されている。 Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 shows a schematic configuration of a mounting structure according to Embodiment 1 of the present invention in a cross-sectional view with a part in cross section. The mounting structure 10 in the illustrated example includes a substrate 2 and a semiconductor element 4 mounted on the substrate 2. An electrode 3 connected to the terminal 5 of the semiconductor element 4 is formed on the surface of the substrate 2.

半導体素子４は、端子５が基板２の電極３と対向するように配置されており、その状態で導体からなる接合部６により端子５と電極３とが接合されて、半導体素子４は、基板２に実装される。電極３および端子５は、例えばＡｕ（金）、Ａｇ(銀)、Ｃｕ(銅)もしくはＡｌ（アルミニウム）、またはそれらの合金から形成することができる。ただし、後で説明する焼結体１２との接合性を考慮するならば、電極３および端子５は、酸化しにくいＡｕもしくはＡｕ合金から形成されるか、または表面をＡｕまたはＡｕ合金によりコーティングした金属とするのが好ましい。   The semiconductor element 4 is arranged so that the terminal 5 faces the electrode 3 of the substrate 2, and in this state, the terminal 5 and the electrode 3 are joined by the joint portion 6 made of a conductor, and the semiconductor element 4 2 is implemented. The electrode 3 and the terminal 5 can be formed from, for example, Au (gold), Ag (silver), Cu (copper), Al (aluminum), or an alloy thereof. However, if the bonding property with the sintered body 12 described later is taken into consideration, the electrode 3 and the terminal 5 are formed of Au or Au alloy which is not easily oxidized, or the surface is coated with Au or Au alloy. It is preferable to use a metal.

接合部６は、バルク金属材料からなるバンプ８と、その周囲に配される金属粒子の焼結体１２とから構成される。バンプ８および焼結体１２は、それぞれ、基板２の電極３および半導体素子４の端子５のそれぞれとの接触面を有している。その結果、基板２の電極３と半導体素子４の端子５とは、バンプ８および焼結体１２の両方により導通された状態となっている。すなわち、バンプ８と焼結体１２とがそれぞれ独立に、半導体素子４の端子５と基板２の電極３とを電気的に接続している。   The joint portion 6 includes a bump 8 made of a bulk metal material, and a sintered body 12 of metal particles disposed around the joint 8. The bump 8 and the sintered body 12 have contact surfaces with the electrode 3 of the substrate 2 and the terminal 5 of the semiconductor element 4, respectively. As a result, the electrode 3 of the substrate 2 and the terminal 5 of the semiconductor element 4 are electrically connected by both the bump 8 and the sintered body 12. That is, the bump 8 and the sintered body 12 electrically connect the terminal 5 of the semiconductor element 4 and the electrode 3 of the substrate 2 independently of each other.

基板２は、例えばアルミナ基板や窒化アルミニウム基板等の放熱性のよい素材から構成された基板とするのが好ましい。その他、メタルコア基板、およびメタルベース基板のような高放熱基板とすることもできる。   The substrate 2 is preferably a substrate made of a material having good heat dissipation, such as an alumina substrate or an aluminum nitride substrate. In addition, a high heat dissipation substrate such as a metal core substrate and a metal base substrate can be used.

バンプ８は、マイグレーションや酸化をしにくいことから、Ａｕで形成するのが好ましい。しかしながら、Ａｕの合金、Ａｇ、Ａｇの合金、Ｃｕ、またはＣｕの合金等の熱伝導性の良い導体であれば、バンプ８の素材として好適に使用することができる。   The bumps 8 are preferably made of Au because they are difficult to migrate and oxidize. However, any conductor having good thermal conductivity such as Au alloy, Ag, Ag alloy, Cu, or Cu alloy can be suitably used as the material of the bump 8.

焼結体１２は金属粒子を含むペーストをバンプ８の周囲に供給し、その金属粒子を焼結して形成される。
図２に、焼結体１２を形成するために使用されるペーストの一例を模式的に示す。図示例のペースト１４は、導電成分である多数の金属粒子１６と、個々の金属粒子１６が、互いに融着しないように分離させる分散剤１８と、分散剤１８により互いに分離された金属粒子１６を分散させる分散媒２０とから構成されている。なお、図２においては、視認性を考慮して、個々の金属粒子１６を断面により示す一方で、分散剤１８については、個々の金属粒子１６の断面を構成する平面と交わる位置にあるものを正面図により示している。 The sintered body 12 is formed by supplying a paste containing metal particles around the bumps 8 and sintering the metal particles.
In FIG. 2, an example of the paste used in order to form the sintered compact 12 is shown typically. The illustrated paste 14 includes a large number of metal particles 16 that are conductive components, a dispersant 18 that separates the individual metal particles 16 so as not to be fused to each other, and metal particles 16 that are separated from each other by the dispersant 18. It is comprised from the dispersion medium 20 to disperse | distribute. In FIG. 2, the individual metal particles 16 are shown in cross-section in consideration of visibility, while the dispersant 18 is located at a position intersecting with the plane constituting the cross-section of the individual metal particles 16. It is shown by a front view.

金属粒子１６には、平均粒径が０．５〜１００ｎｍの金属粒子（金属ナノ粒子）を使用することができる。そのような金属粒子１６の一例として、粒径が３〜７ｎｍである、ハリマ化成（株）製のＮＰＧ−Ｊがある。また、金属粒子１６の素材として、Ａｕ、Ａｇ、およびＣｕ、並びにそれらの合金を使用することができる。
分散媒２０には、テルピネオール、デカノール、テトラデカン、トルエンまたはデカリン等を使用することができる。 As the metal particles 16, metal particles (metal nanoparticles) having an average particle diameter of 0.5 to 100 nm can be used. An example of such a metal particle 16 is NPG-J manufactured by Harima Kasei Co., Ltd. having a particle size of 3 to 7 nm. Further, Au, Ag, and Cu, and alloys thereof can be used as the material for the metal particles 16.
As the dispersion medium 20, terpineol, decanol, tetradecane, toluene, decalin, or the like can be used.

次に、図３Ａから図３Ｄを参照して、接合部６により基板２の電極３と半導体素子４の端子５とを接合する手順の一例を説明する。   Next, an example of a procedure for joining the electrode 3 of the substrate 2 and the terminal 5 of the semiconductor element 4 by the joining portion 6 will be described with reference to FIGS. 3A to 3D.

図３Ａにおいては、半導体素子４の一例としてのＬＥＤ素子の端子５の上に、例えばワイヤーボンディング装置を使用してバンプ８を形成している。このとき、図に示すようにバンプ８の高さに差がある場合には、バンプ８の高さを一定とするようにレベリングを行うのが好ましい。バンプ８は、ワイヤーボンディング装置を使用して形成することができる他、メッキ法、塗布法または印刷法により形成することができる。塗布法または印刷法による場合には、バンプ形成用のペーストを供給した後に、焼成してバンプ８を形成することができる。   In FIG. 3A, bumps 8 are formed on the terminals 5 of LED elements as an example of the semiconductor element 4 by using, for example, a wire bonding apparatus. At this time, when there is a difference in the height of the bump 8 as shown in the figure, it is preferable to perform leveling so that the height of the bump 8 is constant. The bumps 8 can be formed using a wire bonding apparatus, or can be formed by a plating method, a coating method, or a printing method. When the coating method or the printing method is used, the bumps 8 can be formed by firing after supplying the paste for forming the bumps.

また、バンプ８は、端子５の面積が比較的大きい場合には、図３Ａに示すように、半導体素子４の１つの端子５の上に複数個形成するのが好ましい。これにより、焼結体１２よりも熱伝導性に優れるバンプ８が、１つの端子５の上に分散して存在することになり、半導体素子４が発生した熱をより均一に基板へ放熱することができる。その結果、半導体素子４がＬＥＤ素子からなる場合にも、その発熱を効果的に放熱することが可能となり、発光効率の低下を効果的に抑制することができる。   When the area of the terminal 5 is relatively large, a plurality of bumps 8 are preferably formed on one terminal 5 of the semiconductor element 4 as shown in FIG. 3A. As a result, the bumps 8 having higher thermal conductivity than the sintered body 12 are present on the one terminal 5 in a dispersed manner, and the heat generated by the semiconductor element 4 can be dissipated more uniformly to the substrate. Can do. As a result, even when the semiconductor element 4 is an LED element, it is possible to effectively dissipate the generated heat, and it is possible to effectively suppress a decrease in light emission efficiency.

一方、図３Ｂに示すように、基板２の電極３の上には、金属粒子１６を含むペースト１４を供給する。ペースト１４を供給する方法は塗布または印刷によることができる。ペースト１４の塗布または印刷の具体的方法を挙げれば、例えば、スクリーンおよびスキージを使用する方法、インクジェット方式、転写用のステージの上に塗布したペースト１４を電極上に形成されたバンプ８に転写する方法等がある。
ペースト１４を基板２の電極３の上に供給した後、必要に応じて乾燥工程を行うことができる。 On the other hand, as shown in FIG. 3B, a paste 14 containing metal particles 16 is supplied onto the electrode 3 of the substrate 2. The method of supplying the paste 14 can be applied or printed. Specific methods for applying or printing the paste 14 include, for example, a method using a screen and a squeegee, an ink jet method, and the paste 14 applied on a transfer stage is transferred to the bumps 8 formed on the electrodes. There are methods.
After the paste 14 is supplied onto the electrode 3 of the substrate 2, a drying process can be performed as necessary.

なお、半導体素子４がＬＥＤ素子の場合には、発熱性を有しないＮ極端子においては特に伝熱性を上げる必要がないので、接合部を、焼結体１２を有しないバンプ８のみから構成することができる。これにより、ペースト１４の使用量を削減することができる。   In the case where the semiconductor element 4 is an LED element, it is not necessary to increase the heat conductivity particularly in the N-pole terminal that does not have heat generation, and therefore, the joint portion is constituted only by the bumps 8 that do not have the sintered body 12. be able to. Thereby, the usage-amount of the paste 14 can be reduced.

次に、図３Ｃに示すように、図示しないフリップチップボンダーの搭載ツール２２により、半導体素子４を、端子５と基板２の電極３とを対向させるようにして保持する。搭載ツール２２を通して半導体素子４に超音波振動を印加しながら、バンプ８を基板２の電極３に押し付けるように、半導体素子４を基板２に向かって押圧する。これにより、バンプ８により半導体素子４の端子５と基板２の電極３とが接合される。超音波振動を半導体素子４に印加しながら接合することで、バンプ８と電極２とをより強固に接合することができる。   Next, as shown in FIG. 3C, the semiconductor element 4 is held by the flip chip bonder mounting tool 22 (not shown) so that the terminals 5 and the electrodes 3 of the substrate 2 face each other. While applying ultrasonic vibration to the semiconductor element 4 through the mounting tool 22, the semiconductor element 4 is pressed toward the substrate 2 so as to press the bumps 8 against the electrodes 3 of the substrate 2. Thereby, the terminals 5 of the semiconductor element 4 and the electrodes 3 of the substrate 2 are joined by the bumps 8. By bonding while applying ultrasonic vibration to the semiconductor element 4, the bump 8 and the electrode 2 can be bonded more firmly.

ここで、超音波振動を印加せずに、押圧のみにより、または加熱しながら押圧することにより、バンプ８と電極３とを接合してもよい。超音波振動を印加しないことにより、半導体素子４に与える物理的ダメージを低減することができる。   Here, the bumps 8 and the electrodes 3 may be joined by applying pressure alone or by heating without applying ultrasonic vibration. By not applying ultrasonic vibration, physical damage to the semiconductor element 4 can be reduced.

次に、図３Ｄに示すように、基板２を通してペースト１４を加熱することにより、分散剤１８および分散媒２０を分解するとともに、ペースト１４中の金属粒子１６（図２参照）同士を互いに溶着させて焼結体１２を形成する。焼結体１２を形成するための焼成は、例えば電気炉およびホットプレート等を使用して、２００〜３００℃の温度で基板２を３０〜６０分間加熱するようにして行うことができる。   Next, as shown in FIG. 3D, by heating the paste 14 through the substrate 2, the dispersant 18 and the dispersion medium 20 are decomposed, and the metal particles 16 (see FIG. 2) in the paste 14 are welded together. Thus, the sintered body 12 is formed. Firing for forming the sintered body 12 can be performed by heating the substrate 2 at a temperature of 200 to 300 ° C. for 30 to 60 minutes using, for example, an electric furnace and a hot plate.

ここで、焼結体１２の形成は、バンプ８と電極３とを接合するときに（図３Ｃ参照）同時にペースト１４（基板２）を加熱するようにして行ってもよい。これにより、工程数を削減することができる。
また、基板２を通して加熱する方法に限らず、例えば超音波や、電磁波等のエネルギーをペースト１４に付与することにより、ペースト１４中の金属粒子１６を焼結してもよい。 Here, the sintered body 12 may be formed by heating the paste 14 (substrate 2) simultaneously when the bumps 8 and the electrodes 3 are joined (see FIG. 3C). Thereby, the number of processes can be reduced.
Further, the method is not limited to the method of heating through the substrate 2. For example, the metal particles 16 in the paste 14 may be sintered by applying energy such as ultrasonic waves or electromagnetic waves to the paste 14.

以上述べたように、本実施の形態の実装構造体においては、基板２の電極３と半導体素子４の端子５とを接合する接合部６が、バルク金属材料からなるバンプ８と、金属粒子１６の焼結体１２とから構成されている。このため、接合部６の全てをバンプ８から形成する場合と比較して、基板２の電極３と半導体素子４の端子５とを接合するときに、半導体素子４を基板２に向かって押圧するときの荷重をより小さくすることができる。したがって、接合部６と、基板２の電極３および半導体素子４の端子５との接触面積を容易に大きくすることができ、半導体素子４が発生する熱の放熱性を容易に向上させることができる。また、基板２の電極３と半導体素子４の端子５との接合をより強固なものとすることができるとともに、導電性も向上する。   As described above, in the mounting structure of the present embodiment, the joint 6 that joins the electrode 3 of the substrate 2 and the terminal 5 of the semiconductor element 4 includes the bumps 8 made of a bulk metal material and the metal particles 16. And the sintered body 12. For this reason, the semiconductor element 4 is pressed toward the substrate 2 when the electrode 3 of the substrate 2 and the terminal 5 of the semiconductor element 4 are bonded as compared with the case where all of the bonding portions 6 are formed from the bumps 8. The load at the time can be made smaller. Therefore, the contact area between the junction 6 and the electrode 3 of the substrate 2 and the terminal 5 of the semiconductor element 4 can be easily increased, and the heat dissipation of the heat generated by the semiconductor element 4 can be easily improved. . Further, the bonding between the electrode 3 of the substrate 2 and the terminal 5 of the semiconductor element 4 can be made stronger and the conductivity is also improved.

また、図４に示すように、比較的面積の大きい１つの端子５にバンプ８を複数個設ける場合には、端子５の周辺部よりも中央部により多くのバンプ８を設けるのが好ましい。これにより、端子５の周辺部よりも中央部の熱伝導性がより大きくなり、焼結体１２の焼結は、端子５の中央部が周辺部よりも先に完了する。その結果、焼結の際に発生する気体を外部へ効率よく逃がすことができ、焼結体１２内部の空隙を低減することができる。したがって、放熱性が向上する。   As shown in FIG. 4, when a plurality of bumps 8 are provided on one terminal 5 having a relatively large area, it is preferable to provide more bumps 8 in the central portion than in the peripheral portion of the terminals 5. Thereby, the thermal conductivity of the central portion is greater than that of the peripheral portion of the terminal 5, and the sintering of the sintered body 12 is completed before the peripheral portion of the central portion of the terminal 5. As a result, gas generated during sintering can be efficiently released to the outside, and voids in the sintered body 12 can be reduced. Therefore, heat dissipation is improved.

図５に、メッキ法、塗布法または印刷法により、平面視による面積の大きな１つのバンプ８を形成した場合を示す。図示例のバンプ８は、端子５の周辺部よりも中央部において平面視による面積が大きくなっている。その結果、端子５の周辺部よりも中央部の熱伝導性がより大きくなり、図４の場合と同様の効果を得ることができる。   FIG. 5 shows a case where one bump 8 having a large area in plan view is formed by a plating method, a coating method, or a printing method. The bump 8 in the illustrated example has a larger area in plan view at the center than at the periphery of the terminal 5. As a result, the thermal conductivity of the central portion is greater than that of the peripheral portion of the terminal 5, and the same effect as in the case of FIG. 4 can be obtained.

また、図６および図７に示すように、バンプ８は、所定の間隔をおいて互いに平行に並ぶ複数の列をなすように形成することが好ましい。これにより、焼結体１２の焼結の際に発生する気体を外部へ効率よく逃がすことができる。焼結体１２の焼結は、バンプ８の周囲から順次完了するからである。その結果、焼結体１２内部の空隙を低減することができ、放熱性が向上する。   Further, as shown in FIGS. 6 and 7, the bumps 8 are preferably formed so as to form a plurality of rows arranged in parallel with each other at a predetermined interval. Thereby, the gas generated when the sintered body 12 is sintered can be efficiently released to the outside. This is because the sintering of the sintered body 12 is completed sequentially from the periphery of the bump 8. As a result, voids inside the sintered body 12 can be reduced, and heat dissipation is improved.

ここで、バンプ８と基板２の電極３および半導体素子４の端子５との接触面積は、焼結体１２とそれらとの接触面積よりも大きい方が好ましい。これは、バルク金属材料からなるバンプ８は、金属ナノ粒子の焼結体１２よりも一般的に熱伝導性に優れるからであり、その結果、放熱性が向上する。   Here, the contact area between the bump 8 and the electrode 3 of the substrate 2 and the terminal 5 of the semiconductor element 4 is preferably larger than the contact area between the sintered body 12 and them. This is because the bump 8 made of a bulk metal material is generally better in thermal conductivity than the sintered body 12 of metal nanoparticles, and as a result, heat dissipation is improved.

また、本実施の形態１においては、半導体素子４の端子５のほぼ全面と接触するように接合部６を設けている（図３Ｄ等参照）。その結果、接合部６を通した放熱性が顕著に向上する。
なお、接合部６の全てをバンプ８から構成し、その平面視面積を大きくして放熱性の向上を図ろうとすると、高荷重および高温加熱の下で接合を行う必要があり、半導体素子４に損傷を与える可能性が増大する。本実施の形態の実装構造体によれば、そのような不具合を生じることなく放熱性を向上させることができる。 In the first embodiment, the junction 6 is provided so as to be in contact with almost the entire surface of the terminal 5 of the semiconductor element 4 (see FIG. 3D and the like). As a result, the heat dissipation through the joint 6 is significantly improved.
Note that if all of the joint portions 6 are constituted by the bumps 8 and the plan view area is increased to improve heat dissipation, it is necessary to perform the joining under high load and high temperature heating. The potential for damage is increased. According to the mounting structure of the present embodiment, heat dissipation can be improved without causing such a problem.

（実施の形態２）
次に、図８を参照して、本発明の実施の形態２を説明する。実施の形態２は、実施の形態１を改変したものであり、基本的な構成は実施の形態１と共通であるので、以下に、実施の形態１とは異なる部分を主に説明する。
図８に示すように、実施の形態２の実装構造体１０Ａにおいては、ペースト１４は、基板２の電極３の、バンプ８と対向する部分には供給されておらず、バンプ８と対向しない部分にのみ供給されている。 (Embodiment 2)
Next, a second embodiment of the present invention will be described with reference to FIG. The second embodiment is a modification of the first embodiment, and the basic configuration is the same as that of the first embodiment. Therefore, the parts different from the first embodiment will be mainly described below.
As shown in FIG. 8, in the mounting structure 10 </ b> A of the second embodiment, the paste 14 is not supplied to the portion of the electrode 3 of the substrate 2 that faces the bump 8, and the portion that does not face the bump 8. Is only supplied to.

これにより、ペースト１４を、バンプ８と電極３との間に全く介在させることなくバンプ８と電極３とを接合することが可能となる。その結果、バンプ８と電極３との接触面積をさらに大きくすることができる。したがって、半導体素子４から基板２への放熱性がさらに向上する。また、バンプ８と電極３とを接合する際に、バンプ８と対向する部分のペースト１４をバンプ８によって押しのける必要がなくなる。このため、半導体素子の実装をより低荷重で実現することができ、薄い半導体素子であっても損傷することなく基板２に実装することが可能となる。   Thereby, it becomes possible to join the bump 8 and the electrode 3 without interposing the paste 14 between the bump 8 and the electrode 3 at all. As a result, the contact area between the bump 8 and the electrode 3 can be further increased. Therefore, the heat dissipation from the semiconductor element 4 to the substrate 2 is further improved. Further, when bonding the bump 8 and the electrode 3, it is not necessary to push away the paste 14 at the portion facing the bump 8 by the bump 8. For this reason, mounting of the semiconductor element can be realized with a lower load, and even a thin semiconductor element can be mounted on the substrate 2 without being damaged.

以上、本発明を実施の形態により説明したが、本発明は、種々改変が可能である。例えば、バンプ８は半導体素子４の端子５に形成するものとしたが、バンプ８を基板２の電極３に形成し、ペースト１４を半導体素子４の端子５に供給することも可能である。
半導体素子４はＬＥＤ素子に限らず、本発明は、発熱性を有する全ての半導体素子に好適に適用できる。 As mentioned above, although this invention was demonstrated by embodiment, this invention can be variously modified. For example, the bumps 8 are formed on the terminals 5 of the semiconductor element 4, but the bumps 8 may be formed on the electrodes 3 of the substrate 2 and the paste 14 may be supplied to the terminals 5 of the semiconductor element 4.
The semiconductor element 4 is not limited to an LED element, and the present invention can be suitably applied to all semiconductor elements having heat generation properties.

焼結体１２の材料である金属粒子１６は、金属ナノ粒子としたが、ミクロンサイズの金属粒子を金属粒子１６として使用することもできる。ただし、金属ナノ粒子は、素材金属よりも遙かに低い融点で粒子を焼結することができ、焼結後には融点がバルク金属材料と同じ温度にまで上昇するという特徴を持つ。そのため、低温で接合でき、実装後に耐熱温度が向上するという点で、焼結体１２の材料は金属ナノ粒子を用いるのが好ましい。   Although the metal particles 16 that are the material of the sintered body 12 are metal nanoparticles, micron-sized metal particles can also be used as the metal particles 16. However, the metal nanoparticles can sinter particles at a melting point much lower than that of the raw metal, and have a feature that the melting point rises to the same temperature as the bulk metal material after sintering. Therefore, it is preferable to use metal nanoparticles as the material of the sintered body 12 in that bonding can be performed at a low temperature and the heat resistant temperature is improved after mounting.

ペースト１４は、バンプ８を基板２の電極３と接合する前に電極３の上に供給したが、バンプ８を基板２の電極３と接合した後に、基板２の電極３と半導体素子４の端子５との間に注入する等して、供給することもできる。
さらに、半導体素子４の端子５の全てが基板２の電極２と対向している必要はなく、複数設けられた端子５の中の少なくとも１つが基板２と対向していればよい。 The paste 14 was supplied onto the electrode 3 before bonding the bump 8 to the electrode 3 on the substrate 2, but after bonding the bump 8 to the electrode 3 on the substrate 2, the electrode 3 on the substrate 2 and the terminal of the semiconductor element 4. It is also possible to supply it by injecting between the two.
Furthermore, it is not necessary for all the terminals 5 of the semiconductor element 4 to face the electrode 2 of the substrate 2, and at least one of the plurality of terminals 5 provided to face the substrate 2.

本発明の実装構造体、およびその製造方法によれば、低荷重下での半導体素子の端子と基板の電極との間での良好な接合、並びに半導体素子から基板への接合部を通した良好な放熱性が達成される。したがって、発熱量の多い半導体素子や、温度の上昇により性能の劣化が激しい半導体素子の実装への適用に有効である。   According to the mounting structure of the present invention and the manufacturing method thereof, good bonding between the terminal of the semiconductor element and the electrode of the substrate under a low load, and good passing through the bonding portion from the semiconductor element to the substrate Heat dissipation is achieved. Therefore, it is effective for application to mounting of a semiconductor element having a large amount of heat generation or a semiconductor element whose performance is severely deteriorated due to a rise in temperature.

２ 基板
３ 電極
４ 半導体素子
５ 端子
６ 接合部
８ バンプ
１０ 実装構造体
１２ 焼結体
１４ ペースト
１６ 金属粒子 2 Substrate 3 Electrode 4 Semiconductor element 5 Terminal 6 Joint 8 Bump 10 Mounting structure 12 Sintered body 14 Paste 16 Metal particle

Claims (15)

半導体素子と基板とを備え、前記半導体素子の端子と前記基板の電極とを対向させるとともに、導体からなる接合部により接合して、前記半導体素子を前記基板に実装した実装構造体であって、
前記接合部は、バルク金属材料よりなるバンプと、その周囲に配された、金属粒子を焼結した焼結体とを含み、
前記バンプと前記焼結体とがそれぞれ独立に、前記半導体素子の端子と前記基板の電極とを電気的に接続している実装構造体。 A mounting structure comprising a semiconductor element and a substrate, the terminal of the semiconductor element and the electrode of the substrate are opposed to each other and bonded by a bonding portion made of a conductor, and the semiconductor element is mounted on the substrate,
The joint includes a bump made of a bulk metal material, and a sintered body that is disposed around the bump and sinters metal particles,
The mounting structure in which the bump and the sintered body electrically connect the terminal of the semiconductor element and the electrode of the substrate independently. 前記金属粒子は、平均粒径が０．５ｎｍ以上且つ１００ｎｍ以下の金属ナノ粒子である請求項１記載の実装構造体。   The mounting structure according to claim 1, wherein the metal particles are metal nanoparticles having an average particle size of 0.5 nm or more and 100 nm or less. 前記半導体素子の端子または前記基板の電極は、前記バンプとの接触面積が、前記焼結体との接触面積よりも大きい請求項１または２記載の実装構造体。   3. The mounting structure according to claim 1, wherein the terminal of the semiconductor element or the electrode of the substrate has a larger contact area with the bump than a contact area with the sintered body. 前記半導体素子は、少なくとも１つの端子が、複数個の前記バンプを含む接合部により前記基板の電極と接合されている請求項１〜３のいずれかに記載の実装構造体。   The mounting structure according to claim 1, wherein at least one terminal of the semiconductor element is bonded to an electrode of the substrate by a bonding portion including a plurality of the bumps. 前記半導体素子の端子は、略全面が前記接合部と接触しており、その中央部における前記バンプとの接触面積の比率が、その周辺部における前記バンプとの接触面積の比率よりも大きい請求項１〜４のいずれかに記載の実装構造体。   The substantially entire surface of the terminal of the semiconductor element is in contact with the bonding portion, and the ratio of the contact area with the bump in the central portion is larger than the ratio of the contact area with the bump in the peripheral portion. The mounting structure in any one of 1-4. 前記バンプが所定の間隔をおいて互いに平行に並ぶ複数の列をなすように形成された請求項１〜５のいずれかに記載の実装構造体。   The mounting structure according to claim 1, wherein the bumps are formed in a plurality of rows arranged in parallel with each other at a predetermined interval. 前記金属粒子が、金、銀および銅、並びにそれらの合金よりなる群から選択される少なくとも１種を含む請求項１〜６のいずれかに記載の実装構造体。   The mounting structure according to claim 1, wherein the metal particles include at least one selected from the group consisting of gold, silver, copper, and alloys thereof. 前記バンプが、金、銀および銅、並びにそれらの合金よりなる群から選択される少なくとも１種を含む請求項１〜７のいずれかに記載の実装構造体。   The mounting structure according to claim 1, wherein the bump includes at least one selected from the group consisting of gold, silver, copper, and alloys thereof. 前記半導体素子の端子または前記基板の電極が、金または金合金を含み、または表面が金または金合金によりコーティングされた導体から構成された請求項１〜８のいずれかに記載の実装構造体。   The mounting structure according to claim 1, wherein the terminal of the semiconductor element or the electrode of the substrate includes gold or a gold alloy, or a conductor whose surface is coated with gold or a gold alloy. 前記半導体素子がＬＥＤ素子である請求項１〜９のいずれかに記載の実装構造体。   The mounting structure according to claim 1, wherein the semiconductor element is an LED element. 半導体素子と基板とを備え、前記半導体素子の端子と前記基板の電極とを対向させるとともに、導体からなる接合部により接合して、前記半導体素子を前記基板に実装した実装構造体であって、
前記接合部の少なくとも１つが、バルク金属材料よりなるバンプと、その周囲に配された、金属粒子を焼結した焼結体とを含み、当該接合部は、前記バンプと前記焼結体とがそれぞれ独立に、前記半導体素子の端子と前記基板の電極とを電気的に接続しているとともに、
前記接合部の他の少なくとも１つが、前記バンプのみからなる実装構造体。 A mounting structure comprising a semiconductor element and a substrate, the terminal of the semiconductor element and the electrode of the substrate are opposed to each other and bonded by a bonding portion made of a conductor, and the semiconductor element is mounted on the substrate,
At least one of the joint portions includes a bump made of a bulk metal material and a sintered body that is disposed around the bump and is sintered with metal particles, and the joint portion includes the bump and the sintered body. Independently, while electrically connecting the terminal of the semiconductor element and the electrode of the substrate,
A mounting structure in which at least one of the joint portions is composed only of the bumps. 半導体素子の端子および基板の電極の少なくとも一方に、バルク金属材料からなるバンプを形成する工程ａ、
前記半導体素子の端子および前記基板の電極の他方に金属粒子を含むペーストを供給する工程ｂ、
前記半導体素子の端子と前記基板の電極とを対向させ、前記バンプにより前記半導体素子の端子と前記基板の電極とを接合する工程ｃ、並びに
前記バンプの周囲に配された前記金属粒子を含むペーストを加熱して、前記半導体素子の端子と前記基板の電極とをさらに接合するように、前記金属粒子の焼結体を形成する工程ｄ、
を含む実装構造体の製造方法。 Forming a bump made of a bulk metal material on at least one of a terminal of a semiconductor element and an electrode of a substrate; a,
Supplying a paste containing metal particles to the other of the terminal of the semiconductor element and the electrode of the substrate b;
A step c in which the terminal of the semiconductor element and the electrode of the substrate are made to face each other, and the terminal of the semiconductor element and the electrode of the substrate are joined by the bump; and a paste containing the metal particles arranged around the bump Forming a sintered body of the metal particles so as to further bond the terminal of the semiconductor element and the electrode of the substrate,
A method for manufacturing a mounting structure including: さらに、前記形成されたバンプをレベリングする工程ｅを含む請求項１２に記載の製造方法。   The manufacturing method according to claim 12, further comprising a step e of leveling the formed bump. 前記工程ｃが、前記バンプに超音波振動を付与して行われる請求項１２または１３記載の実装構造体の製造方法。   The method of manufacturing a mounting structure according to claim 12, wherein the step c is performed by applying ultrasonic vibration to the bump. 前記工程ｂにおいて、前記ペーストを、前記半導体素子の端子または前記基板の電極の他方の、前記バンプと対向する部分を除いた部分に供給する請求項１２〜１４のいずれかに記載の実装構造体の製造方法。   The mounting structure according to any one of claims 12 to 14, wherein in the step b, the paste is supplied to a portion of the other of the terminal of the semiconductor element or the electrode of the substrate excluding the portion facing the bump. Manufacturing method.
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