JP2010278193A - Electronic component, electronic component device using the same and method of manufacturing them - Google Patents

Electronic component, electronic component device using the same and method of manufacturing them Download PDF

Info

Publication number
JP2010278193A
JP2010278193A JP2009128684A JP2009128684A JP2010278193A JP 2010278193 A JP2010278193 A JP 2010278193A JP 2009128684 A JP2009128684 A JP 2009128684A JP 2009128684 A JP2009128684 A JP 2009128684A JP 2010278193 A JP2010278193 A JP 2010278193A
Authority
JP
Japan
Prior art keywords
electronic component
electrode
wall
metal nanoparticle
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009128684A
Other languages
Japanese (ja)
Inventor
Takashi Yamamoto
孝志 山本
Daigo Kobayashi
大悟 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2009128684A priority Critical patent/JP2010278193A/en
Publication of JP2010278193A publication Critical patent/JP2010278193A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/035Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/03505Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/05698Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05699Material of the matrix
    • H01L2224/05794Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/057 - H01L2224/05791
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/05698Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05798Fillers
    • H01L2224/05799Base material
    • H01L2224/058Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05838Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05847Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199Material of the matrix
    • H01L2224/13294Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13347Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/8184Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]

Landscapes

  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component with high connection reliability and electrical conductivity, even when a metal nanoparticle layer in a metal nanoparticle junction is thin, and to provide an electronic component device which uses the component and a method of manufacturing them. <P>SOLUTION: In the electronic component including a base body, a first electrode formed on the base body, a wall formed on the surface of the base body and formed so as to be in contact with at least one of the side face and upper surface of the first electrode and to surround the periphery of the first electrode, and a second electrode bonded on the first electrode, the second electrode comprises a metal nanoparticle sintered body, is formed inside a space surrounded by the first electrode and the wall, and is formed into a bathtub shape. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、電子部品、それを用いた電子部品装置及びそれらの製造方法に関し、特に基板と電子部品などが金属ナノ粒子によって接合されるようにした電子部品、それを用いた電子部品装置及びそれらの製造方法に関する。   The present invention relates to an electronic component, an electronic component device using the same, and a method of manufacturing the same, and more particularly, an electronic component in which a substrate and an electronic component are joined by metal nanoparticles, an electronic component device using the electronic component, and the like It relates to the manufacturing method.

基板と電子部品の電極同士の接合に用いる材料はこれまでPb−5Sn系はんだが主たるものであったが、昨今の環境保全の要求に伴うPb使用に対する規制が厳しくなっている。その代替手段として金属ナノ粒子を主材とする接合材料を用いた電子部品装置およびその製造方法が提案されている(特許文献1参照)。   The material used for joining the electrodes of the substrate and the electronic component has been mainly Pb-5Sn solder so far, but regulations on the use of Pb in accordance with recent demands for environmental protection are becoming stricter. As an alternative, an electronic component device using a bonding material mainly composed of metal nanoparticles and a manufacturing method thereof have been proposed (see Patent Document 1).

特許文献1には、金属ナノ粒子ペーストを用いて、フリップチップ接続することにより得られる電子部品装置が開示されている。その製造工程の一例を図7に示す。   Patent Document 1 discloses an electronic component device obtained by flip-chip connection using a metal nanoparticle paste. An example of the manufacturing process is shown in FIG.

以下に、図7を用いて製造工程を説明する。まず、電子部品素子202に電子部品電極203を形成し、その表面に金属ナノ粒子ペーストからなる第2の電極212を形成する(図7(a))。次に、基板素子207に基板電極208を形成し、その表面に、接合材である金属ナノ粒子ペースト209を塗布する(図7(b))。そして、図7(a)で作製した電子部品214と図7(b)で作製した基板215を、互いに接触する形で対向させる(図7(c))。その後、図7(c)で示した電子部品214と基板215を加熱することにより、第2の電極212とそれに塗布されている金属ナノ粒子ペースト209中の金属ナノ粒子が焼結し、それぞれ金属ナノ粒子焼結体213、210となり、電子部品214と基板215が接合され、図7(d)に示すような電子部品装置200を得る。なお、第2の電極213の形成目的は、電子部品電極203や基板電極208と、接合材210間での接合性を良好にすることである。   The manufacturing process will be described below with reference to FIG. First, an electronic component electrode 203 is formed on the electronic component element 202, and a second electrode 212 made of a metal nanoparticle paste is formed on the surface (FIG. 7 (a)). Next, a substrate electrode 208 is formed on the substrate element 207, and a metal nanoparticle paste 209, which is a bonding material, is applied to the surface (FIG. 7B). Then, the electronic component 214 manufactured in FIG. 7A and the substrate 215 manufactured in FIG. 7B are opposed to each other in a form of contact with each other (FIG. 7C). Thereafter, by heating the electronic component 214 and the substrate 215 shown in FIG. 7C, the second electrode 212 and the metal nanoparticles in the metal nanoparticle paste 209 applied to the second electrode 212 are sintered. The nanoparticle sintered bodies 213 and 210 are formed, and the electronic component 214 and the substrate 215 are joined to obtain the electronic component device 200 as shown in FIG. Note that the purpose of forming the second electrode 213 is to improve the bondability between the electronic component electrode 203 and the substrate electrode 208 and the bonding material 210.

特開2005-203468JP2005-203468

ところで、電極203の表面に形成した第2の電極である金属ナノ粒子ペースト212中の金属含有率が低くなると、有機物含有率が高くなる。有機物の含有率が高くなると、加熱時に有機物が表層から分離しにくくなり、残留した有機物は金属ナノ粒子ペースト212内部(特に電極203と金属ナノ粒子ペースト212の界面近傍)での金属ナノ粒子の焼結を阻害する。このため、金属含有率が低く、金属ナノ粒子ペースト212の厚みが厚い場合には、電子部品電極203と金属ナノ粒子焼結体213の間の接合信頼性および電気伝導性が低下する。     By the way, when the metal content rate in the metal nanoparticle paste 212 which is the second electrode formed on the surface of the electrode 203 becomes low, the organic matter content rate becomes high. When the content of the organic matter increases, the organic matter becomes difficult to separate from the surface layer during heating, and the remaining organic matter is burned out of the metal nanoparticles inside the metal nanoparticle paste 212 (particularly near the interface between the electrode 203 and the metal nanoparticle paste 212). Inhibits ligation. For this reason, when the metal content is low and the metal nanoparticle paste 212 is thick, the bonding reliability and electrical conductivity between the electronic component electrode 203 and the metal nanoparticle sintered body 213 are lowered.

一方、金属含有率が低くなっても、ペースト厚みが薄い時には、焼成時に有機物がペースト表層から分解されやすくなり、ペースト内部での金属ナノ粒子の焼結は阻害されない。このため、ペーストが薄膜化された場合は、接合信頼性および電気伝導性が向上するが、ペースト供給量の制御の難易度が高くなるという問題がある。   On the other hand, even when the metal content is low, when the paste thickness is thin, the organic matter is easily decomposed from the paste surface layer during firing, and the sintering of the metal nanoparticles inside the paste is not hindered. For this reason, when the paste is thinned, the bonding reliability and electrical conductivity are improved, but there is a problem that the degree of difficulty in controlling the paste supply amount is increased.

そこで、この発明の目的は、薄膜の、金属ナノ粒子焼結体からなる層を容易に形成し、接続信頼性、電気伝導性が高い電子部品、電子部品装置およびそれらの製造方法を提供しようとすることである。   Accordingly, an object of the present invention is to provide an electronic component, an electronic component device, and a method of manufacturing the same, in which a thin layer of a metal nanoparticle sintered body is easily formed, and connection reliability and electrical conductivity are high. It is to be.

上記問題点を解決するために、請求項1の電子部品は、基体と、前記基体上に形成された第1の電極と、前記基体の表面に形成され、前記第1の電極の側面と上面の少なくとも一方に接し、かつ前記第1の電極の周りを囲むように形成された壁と、前記第1の電極上に接合されている第2の電極を有する電子部品において、前記第2の電極は、金属ナノ粒子焼結体からなり、前記第1の電極と前記壁とに囲まれる空間内に形成され、かつバスタブ形状であることを特徴としている。   In order to solve the above problem, an electronic component according to claim 1 is formed on a base, a first electrode formed on the base, a surface of the base, and a side surface and an upper surface of the first electrode. An electronic component having a wall that is in contact with at least one of the first electrode and surrounding the first electrode; and a second electrode that is bonded onto the first electrode. Is made of a metal nanoparticle sintered body, is formed in a space surrounded by the first electrode and the wall, and has a bathtub shape.

また、請求項2の電子部品は、請求項1に記載された電子部品であって、前記第1の電極と前記壁とに囲まれる空間の金属ナノ粒子焼結体の最薄部の厚みが0.1〜0.6μmであり、かつ前記壁の高さが1.0μm以上であることを特徴としている。   An electronic component according to claim 2 is the electronic component according to claim 1, wherein the thickness of the thinnest part of the metal nanoparticle sintered body in the space surrounded by the first electrode and the wall is It is 0.1 to 0.6 μm, and the height of the wall is 1.0 μm or more.

また、請求項3の電子部品は、請求項1に記載された電子部品であって、前記壁が、パッシベーション膜からなることを特徴としている。   An electronic component according to a third aspect is the electronic component according to the first aspect, wherein the wall is made of a passivation film.

また、請求項4の電子部品は、請求項1に記載された電子部品であって、前記第1の電極がAlまたはAlの合金であることを特徴としている。   An electronic component according to a fourth aspect is the electronic component according to the first aspect, wherein the first electrode is Al or an alloy of Al.

また、請求項5の電子部品は、請求項1に記載された電子部品であって、前記金属ナノ粒子がCuであることを特徴としている。   An electronic component according to a fifth aspect is the electronic component according to the first aspect, wherein the metal nanoparticles are Cu.

また、請求項6の電子部品装置は、第1の電子部品と第2の電子部品とが接合部を介して電気的に接続されている電子部品装置において、前記第1の電子部品または前記第2の電子部品の少なくとも一方が、請求項1ないし5のうち少なくとも1項に記載の電子部品であることを特徴としている。   The electronic component device according to claim 6 is the electronic component device in which the first electronic component and the second electronic component are electrically connected via a joint portion. At least one of the two electronic components is the electronic component according to at least one of claims 1 to 5.

また、請求項7の電子部品装置は、請求項6に記載された電子部品装置であって、前記第1の電子部品の電極と前記第2の電子部品の電極とが対向した状態で接続されていることを特徴としている。   An electronic component device according to claim 7 is the electronic component device according to claim 6, wherein the electrodes of the first electronic component and the electrodes of the second electronic component are connected to face each other. It is characterized by having.

また、請求項8の電子部品の製造方法は基体を準備する工程と、前記基体上に形成された第1の電極と、前記基体の表面に形成され、前記第1の電極の側面と上面の少なくとも一方に接し、かつ前記第1の電極の周りを囲むように壁を形成する工程と、金属ナノ粒子と、分散剤と、有機溶媒とを含む金属ナノ粒子ペーストを準備する工程と、前記第1の電極と前記壁に囲まれた空間の体積よりも少ない量の前記金属ナノ粒子ペーストを前記第1の電極上に付与する工程と、前記金属ナノ粒子ペーストに含まれる分散剤と有機溶媒とが加熱により除去できる温度以上、前記金属ナノ粒子の融点未満の温度で加熱して前記金属ナノ粒子を焼結させることにより、前記第1の電極上に前記金属ナノ粒子を接合させる工程を有することを特徴としている。   According to another aspect of the invention, there is provided a method of manufacturing an electronic component comprising: a step of preparing a base; a first electrode formed on the base; a surface of the base; and a side surface and an upper surface of the first electrode. Forming a wall in contact with at least one and surrounding the first electrode; preparing a metal nanoparticle paste containing metal nanoparticles, a dispersant, and an organic solvent; Applying the metal nanoparticle paste in an amount less than the volume of the space surrounded by the electrode and the wall on the first electrode, a dispersant and an organic solvent contained in the metal nanoparticle paste, The metal nanoparticles are bonded onto the first electrode by heating the metal nanoparticles at a temperature not lower than the melting point of the metal nanoparticles and sintering the metal nanoparticles. Features .

また、請求項9の電子部品の製造方法は、請求項8に記載された電子部品の製造方法であって、前記第壁を形成した後に前記第1の電極の表面を洗浄することを特徴としている。   An electronic component manufacturing method according to claim 9 is the electronic component manufacturing method according to claim 8, wherein the surface of the first electrode is cleaned after the first wall is formed. Yes.

また、請求項10の電子部品装置の製造方法は、第1の電子部品の電極と第2の電子部品の電極との間にペースト状の接合材料を付与した後、前記ペースト状の接合材料を硬化させることにより前記第1の電子部品の電極と前記第2の電子部品の電極との接合部を形成する電子部品装置の製造方法において、前記第1の電子部品または前記第2の電子部品の少なくとも一方の製造方法が、請求項8〜9に記載の電子部品の製造方法であることを特徴としている。   According to a tenth aspect of the present invention, there is provided a method for manufacturing an electronic component device, comprising: applying a paste-like bonding material between an electrode of a first electronic component and an electrode of a second electronic component; In the manufacturing method of an electronic component device for forming a joint portion between the electrode of the first electronic component and the electrode of the second electronic component by curing, the first electronic component or the second electronic component At least one of the manufacturing methods is a method for manufacturing an electronic component according to any one of claims 8 to 9.

また、請求項11の電子部品装置の製造方法は、請求項10に記載された電子部品装置の製造方法であって、前記第1の電子部品の電極と前記第2の電子部品の電極とを対向させた状態で、前記第1の電子部品の電極と前記第2の電子部品の電極との接合部を形成することを特徴としている。   An electronic component device manufacturing method according to an eleventh aspect is the electronic component device manufacturing method according to the tenth aspect, in which the electrode of the first electronic component and the electrode of the second electronic component are combined. In a state of being opposed to each other, a junction portion between the electrode of the first electronic component and the electrode of the second electronic component is formed.

この発明に係る電子部品は、薄膜の、金属ナノ粒子焼結体からなる層を容易に形成することができ、電子部品の接続信頼性、電気伝導性を高めることができる。   In the electronic component according to the present invention, a thin layer of a metal nanoparticle sintered body can be easily formed, and the connection reliability and electrical conductivity of the electronic component can be improved.

なお、前記第1の電極と前記壁とに囲まれる空間の金属ナノ粒子焼結体の最薄部の厚みが0.1〜0.6μmであり、かつ前記壁の高さを1.0μm以上とした場合、前記金属ナノ粒子ペーストが前記空間の外に漏れ出しにくくなるため、安定してバスタブ形状が得られるため好ましい。なお、ここで言う高さとは、前記第1の電極の表面から測定したものである。   The thickness of the thinnest part of the metal nanoparticle sintered body in the space surrounded by the first electrode and the wall is 0.1 to 0.6 μm, and the height of the wall is 1.0 μm or more. In this case, the metal nanoparticle paste is difficult to leak out of the space, and thus a bathtub shape can be stably obtained. Note that the height referred to here is measured from the surface of the first electrode.

また、前記壁をパッシベーション膜により形成した場合、電子部品の製造工数を削減できるため好ましい。   Further, it is preferable that the wall is formed of a passivation film because the number of manufacturing steps of the electronic component can be reduced.

また、前記第1の電極をAlまたはAlの合金とした場合、前記第1の電極表面に存在するAl酸化物と前記第2の電極が強固に繋ぎ合わさり、より高い接合信頼性、電気伝導性が得られるため好ましい。   Further, when the first electrode is made of Al or an Al alloy, the Al oxide existing on the surface of the first electrode and the second electrode are firmly connected to each other, so that higher bonding reliability and electrical conductivity are achieved. Is preferable.

また、前記金属ナノ粒子ペースト中の金属ナノ粒子をCuとした場合、マイグレーションに対する耐性が向上し、より狭ピッチ実装に対応できるため好ましい。   Moreover, when the metal nanoparticle in the said metal nanoparticle paste is set to Cu, since the tolerance with respect to migration improves and it can respond to narrow pitch mounting, it is preferable.

また、この発明に係る電子部品装置は、前記第1の電子部品と前記第2の電子部品の間で高い接合信頼性を得ることができる。   Moreover, the electronic component device according to the present invention can obtain high joint reliability between the first electronic component and the second electronic component.

また、前記第1の電子部品の電極と前記第2の電子部品の電極とが対向した状態で接続されている場合、電子部品の単位面積当たりの電極数を高めて高密度実装や実装面積の縮小を図るに当たり、微細な接続部を形成する必要がある場合にも。十分な接合信頼性を確保できる。   In addition, when the electrodes of the first electronic component and the electrodes of the second electronic component are connected to face each other, the number of electrodes per unit area of the electronic component can be increased to achieve high-density mounting or mounting area. Even when it is necessary to form fine connection parts for reduction. Sufficient bonding reliability can be secured.

また、この発明に係る電子部品の製造方法は、薄膜の金属ナノ粒子層を容易に形成することができ、電子部品の接続信頼性、電気伝導性を高めることができる。   Moreover, the manufacturing method of the electronic component which concerns on this invention can form a thin metal nanoparticle layer easily, and can improve the connection reliability and electrical conductivity of an electronic component.

また、前記壁形成時に、前記第1の電極上に、前記壁の成分が付着し、前記第1の電極と前記金属ナノ粒子の接合を妨げることがある。この時、前記壁を形成した後に、前記第1の電極の表面を洗浄することが好ましい。   In addition, when the wall is formed, a component of the wall may adhere to the first electrode, and the bonding between the first electrode and the metal nanoparticles may be hindered. At this time, it is preferable to clean the surface of the first electrode after forming the wall.

また、この発明に係る電子部品装置の製造方法は、前記第1の電子部品と前記第2の電子部品の間で高い接合信頼性を得ることができる。   Moreover, the manufacturing method of the electronic component device according to the present invention can obtain high bonding reliability between the first electronic component and the second electronic component.

また、電子部品の単位面積当たりの電極数を高めて高密度実装や実装面積の縮小を図るに当たり、微細な接続部を形成する必要がある場合にも。十分な接合信頼性を確保できる。   In addition, when the number of electrodes per unit area of an electronic component is increased to achieve high-density mounting or reduction of the mounting area, it is also necessary to form fine connection portions. Sufficient bonding reliability can be secured.

本発明の電子部品装置の一例を示す断面図である。It is sectional drawing which shows an example of the electronic component apparatus of this invention. 本発明の電子部品装置の製造工程の一例を示す模式図である。It is a schematic diagram which shows an example of the manufacturing process of the electronic component apparatus of this invention. 本発明の電子部品装置の別の例を示す断面図である。It is sectional drawing which shows another example of the electronic component apparatus of this invention. 、 本発明の電子部品装置のさらに別の例を示す断面図である。FIG. 6 is a cross-sectional view showing still another example of the electronic component device of the present invention. 本発明の電子部品装置のさらに別の例を示す断面図である。It is sectional drawing which shows another example of the electronic component apparatus of this invention. 金属ナノペーストの供給量と供給厚の関係に対するパッシベーションの有無の影響を示すグラフである。It is a graph which shows the influence of the presence or absence of the passivation with respect to the relationship between the supply amount of metal nano paste, and supply thickness. 従来の電子部品装置の製造工程の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing process of the conventional electronic component apparatus.

以下に、この発明に係る電子部品、電子部品装置の実施形態およびその製造方法について、図1〜4に基づき詳細に説明する。   Hereinafter, an embodiment of an electronic component and an electronic component device according to the present invention and a manufacturing method thereof will be described in detail with reference to FIGS.

この発明に係る電子部品とそれを用いた電子部品装置として、図1にその断面図を示す。   FIG. 1 shows a cross-sectional view of an electronic component according to the present invention and an electronic component device using the electronic component.

この電子部品装置1は、ガラスエポキシ基板15上にSi系半導体チップ14がいわゆるフリップチップ実装されたものである。電子部品装置1の構造について説明すると、半導体素子2上にはAlからなる電子部品電極3(第1の電極)と、パッシベーション膜4と、パッシベーション膜4の一部を電子部品電極3上に乗り上げさせて形成した、高さが1.0μm以上の壁4aが配設されている。そして、前記電子部品電極3の表面に形成されたAl酸化物を主成分とする層11を介して、バスタブ形状であり、最薄部の厚みが0.1〜0.6μmであるCuナノ粒子焼結体(第2の電極13)が配設されている。一方、基板素子7にはSi系半導体チップ14との電気的導通を得るための、Au/Ni/Cu(最表層がAu、中層がNi、最下層がCu)の3層からなる基板電極8が配設されている。   In the electronic component device 1, a Si-based semiconductor chip 14 is mounted on a glass epoxy substrate 15 by so-called flip chip mounting. The structure of the electronic component device 1 will be described. On the semiconductor element 2, an electronic component electrode 3 (first electrode) made of Al, a passivation film 4, and a part of the passivation film 4 are mounted on the electronic component electrode 3. A wall 4a having a height of 1.0 μm or more is provided. Then, Cu nanoparticles having a bathtub shape and a thickness of the thinnest part of 0.1 to 0.6 μm are formed through the layer 11 mainly composed of Al oxide formed on the surface of the electronic component electrode 3. A sintered body (second electrode 13) is disposed. On the other hand, the substrate element 8 has three layers of Au / Ni / Cu (the outermost layer is Au, the middle layer is Ni, and the lowermost layer is Cu) for obtaining electrical continuity with the Si-based semiconductor chip 14. Is arranged.

上記の電子部品電極3と基板電極8とは、対向した状態で、Cuナノ粒子焼結体10により接合されている。ここで、Cuナノ粒子焼結体からなる第2の電極13の最薄部の厚みを0.1〜0.6μmとすることで、接続信頼性、電気伝導性をより向上させることができる。このとき、第2の電極13の最薄部の厚みが0.1μm未満の場合には、膜に欠陥ができ、電子部品電極3が一部露出してしまい、接続信頼性、電気伝導性が阻害される。一方、第2の電極13の最薄部の厚みが0.6μmより大きくなると、前記Cuナノ粒子焼結体内部が焼結しにくくなり、接続信頼性、電気伝導性が阻害される。   The electronic component electrode 3 and the substrate electrode 8 are bonded to each other by the Cu nanoparticle sintered body 10 while facing each other. Here, by setting the thickness of the thinnest part of the second electrode 13 made of the Cu nanoparticle sintered body to 0.1 to 0.6 μm, the connection reliability and the electrical conductivity can be further improved. At this time, when the thickness of the thinnest part of the second electrode 13 is less than 0.1 μm, the film is defective, and the electronic component electrode 3 is partially exposed, and the connection reliability and electrical conductivity are improved. Be inhibited. On the other hand, when the thickness of the thinnest part of the second electrode 13 is larger than 0.6 μm, the inside of the Cu nanoparticle sintered body becomes difficult to sinter, and connection reliability and electrical conductivity are hindered.

また、中央部の薄膜化は次に示す作用によるものである。電極上に、Cuナノ粒子焼結体からなる第2の電極13の前駆体であるCuナノ粒子ペーストが電極上に供給された際に、Cuナノ粒子ペーストは壁面に濡れ上がろうとする。この時、Cuナノ粒子ペーストは周辺部の乾燥体積を補うため、中央部から周辺部の方向にペーストが搬送され、中央部の層の厚みが薄くなり、バスタブ形状になる。   The thinning of the central part is due to the following action. When a Cu nanoparticle paste, which is a precursor of the second electrode 13 made of a Cu nanoparticle sintered body, is supplied onto the electrode, the Cu nanoparticle paste tends to wet onto the wall surface. At this time, since the Cu nanoparticle paste compensates for the dry volume of the peripheral portion, the paste is transported from the central portion toward the peripheral portion, and the thickness of the central layer is reduced, resulting in a bathtub shape.

また、前記バスタブ形状の一例としては、断面が凹形状、V形状であるものが挙げられる。   Moreover, as an example of the said bathtub shape, that whose cross section is concave shape and V shape is mentioned.

次いで、この発明に係る電子部品および電子部品装置の製造方法の一例として図1に示したフリップチップ実装による電子部品装置の製造工程を表したものを図2に示す。   Next, FIG. 2 shows a manufacturing process of the electronic component device by flip chip mounting shown in FIG. 1 as an example of the method of manufacturing the electronic component and the electronic component device according to the present invention.

まず、図2(a)で示すように、半導体素子2上にAlからなる電子部品電極3を配設する。次にパッシベーション膜4を、電子部品電極3に対応する部分は開口するように配設し、パッシベーション膜4の一部を電子部品電極3上に乗り上げさせ、電子部品電極3の周囲を取り囲むように高さが1.0μm以上の壁4aを形成する。さらに、電子部品電極3上に、Cuナノ粒子、分散剤、有機溶媒からなるCuナノ粒子ペースト12を、電子部品電極3と壁4aに囲まれた空間の体積より少ない量で、インクジェット工法を用いて付与する。電子部品電極3の表面はAl酸化膜11で覆われているため、実際にはCuナノ粒子ペースト12はAl酸化膜11を介して電子部品電極3上に付与されることになる。   First, as shown in FIG. 2A, an electronic component electrode 3 made of Al is disposed on the semiconductor element 2. Next, the passivation film 4 is disposed so that the portion corresponding to the electronic component electrode 3 is opened, and a part of the passivation film 4 is placed on the electronic component electrode 3 so as to surround the periphery of the electronic component electrode 3. The wall 4a having a height of 1.0 μm or more is formed. Furthermore, an ink jet method is used on the electronic component electrode 3 with a Cu nanoparticle paste 12 made of Cu nanoparticles, a dispersant, and an organic solvent in an amount smaller than the volume of the space surrounded by the electronic component electrode 3 and the wall 4a. To grant. Since the surface of the electronic component electrode 3 is covered with the Al oxide film 11, the Cu nanoparticle paste 12 is actually applied onto the electronic component electrode 3 through the Al oxide film 11.

次に図2(b)で、Si系半導体チップ14を、Cuナノ粒子ペースト12に含まれる分散剤と有機溶媒とが加熱により除去できる温度以上、金属ナノ粒子の融点未満の温度で、オーブンにて加熱することにより、電子部品電極3上にバスタブ形状のCuナノ粒子焼結体13を形成する。   Next, in FIG. 2B, the Si-based semiconductor chip 14 is placed in an oven at a temperature that is higher than the temperature at which the dispersant and the organic solvent contained in the Cu nanoparticle paste 12 can be removed by heating and lower than the melting point of the metal nanoparticles. The bathtub-shaped Cu nanoparticle sintered body 13 is formed on the electronic component electrode 3 by heating.

この段階で、電子部品電極3と接している最薄部の厚みが0.1〜0.6μmとなり、Cuナノ粒子が焼結しやすくなり、Cuナノ粒子焼結体13と電子部品電極3は強固に接合されることになり、以後の基板電極との接合の際に、高い接合信頼性、電気伝導性を得ることができる。   At this stage, the thickness of the thinnest part in contact with the electronic component electrode 3 becomes 0.1 to 0.6 μm, Cu nanoparticles are easily sintered, and the Cu nanoparticle sintered body 13 and the electronic component electrode 3 are It is strongly bonded, and high bonding reliability and electrical conductivity can be obtained in the subsequent bonding with the substrate electrode.

次に図2(c)に示すように、基板素子7上にAu/Ni/Cu(最表層がAu、中層がNi、最下層がCu)の3層からなる基板電極8を配設する。次に基板電極8上に、Cuナノ粒子ペースト9を、インクジェット工法を用いて付与する。次に、図2(d)で示すように、図2(b)の工程で準備されたSi系半導体チップ14の上下(図面上で上下)を反転させ、図2(c)の工程で準備されたガラスエポキシ基板15に対し、位置合わせし、載置する。   Next, as shown in FIG. 2C, a substrate electrode 8 composed of three layers of Au / Ni / Cu (the outermost layer is Au, the middle layer is Ni, and the lowermost layer is Cu) is disposed on the substrate element 7. Next, a Cu nanoparticle paste 9 is applied on the substrate electrode 8 using an ink jet method. Next, as shown in FIG. 2D, the upper and lower sides (up and down in the drawing) of the Si-based semiconductor chip 14 prepared in the step of FIG. 2B are reversed and prepared in the step of FIG. The glass epoxy substrate 15 is aligned and placed.

次に図2(e)で示すように、電子部品電極3と基板電極8が対向するように載置したSi系半導体チップ14とガラスエポキシ基板15とを重ね合わせ、その状態で、オーブンにて加熱してCuナノ粒子ペースト9を焼結させ、電子部品電極3と基板電極8とを接合する接合部(Cuナノ粒子焼結体10)を形成する。   Next, as shown in FIG. 2 (e), the Si-based semiconductor chip 14 and the glass epoxy substrate 15 placed so that the electronic component electrode 3 and the substrate electrode 8 face each other are overlapped, and in that state, By heating, the Cu nanoparticle paste 9 is sintered, and a joining portion (Cu nanoparticle sintered body 10) for joining the electronic component electrode 3 and the substrate electrode 8 is formed.

以上の工程を経て、接合信頼性および電気伝導性の高い電子部品装置を得ることができる。   Through the above steps, an electronic component device having high bonding reliability and high electrical conductivity can be obtained.

なお、この実施形態に示した電子部品、それを用いた電子部品装置の実施形態およびその製造方法は一例であって、これ以外にもこの発明内容の範囲内であれば種々の変形を行なうことは差し支えない。   The embodiment of the electronic component shown in this embodiment, the embodiment of the electronic component device using the electronic component, and the manufacturing method thereof are merely examples, and other various modifications may be made within the scope of the present invention. Is fine.

例えば、Si系半導体チップ14は、GaAs系半導体チップや表面弾性波素子であってもよい。ガラスエポキシ基板15は、低温焼成可能なセラミック基板であってもよい。   For example, the Si semiconductor chip 14 may be a GaAs semiconductor chip or a surface acoustic wave element. The glass epoxy substrate 15 may be a ceramic substrate that can be fired at a low temperature.

また、電子部品電極3は、Al−1Cu、Al−1Si、Al−1Si−0.5Cuなどを用いることもできる。また電子部品電極3の少なくとも表面はAlまたはAl合金であるような場合、すなわちAuやCuのバンプが形成されている上に、Alまたは上記のようなAl合金がスパッタリングもしくは蒸着などの方法により膜状に形成されている場合にも、その表面にはAl酸化膜が存在しているので、この発明を効果的に適用することができる。基板電極8はAu、Ag、Cuなどを単層構造として用いても良く、ビア構造となっていても良い。   Moreover, Al-1Cu, Al-1Si, Al-1Si-0.5Cu etc. can also be used for the electronic component electrode 3. FIG. Further, when at least the surface of the electronic component electrode 3 is made of Al or an Al alloy, that is, on which Au or Cu bumps are formed, Al or the above Al alloy is formed into a film by a method such as sputtering or vapor deposition. Even when formed in the shape, an Al oxide film is present on the surface thereof, so that the present invention can be applied effectively. The substrate electrode 8 may use Au, Ag, Cu or the like as a single layer structure, or may have a via structure.

また、この実施形態ではパッシベーション膜4の一部を、それぞれ電子部品電極3に乗り上げさせて壁4aを形成してあるが、異なる構成部材により別途壁を形成しても良い。   Further, in this embodiment, a part of the passivation film 4 is respectively placed on the electronic component electrode 3 to form the wall 4a. However, a separate wall may be formed from different components.

また、電子部品電極3表面にパッシベーション膜の残渣が付着することがあるが、その際にはUV洗浄やプラズマ洗浄により除去することで、電極上での不濡れを防止することができる。   Further, a passivation film residue may adhere to the surface of the electronic component electrode 3. In this case, removal by UV cleaning or plasma cleaning can prevent non-wetting on the electrode.

また、金属ナノ粒子としては、Ag−Pd合金などのAg合金ナノ粒子や、Auナノ粒子などを用いても良い。例えば、AgにPdが15重量%程度添加されているAg−Pd合金を用いた場合、Cuを用いた場合と同様、電子部品装置の使用環境によっては発生する可能性のあるAgマイグレーションを効果的に抑制することができる。   Further, as the metal nanoparticles, Ag alloy nanoparticles such as an Ag—Pd alloy, Au nanoparticles, or the like may be used. For example, when an Ag—Pd alloy in which about 15 wt% of Pd is added to Ag is used, Ag migration that may occur depending on the use environment of the electronic component device is effective as in the case of using Cu. Can be suppressed.

また、金属ナノ粒子ペーストの付与はインクジェット工法の他、スクリーン印刷または転写など、電極面積に合わせた方法で行なうことができる。特に微量の金属ナノ粒子ペーストの付与を行なう際には、吐出量が高精度に制御できるマイクロディスペンサやインクジェット装置を用いることが好ましい。   Moreover, the application of the metal nanoparticle paste can be performed by a method according to the electrode area, such as screen printing or transfer, in addition to the inkjet method. In particular, when a small amount of metal nanoparticle paste is applied, it is preferable to use a microdispenser or an ink jet apparatus capable of controlling the discharge amount with high accuracy.

また、金属ナノ粒子ペーストを焼結させる際の加熱装置としては、オーブンの他、リフロー炉やホットプレートを用いるなどして、電子部品の形態や処理数量に合わせたものを用いることができる。   Moreover, as a heating apparatus at the time of sintering the metal nanoparticle paste, an apparatus other than an oven, a reflow furnace, a hot plate, or the like can be used according to the form of electronic components or the processing quantity.

また、この実施形態では基板素子7の基板電極8側にフリップチップ実装によって電子部品2と基板7とを接合するのに十分な量以上で、隣接する電極同士を接続してしまう量未満のCuナノ粒子ペースト9を付与するようにしたが、電子部品電極3側、または基板電極8側と電子部品電極3側との双方に付与するようにしても良い。   Further, in this embodiment, the Cu is less than an amount sufficient to connect the electronic components 2 and the substrate 7 to each other by flip chip mounting on the substrate electrode 8 side of the substrate element 7 and less than the amount that connects adjacent electrodes. Although the nanoparticle paste 9 is applied, it may be applied to the electronic component electrode 3 side or both the substrate electrode 8 side and the electronic component electrode 3 side.

また、基板7上にはレジスト膜や、レジスト膜の一部を、基板電極8の周りを囲むように、乗り上げさせて形成された壁が設けられていても良い。   Further, a wall formed by riding a resist film or a part of the resist film on the substrate 7 so as to surround the substrate electrode 8 may be provided.

なお、この実施形態では、基板電極8側にも接合材料として金属ナノ粒子ペースト9を付与したが、基板電極8の材質として表面に酸化膜が形成されにくいものが用いられている場合は、接合材料に高い活性度を必要としないので、例えばはんだペーストや導電性接着剤など、金属ナノ粒子ペースト以外に通常用いられる接合材料を用いても良い。   In this embodiment, the metal nanoparticle paste 9 is also applied as the bonding material to the substrate electrode 8 side. However, if the material of the substrate electrode 8 that is difficult to form an oxide film on the surface is used, the bonding is performed. Since the material does not require high activity, a commonly used bonding material other than the metal nanoparticle paste, such as a solder paste or a conductive adhesive, may be used.

また、Si系半導体チップ14およびガラスエポキシ基板15はそれぞれ個片の状態で接合するのではなく、分割前のウエハ状態および集合基板状態で接合し、その後分割して電子部品装置1としても良い。そのようにすることで生産性を向上させることができる。   Further, the Si-based semiconductor chip 14 and the glass epoxy substrate 15 may be joined in the wafer state and the assembled substrate state before the division, and then divided into the electronic component device 1 instead of being joined in the individual state. By doing so, productivity can be improved.

また、製造された電子部品装置1のSi系半導体チップ14とガラスエポキシ基板15との間にアンダーフィル樹脂を充填して、硬化させる工程を追加しても良い。この工程追加により、この発明の電子部品装置1は、実際に使用される時に接続部に生じる歪み(Si系半導体チップ14とガラスエポキシ基板15との線膨張係数差に起因する歪み)を低減することができ、耐環境性能をより高めることができる。Si系半導体チップ14として分割前のウエハやガラスエポキシ基板15として集合基板を使用した場合には、接合して樹脂充填した後、電子部品装置1を個片に分離する工程を設けてもよい。   Moreover, you may add the process of filling underfill resin between the Si type semiconductor chip 14 of the manufactured electronic component apparatus 1, and the glass epoxy board | substrate 15, and hardening it. By adding this process, the electronic component device 1 of the present invention reduces distortion (strain caused by the difference in linear expansion coefficient between the Si-based semiconductor chip 14 and the glass epoxy substrate 15) generated in the connection portion when actually used. Environmental resistance can be further improved. In the case where an undivided wafer is used as the Si-based semiconductor chip 14 or a collective substrate is used as the glass epoxy substrate 15, a step of separating the electronic component device 1 into individual pieces after bonding and resin filling may be provided.

図3と図4と図5にこの発明の別の実施形態を示す。図3の実施形態はSi系半導体チップ114をフェースアップでガラスエポキシ基板115へ実装した構造の電子部品装置100である。半導体素子102の上面には電子部品電極103とパッシベーション膜104が配設されており、パッシベーション膜104の一部が電子部品電極103に乗り上げるような形で壁104aが形成されている。     3, 4 and 5 show another embodiment of the present invention. The embodiment of FIG. 3 is an electronic component device 100 having a structure in which a Si-based semiconductor chip 114 is mounted face-up on a glass epoxy substrate 115. An electronic component electrode 103 and a passivation film 104 are disposed on the upper surface of the semiconductor element 102, and a wall 104 a is formed so that a part of the passivation film 104 runs over the electronic component electrode 103.

そして電子部品電極103と壁104aに囲まれた空間にバスタブ形状のCuナノ粒子焼結体113が形成されている。  A bathtub-shaped Cu nanoparticle sintered body 113 is formed in a space surrounded by the electronic component electrode 103 and the wall 104a.

ここで、電子部品電極103はAlからなっており、その表面はAl酸化膜111で覆われており、Cuナノ粒子焼結体113と電子部品電極103は、Al酸化膜111を介して接合されることになる。   Here, the electronic component electrode 103 is made of Al, and the surface thereof is covered with an Al oxide film 111, and the Cu nanoparticle sintered body 113 and the electronic component electrode 103 are bonded via the Al oxide film 111. Will be.

基板素子107の上面にはAu/Ni/Cu(最表層がAu、中層がNi、最下層がCu)の3層からなる基板電極108が配設されており、Cuナノ粒子焼結体110を介して電子部品電極103と電気的に導通している。このとき、Cuナノ焼結体110は、電子部品側面に設けられた樹脂116の表面を経路としている。   On the upper surface of the substrate element 107, a substrate electrode 108 composed of three layers of Au / Ni / Cu (the outermost layer is Au, the middle layer is Ni, and the lowermost layer is Cu) is disposed, and the Cu nanoparticle sintered body 110 is disposed. Through the electronic component electrode 103. At this time, the Cu nano-sintered body 110 is routed through the surface of the resin 116 provided on the side surface of the electronic component.

この電子部品装置100は、フリップチップの代わりにフェースアップで予めCuナノ粒子焼結体を接合したSi系半導体チップ114をフェースアップでガラスエポキシ基板115へ戴置した後、加熱条件などは実施例1と同様にして製造することができる。   In this electronic component device 100, a Si-based semiconductor chip 114 to which a Cu nanoparticle sintered body is bonded in advance face-up instead of a flip chip is placed on the glass epoxy substrate 115 face-up. 1 in the same manner.

また、この実施形態では、パッシベーション膜を電子部品電極に乗り上げさせて壁を形成したが、図4に示すように、電子部品電極103の側面のみに接する、金属ナノ粒子ペーストが濡れ上がりやすい素材からなる壁104bを形成しても良い。   Further, in this embodiment, the passivation film is placed on the electronic component electrode to form the wall. However, as shown in FIG. 4, the metal nanoparticle paste that touches only the side surface of the electronic component electrode 103 is easily wetted. A wall 104b may be formed.

また、電子部品電極103と基板電極108は、図5に示すようにボンディグワイヤ117を介したワイヤボンディング工法により導通させてもよい。   Further, the electronic component electrode 103 and the substrate electrode 108 may be made conductive by a wire bonding method via a bonding wire 117 as shown in FIG.

この発明におけるさらに具体的な実施例について以下に説明する。   More specific embodiments of the present invention will be described below.

表1に示す電子部品と基板を用意した。表2に示したCuナノ粒子供給量と供給後の電子部品電極上でのCuナノ粒子ペーストの厚みの関係を図6に示す。   Electronic components and substrates shown in Table 1 were prepared. FIG. 6 shows the relationship between the Cu nanoparticle supply amount shown in Table 2 and the thickness of the Cu nanoparticle paste on the electronic component electrode after supply.

パッシベーションにより壁を形成した場合は、幅広いCuナノ粒子ペースト供給量の範囲において、Cuナノ粒子ペースト付与後の厚みが安定して薄膜化されていることを示している。 このとき、電極と前記壁とに囲まれる空間の金属ナノ粒子焼結体の最薄部の厚みは0.1μmであり前記壁の高さは1.0μmとなっている。   When the wall is formed by passivation, it is shown that the thickness after application of the Cu nanoparticle paste is stably reduced in a wide range of Cu nanoparticle paste supply amount. At this time, the thickness of the thinnest part of the sintered metal nanoparticle in the space surrounded by the electrode and the wall is 0.1 μm, and the height of the wall is 1.0 μm.

上記のようにしてCuナノ粒子ペーストが付与された電子部品を、加熱温度100〜300℃、加熱時間1〜60分、還元雰囲気という条件で加熱しCuナノ粒子ペーストを焼結させた。   The electronic component to which the Cu nanoparticle paste was applied as described above was heated under the conditions of a heating temperature of 100 to 300 ° C., a heating time of 1 to 60 minutes, and a reducing atmosphere to sinter the Cu nanoparticle paste.

次に、基板の基板電極上にフリップチップ実装によって電子部品と基板とを接合するのに十分な量以上で、隣接する電極同士を接続してしまう量未満のCuナノ粒子ペーストを付与する。   Next, a Cu nanoparticle paste is applied on the substrate electrode of the substrate in an amount more than an amount sufficient to join the electronic component and the substrate by flip chip mounting and less than the amount that connects the adjacent electrodes.

次に、電子部品の上下を反転させ、基板電極上に所定量のCuナノ粒子ペーストが付与された基板に対して位置合わせする。   Next, the electronic component is turned upside down and aligned with a substrate on which a predetermined amount of Cu nanoparticle paste is applied on the substrate electrode.

次に電子部品と基板とを重ね合わせ、その状態で加熱温度100〜300℃、加熱時間1〜60分、還元雰囲気という条件で加熱し、Cuナノ粒子ペーストを焼結させ、電子部品電極と基板電極とを接合する接合部(Cuナノ粒子焼結体)を形成する。   Next, the electronic component and the substrate are overlapped, and in this state, heating is performed under the conditions of a heating temperature of 100 to 300 ° C., a heating time of 1 to 60 minutes, and a reducing atmosphere to sinter the Cu nanoparticle paste, and the electronic component electrode and the substrate A joint (Cu nanoparticle sintered body) for joining the electrodes is formed.

1、100、200 電子部品装置(フリップチップ実装構造)
2、102、 半導体素子
3、103、203 電子部品電極(第1の電極)
4、104 パッシベーション膜
4a、104a パッシベーション膜からなる壁
7、107、207 基板素子
8、108、208 基板電極
9、209 金属ナノ粒子ペースト(接合剤)
10、110、210 金属ナノ粒子焼結体(接合剤)
11、111 Al酸化物膜
12、212 金属ナノ粒子ペースト(第2の電極)
13、113、213 金属ナノ粒子焼結体(第2の電極)
14、114 Si系半導体チップ
15、115 ガラスエポキシ基板
104b 金属ナノ粒子ペーストが濡れ上がりやすい素材からなる壁
116 樹脂
117 ボンディングワイヤ
202 電子部品素子
214 電子部品
215 基板
1, 100, 200 Electronic component device (flip chip mounting structure)
2, 102, semiconductor element 3, 103, 203 Electronic component electrode (first electrode)
4, 104 Passivation film 4a, 104a Wall made of passivation film 7, 107, 207 Substrate element 8, 108, 208 Substrate electrode 9, 209 Metal nanoparticle paste (bonding agent)
10, 110, 210 Metal nanoparticle sintered body (bonding agent)
11, 111 Al oxide film 12, 212 Metal nanoparticle paste (second electrode)
13, 113, 213 Metal nanoparticle sintered body (second electrode)
14, 114 Si-based semiconductor chip 15, 115 Glass epoxy substrate 104b Wall made of a material in which the metal nanoparticle paste easily wets 116 Resin 117 Bonding wire 202 Electronic component element 214 Electronic component 215 Substrate

Claims (11)

基体と、前記基体上に形成された第1の電極と、前記基体の表面に形成され、前記第1の電極の側面と上面の少なくとも一方に接し、かつ前記第1の電極の周りを囲むように形成された壁と、前記第1の電極上に接合されている第2の電極を有する電子部品において、前記第2の電極は、金属ナノ粒子焼結体からなり、前記第1の電極と前記壁とに囲まれる空間内に形成され、かつバスタブ形状であることを特徴とする電子部品。   A base, a first electrode formed on the base, and formed on a surface of the base, in contact with at least one of a side surface and an upper surface of the first electrode, and surrounding the first electrode In the electronic component having the wall formed on the first electrode and the second electrode joined on the first electrode, the second electrode is made of a metal nanoparticle sintered body, and the first electrode An electronic component formed in a space surrounded by the wall and having a bathtub shape. 前記第1の電極と前記壁とに囲まれる空間の金属ナノ粒子焼結体の最薄部の厚みが0.1〜0.6μmであり、かつ前記壁の高さが1.0μm以上であることを特徴とする請求項1に記載の電子部品。   The thickness of the thinnest part of the metal nanoparticle sintered body in the space surrounded by the first electrode and the wall is 0.1 to 0.6 μm, and the height of the wall is 1.0 μm or more. 2. The electronic component according to claim 1, wherein 前記壁は、パッシベーション膜からなることを特徴とする請求項1に記載の電子部品。  The electronic component according to claim 1, wherein the wall is made of a passivation film. 前記第1の電極はAlまたはAlの合金であることを特徴とする請求項1に記載の電子部品。   2. The electronic component according to claim 1, wherein the first electrode is Al or an Al alloy. 前記金属ナノ粒子焼結体を構成する金属ナノ粒子がCuであることを特徴とする請求項1に記載の電子部品。   2. The electronic component according to claim 1, wherein the metal nanoparticles constituting the metal nanoparticle sintered body are Cu. 第1の電子部品と第2の電子部品とが接合部を介して電気的に接続されている電子部品装置において、前記第1の電子部品または前記第2の電子部品の少なくとも一方が、請求項1ないし5のうち少なくとも1項に記載の電子部品であることを特徴とする電子部品装置。   In the electronic component device in which the first electronic component and the second electronic component are electrically connected via a joint, at least one of the first electronic component or the second electronic component is claimed. An electronic component device according to claim 1, wherein the electronic component device is at least one of 1 to 5. 前記第1の電子部品の電極と前記第2の電子部品の電極とが対向した状態で接続されていることを特徴とする、請求項6に記載の電子部品装置。   The electronic component device according to claim 6, wherein the electrode of the first electronic component and the electrode of the second electronic component are connected to face each other. 基体を準備する工程と、
基体と、前記基体上に形成された第1の電極と、前記基体の表面に形成され、前記第1の電極の側面と上面の少なくとも一方に接し、かつ前記第1の電極の周りを囲むように壁を形成する工程と、
金属ナノ粒子と、分散剤と、有機溶媒とを含む金属ナノ粒子ペーストを準備する工程と、前記第1の電極と前記壁に囲まれた空間の体積よりも少ない量の前記金属ナノ粒子ペーストを前記第1の電極上に付与する工程と、
前記金属ナノ粒子ペーストに含まれる分散剤と有機溶媒とが加熱により除去できる温度以上、前記金属ナノ粒子の融点未満の温度で加熱して前記金属ナノ粒子を焼結させることにより、前記第1の電極上に前記金属ナノ粒子を接合させる工程を有することを特徴とする、電子部品の製造方法。
Preparing a substrate;
A base, a first electrode formed on the base, and formed on a surface of the base, in contact with at least one of a side surface and an upper surface of the first electrode, and surrounding the first electrode Forming a wall in the
Preparing a metal nanoparticle paste comprising metal nanoparticles, a dispersant, and an organic solvent; and a volume of the metal nanoparticle paste that is less than the volume of the space surrounded by the first electrode and the wall Applying on the first electrode;
The first and second metal nanoparticles are sintered by heating at a temperature not lower than the melting point of the metal nanoparticles above the temperature at which the dispersant and the organic solvent contained in the metal nanoparticle paste can be removed by heating. The manufacturing method of an electronic component characterized by having the process of joining the said metal nanoparticle on an electrode.
前記壁を形成した後に前記第1の電極の表面を洗浄することを特徴とする請求項8に記載の電子部品の製造方法。   The method of manufacturing an electronic component according to claim 8, wherein the surface of the first electrode is washed after the wall is formed. 第1の電子部品の電極と第2の電子部品の電極との間にペースト状の接合材料を付与した後、前記ペースト状の接合材料を硬化させることにより前記第1の電子部品の電極と前記第2の電子部品の電極との接合部を形成する電子部品装置の製造方法において、前記第1の電子部品または前記第2の電子部品の少なくとも一方の製造方法が、請求項8〜9に記載の電子部品の製造方法であることを特徴とする、電子部品装置の製造方法。   After applying the paste-like bonding material between the electrode of the first electronic component and the electrode of the second electronic component, the electrode of the first electronic component and the electrode are cured by curing the paste-like bonding material In the manufacturing method of the electronic component apparatus which forms a junction part with the electrode of a 2nd electronic component, the manufacturing method of at least one of the said 1st electronic component or the said 2nd electronic component is Claim 8-9. A method for manufacturing an electronic component device, comprising: 前記第1の電子部品の電極と前記第2の電子部品の電極とを対向させた状態で、前記第1の電子部品の電極と前記第2の電子部品の電極との接合部を形成することを特徴とする、請求項10に記載の電子部品装置の製造方法。    Forming a joint between the electrode of the first electronic component and the electrode of the second electronic component in a state where the electrode of the first electronic component and the electrode of the second electronic component are opposed to each other; The manufacturing method of the electronic component apparatus of Claim 10 characterized by these.
JP2009128684A 2009-05-28 2009-05-28 Electronic component, electronic component device using the same and method of manufacturing them Pending JP2010278193A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009128684A JP2010278193A (en) 2009-05-28 2009-05-28 Electronic component, electronic component device using the same and method of manufacturing them

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009128684A JP2010278193A (en) 2009-05-28 2009-05-28 Electronic component, electronic component device using the same and method of manufacturing them

Publications (1)

Publication Number Publication Date
JP2010278193A true JP2010278193A (en) 2010-12-09

Family

ID=43424894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009128684A Pending JP2010278193A (en) 2009-05-28 2009-05-28 Electronic component, electronic component device using the same and method of manufacturing them

Country Status (1)

Country Link
JP (1) JP2010278193A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109644559A (en) * 2016-08-30 2019-04-16 株式会社村田制作所 Electronic device and multilayer ceramic substrate
WO2021256040A1 (en) * 2020-06-15 2021-12-23 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device and method for producing same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109644559A (en) * 2016-08-30 2019-04-16 株式会社村田制作所 Electronic device and multilayer ceramic substrate
JPWO2018042846A1 (en) * 2016-08-30 2019-06-24 株式会社村田製作所 Electronic device and multilayer ceramic substrate
WO2021256040A1 (en) * 2020-06-15 2021-12-23 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device and method for producing same

Similar Documents

Publication Publication Date Title
US9111782B2 (en) Solderless die attach to a direct bonded aluminum substrate
JP4629016B2 (en) Power module substrate with heat sink, method for manufacturing power module substrate with heat sink, and power module
JP5367914B2 (en) Wiring substrate, manufacturing method thereof, and semiconductor device
CN102856219B (en) For metal surface being attached to method and the packaging module of carrier
KR101890085B1 (en) A method of manufacturing a package and a package manufactured by the method
TW200303588A (en) Semiconductor device and its manufacturing method
US20150123263A1 (en) Two-step method for joining a semiconductor to a substrate with connecting material based on silver
JP2009302511A (en) Bump, manufacturing method for the bump, and mounting method for substrate having the bump formed
US9640511B2 (en) Method for producing a circuit carrier arrangement having a carrier which has a surface formed by an aluminum/silicon carbide metal matrix composite material
JP4859996B1 (en) Method for forming metal wiring by transfer substrate for forming metal wiring
TW201340795A (en) Transfer substrate for forming metallic wiring and method for forming metallic wiring with the use of the transfer substrate
JPWO2015114987A1 (en) Power module substrate and power module using the same
JPWO2014027418A1 (en) Electronic component and method for manufacturing electronic component
JP5977180B2 (en) Wiring board
JP5625578B2 (en) Circuit module
JP2008060287A (en) Terminal electrode and electronic part
JP2004146731A (en) Manufacturing method of multilayer wiring substrate
JP4599121B2 (en) Electrical relay plate
JP2010278193A (en) Electronic component, electronic component device using the same and method of manufacturing them
JP5560713B2 (en) Electronic component mounting method, etc.
JP5414622B2 (en) Semiconductor mounting substrate and mounting structure using the same
JP3618060B2 (en) Wiring board for mounting semiconductor element and semiconductor device using the same
JP2013165156A (en) Electrode assembly and manufacturing method of the same
JP6154110B2 (en) Mounting board
CN109848497A (en) A kind of low-temperature sintering method for large-area substrates encapsulation