KR101198848B1 - Semiconductor Device and Fabricating Method thereof - Google Patents

Semiconductor Device and Fabricating Method thereof Download PDF

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Publication number
KR101198848B1
KR101198848B1 KR20100132704A KR20100132704A KR101198848B1 KR 101198848 B1 KR101198848 B1 KR 101198848B1 KR 20100132704 A KR20100132704 A KR 20100132704A KR 20100132704 A KR20100132704 A KR 20100132704A KR 101198848 B1 KR101198848 B1 KR 101198848B1
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KR
South Korea
Prior art keywords
electrode layer
substrate
semiconductor device
insulating layer
semiconductor chip
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Application number
KR20100132704A
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Korean (ko)
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KR20120071102A (en
Inventor
남기명
송태환
전영철
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(주)포인트엔지니어링
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Priority to KR20100132704A priority Critical patent/KR101198848B1/en
Publication of KR20120071102A publication Critical patent/KR20120071102A/en
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Publication of KR101198848B1 publication Critical patent/KR101198848B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13062—Junction field-effect transistor [JFET]

Abstract

Disclosed is a semiconductor device and a method of manufacturing the same, which can improve heat dissipation efficiency.
For example, a semiconductor device according to the present invention may include a substrate including a substrate member formed of aluminum or an aluminum alloy, an insulating layer formed by being anodized on an upper surface of the substrate member, and an electrode layer formed on the insulating layer; A semiconductor chip formed on the substrate; Disclosed is a semiconductor device including a conductive member connecting an electrode of the semiconductor chip with the electrode terminal.

Description

Semiconductor device and fabrication method

The present invention relates to a semiconductor device and a method of manufacturing the same.

Modern electronic products are required to be small in size but high in performance. As a result, semiconductor devices, which are essential components for electronic products, also require miniaturization and high performance.

By the way, the semiconductor device has been miniaturized as the semiconductor integrated technology is improved, but in order to increase the performance, the heat dissipation function is required to be improved. This is because if the heat generated from the chip of the semiconductor device cannot be easily radiated, the performance of the semiconductor device may be degraded or the semiconductor chip may be damaged. In particular, in the case of power semiconductor devices, heat radiation is more important because a large amount of current flows.

The present invention provides a semiconductor device and a method of manufacturing the same that can improve heat dissipation efficiency.

A semiconductor device according to the present invention includes a substrate comprising a substrate member formed of aluminum or an aluminum alloy, an insulating layer formed by anodizing on an upper surface of the substrate member, and an electrode layer formed on the insulating layer; A semiconductor chip formed on the substrate; It may include a conductive member for connecting the electrode of the semiconductor chip with the electrode terminal.

Here, the substrate may further include a solder resist surrounding the edge of the electrode layer.

The conductive member may be formed between the electrode layer and the semiconductor chip to include an electrode terminal electrically connected to one of the electrodes of the semiconductor chip.

The conductive member may further include an electrode lead connected to another electrode of the semiconductor chip.

The conductive member may include a conductive wire connecting the semiconductor chip and the electrode layer.

In addition, a heat sink may be further coupled to the lower portion of the substrate.

In addition, the heat sink may be coupled to the substrate through a bolt.

In addition, an upper electrode layer may be further formed on an upper portion of the heat sink to be coupled to the lower portion of the substrate through soldering.

In addition, a lower electrode layer is further formed on the lower portion of the substrate, and may be coupled to the upper portion of the heat sink through solder.

In addition, the bottom surface of the substrate may be formed with a plurality of heat radiation fins engraved into the interior of the substrate.

In addition, the method of manufacturing a semiconductor device according to the present invention comprises the steps of: providing a substrate member having a substrate member formed of aluminum or an aluminum alloy; Forming an insulating layer by anodizing an upper surface of the substrate member; An electrode layer forming step of forming an electrode layer on the insulating layer by using at least one method selected from a spray method, a paste method, an ink printing method, an electrolytic plating and an electroless plating; And a semiconductor chip forming step of forming a semiconductor chip on the electrode layer. A conductive member forming step of connecting the electrode of the semiconductor chip and the electrode layer through a conductive member may be included.

Here, the electrode layer forming step may be formed of at least one or a combination of the electrode layer selected from copper, silver, nickel, gold, tin, aluminum, palladium.

After the electrode layer forming step, a heat sink coupling step of forming a heat sink under the substrate member may be further performed.

In addition, the heat sink coupling step may be to combine the heat sink with the substrate member through a bolt.

In addition, the heat sink coupling step may be to combine the substrate member and the heat sink through a solder.

In addition, the providing of the substrate member may include providing the substrate member to have at least one heat dissipation fin formed by being engraved below.

The semiconductor device according to the present invention is a semiconductor formed on an upper portion of a substrate by forming a substrate member for forming a substrate from aluminum or an aluminum alloy, anodizing the substrate member to form an insulating layer thereon, and forming an electrode layer formed thereon. The heat of the chip can be easily dissipated through the heat sink.

1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
3 is a cross-sectional view of a semiconductor device according to still another embodiment of the present invention.
4 is a cross-sectional view of a semiconductor device according to still another embodiment of the present invention.
5 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
6A to 6H are diagrams for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

Hereinafter, a configuration of a semiconductor device according to an embodiment of the present invention will be described.

1 is a cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device 100 according to an embodiment of the present invention may include a substrate 110, a heat sink 120, a coupling member 130, a first conductive member 140, a semiconductor chip 150, The second conductive member 160 is included.

The substrate 110 includes a substrate member 111, an insulating layer 112 formed on the substrate member 111, an electrode layer 113 formed on the insulating layer 112, and edges of the electrode layer 113. It includes a solder resist 114 surrounding the.

The substrate member 111 is formed in a plate shape formed in one direction. In addition, the substrate member 111 is formed of a metal and has excellent thermal conductivity. The substrate member 111 may be made of aluminum or an aluminum alloy, and the heat transfer coefficient of the aluminum or aluminum alloy may be about 130 to 250 [W / mK], indicating that the thermal conductivity of the substrate 111 is high. Therefore, the substrate member 111 can easily dissipate heat to the outside of the semiconductor chip 150 mounted thereon.

The insulating layer 112 is formed on the substrate member 111. The insulating layer 121 is formed over the entire upper surface of the substrate member 111. The insulating layer 112 may be formed by anodizing an upper surface of the substrate member 111. That is, the insulating layer 112 may be formed by anodizing the substrate member 111. In this case, when the substrate member 111 is made of aluminum or an aluminum alloy, the insulating layer 112 may be formed of aluminum oxide (Al 2 O 3 ). In addition, the insulating layer 112 may be formed by spraying a ceramic of aluminum oxide (Al 2 O 3 ) or yttrium oxide (Y 2 O 3 ) on the substrate member 111 by a plasma arc spray method. In addition, the insulating layer 112 may be formed by mixing the anodizing and spraying methods, and performing anodizing on the upper surface of the substrate 110, and then spraying on the upper portion of the insulating layer 112.

The electrode layer 113 is formed on the insulating layer 112. The electrode layer 113 is formed on top of the insulating layer 112 by using at least one or a combination of plasma arc spraying, cold spraying, paste, ink printing, electrolytic plating and electroless plating. Is formed. At this time, the method using the ink printing method first prepares a metal component such as silver or copper of a fine size (approximately nano size), and mixes it with a dispersant or the like to provide a constant metal ink. In addition, the electrode layer 113 may be formed by spraying the metal ink on the insulating layer 112 and applying a predetermined heat for a predetermined time. The electrode layer 113 may include at least one selected from copper (Cu), silver (Ag), nickel (Ni), gold (Au), tin (Sn), aluminum (Al), and palladium (Pd). It is formed using.

The solder resist 114 is formed on the substrate member 111. The solder resist 114 is formed to surround the edge of the electrode layer 113. The solder resist 114 insulates the edge of the electrode layer 113 so as not to be exposed to the outside. The solder resist 114 allows the solder 151 for coupling the semiconductor chip 150 only to the exposed upper portion of the electrode layer 113.

The heat sink 120 is formed under the substrate 110. The heat sink 120 is physically attached to the substrate 110 to radiate heat of the semiconductor chip 150 transferred to the substrate 110 to the bottom. The heat dissipation plate 120 includes a plurality of heat dissipation fins 121 at a lower portion thereof. Therefore, the heat sink 120 may increase the contact area with the air, thereby more easily dissipating heat.

The coupling member 130 couples the substrate 110 and the heat sink 120. The coupling member 130 is provided in the form of a bolt penetrating from an upper surface of the substrate 110 and extending to the heat sink 120. The coupling member 130 is coupled to a plurality of regions of the substrate 110 so that the substrate 110 is fixed at the heat sink 120.

The first conductive member 140 is formed on the electrode layer 113 of the substrate 110. The first conductive member 140 is provided in the form of an electrode terminal, and one end is coupled through the electrode layer 113 and the solder 141. The first conductive member 140 is electrically connected to one of the electrodes of the semiconductor chip 150 and the electrode layer 113. In addition, the other end of the first conductive member 140 is connected to an external circuit to form an electrical path between the semiconductor chip 150 and the external circuit. In addition, the first conductive member 140 forms a movement path of heat generated in the semiconductor chip 150. The first conductive member 140 emits heat of the semiconductor chip 150 through the electrode layer 113, the insulating layer 112, the substrate member 111, and the heat sink 120.

The semiconductor chip 150 is formed on the electrode layer 113. The semiconductor chip 150 is formed to have the plurality of electrodes. The semiconductor chip 150 may be formed of a small signal semiconductor device such as a general FET or a BJT, or may be composed of a power semiconductor device such as a diode, a JFET, or an IGBT. In particular, in the case of a power semiconductor device, the heat generation amount of the semiconductor chip 150 increases, and in this case, a substantial portion of the heat of the semiconductor chip 150 passes through the first conductive member 140 through the heat sink 120. You can exit.

The second conductive member 160 connects one of the electrodes of the semiconductor chip 150 with an external circuit. The second conductive member 160 may be provided in the form of a lead. In addition, the second conductive member 160 may be connected to the electrode of the semiconductor chip 150 through the solder 161.

As described above, in the semiconductor device 100 according to the exemplary embodiment of the present invention, the substrate member 111 forming the substrate 110 may be formed of aluminum or an aluminum alloy, and the substrate member 111 may be anodized on the top. By forming the insulating layer 112 and the electrode layer 113 formed thereon, the heat of the semiconductor chip 150 formed on the substrate 110 can be easily radiated through the heat sink 120. .

Hereinafter, a configuration of a semiconductor device according to another embodiment of the present invention will be described.

2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. Parts having the same configuration and operation as those of the foregoing embodiment are denoted by the same reference numerals, and will be described below with emphasis on differences.

2, a semiconductor device 200 according to another embodiment of the present invention may include a substrate 210, a heat sink 220, a coupling member 230, a first conductive member 140, a semiconductor chip 150, The second conductive member 160 is included.

The substrate 210 includes a substrate member 111, an insulating layer 112, an electrode layer 113, a solder resist 114, and a lower electrode layer 215.

The lower electrode layer 215 is formed on the bottom surface of the substrate member 111. The lower electrode layer 215 may be formed of at least one selected from nickel (Ni) and tin (Sn). The lower electrode layer 215 may be plated on the bottom surface of the substrate member 111. The lower electrode layer 215 is formed between the substrate member 111 and the coupling member 230 to serve as an intermediate layer to facilitate the coupling between the lower electrode layer 215. In addition, the lower electrode layer 215 has a good thermal conductivity, so that the heat of the semiconductor chip 150 transferred to the substrate member 111 can be easily transferred to the heat sink 120.

The heat dissipation plate 220 includes a plurality of heat dissipation fins 121 formed at the bottom and an upper electrode layer 222 formed at the top.

The upper electrode layer 222 may be formed using at least one selected from nickel or tin in the same manner as the lower electrode layer 215 of the substrate 210. The upper electrode layer 222 is preferably formed of the same material as the lower electrode layer 215. The upper electrode layer 222 is formed between the coupling member 230 and the heat dissipation plate 220 to facilitate the coupling between the upper electrode layer 222 and the heat of the semiconductor chip 150 to the heat dissipation plate 220. Be sure to

The coupling member 230 is formed between the substrate 210 and the heat sink 220. The coupling member 230 is formed of a solder material. Since the coupling member 230 is coupled to the lower electrode layer 215 of the substrate 210 and the upper electrode layer 222 of the heat sink 220, the coupling member 230 may be stably coupled. Therefore, since the coupling member 230 is tightly coupled to the substrate 210 and the heat sink 220, the coupling member 230 may easily transfer heat of the semiconductor chip 150.

Hereinafter, a configuration of a semiconductor device according to still another embodiment of the present invention will be described.

3 is a cross-sectional view of a semiconductor device according to still another embodiment of the present invention.

Referring to FIG. 3, a semiconductor device 300 according to another embodiment of the present invention may include a substrate 310, a heat sink 120, a coupling member 130, a semiconductor chip 150, and a second conductive member 360. It includes. In the semiconductor device 300 according to another exemplary embodiment of the present invention, the first conductive member does not necessarily have to be provided. However, the first conductive member is not described separately, but may be provided in some cases.

The substrate 310 includes a substrate member 111, an insulating layer 112, an electrode layer 313, and a solder resist 314.

The electrode layer 313 is formed on the insulating layer 112. In this case, unlike the previous embodiments, the electrode layer 313 is not formed as a single structure on the upper portion of the insulating layer 112, but is provided in plural to form a pattern. The pattern of the electrode layer 313 may be formed through a mask when the electrode layer 313 is formed. The electrode layer 313 may be electrically connected to the semiconductor chip 150 by the second conductive member 360.

The solder resist 314 is formed surrounding the edge of the electrode layer 313. The solder resist 314 is the same as in the previous embodiment except for providing a pattern corresponding to the pattern of the electrode layer 313.

The second conductive member 360 electrically connects the electrode of the semiconductor chip 150 and the electrode layer 313. The second conductive member 360 is formed of a conductive wire. The second conductive member 360 is generally composed of gold, silver or aluminum. However, the second conductive member 360 may be formed of the same material as the electrode layer 313 to increase the bonding force with the electrode layer 313.

Hereinafter, a configuration of a semiconductor device according to still another embodiment of the present invention will be described.

4 is a cross-sectional view of a semiconductor device according to still another embodiment of the present invention.

Referring to FIG. 4, a semiconductor device 400 according to another embodiment of the present invention includes a substrate 410, a first conductive member 140, a semiconductor chip 150, and a second conductive member 160. .

The substrate 410 includes a substrate member 411, an insulating layer 112, an electrode layer 113, and a solder resist 114.

The substrate member 411 is made of aluminum or an aluminum alloy. The substrate member 411 is formed with a plurality of heat radiation fins 411a formed by being engraved on a lower surface thereof. That is, even if a separate heat sink is not provided, the contact area with air may be increased through the heat radiation fins 411a of the substrate member 411 to easily dissipate heat of the semiconductor chip 150.

In addition, the insulating layer 112 may be formed on the upper or entire outer circumference of the substrate member 411. Therefore, since the semiconductor chip 150 is formed on the substrate member 411 and the insulating layer 112, the overall heat dissipation structure can be simplified. Therefore, heat dissipation characteristics of the semiconductor chip 150 may be improved.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described.

5 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. 6A to 6H are diagrams for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 5, a method of manufacturing a semiconductor device 100 according to an embodiment of the present invention may include a substrate member providing step S1, an insulating layer forming step S2, an electrode layer forming step S3, and a solder resist applying step. S4, a heat sink coupling step S5, a first conductive member forming step S6, a semiconductor chip forming step S7, and a second conductive member forming step S8. Hereinafter, each step of FIG. 5 will be described with reference to FIGS. 6A to 6H.

5 and 6A, the step S1 of providing a substrate member includes a substrate member 111 made of metal. The substrate member 111 is provided in the shape of a flat plate. The substrate member 111 may be made of aluminum or an aluminum alloy having good thermal conductivity.

5 and 6B, the insulating layer forming step S2 is a step of forming the insulating layer 112 on the upper surface of the substrate member 111. The insulating layer 112 may be performed by anodizing the substrate member 111. Therefore, when the substrate member 111 is made of aluminum or an aluminum alloy, the insulating layer 112 may be formed of aluminum oxide (Al 2 O 3 ). In addition, the insulating layer 112 may be formed by spraying a ceramic of aluminum oxide (Al 2 O 3 ) or yttrium oxide (Y 2 O 3 ) on the substrate member 111 by a plasma arc spray method. In addition, the insulating layer 112 may be formed by combining the anodizing and ceramic thermal spraying through a plasma arc scrap method.

5 and 6C, the electrode layer forming step S3 is a step of forming the electrode layer 113 on the insulating layer 112. The electrode layer 113 may include at least one selected from copper (Cu), silver (Ag), nickel (Ni), gold (Au), tin (Sn), aluminum (Al), and palladium (Pd). It can be formed using.

The electrode layer 113 may be formed on the insulating layer 112 by using a plasma arc spray method or a cold spray method. That is, the metal material forming the electrode layer 113 may be sprayed on the insulating layer 112 in a powder or melt state. When the metal particles in powder form are sprayed through the spray method, the metal particles collide with the surface of the insulating layer 112. In addition, a part of the surface of the insulating layer 112 is destroyed by the physical impact, and at the same time mixed with the metal powder. In addition, the metal powder instantly bonds between metal particles, thereby increasing adhesion between the insulating layer 112 and the electrode layer 113. As a result, the electrode layer 113 is easily formed on the insulating layer 112. Can be formed.

In addition, although not separately shown, the anodized layer may be physically protected from the metal powder, and may be easily combined with the metal powder through surface roughness. In addition, in the same principle, the anodizing forming the insulating layer 112 is sealed to prevent fine pores on the surface, and a hydroxide layer is formed on the upper portion thereof, and then applied to the anodizing in the spray process. Loss of thermal and physical impact can also be minimized.

The electrode layer 113 may be formed through a paste method. In this case, the electrode layer 113 may be formed on the insulating layer 112 by mixing a bonding material having high adhesion with the insulating layer 112 to a paste forming the electrode layer 113.

The electrode layer 113 may be formed by ink printing. In this case, in the ink printing method, a metal component such as silver or copper having a fine size (approximately nano size) is prepared first, and then mixed with a dispersant or the like and provided as a constant metal ink. In addition, the electrode layer 113 may be formed by spraying the metal ink on the insulating layer 112 and applying a predetermined heat for a predetermined time.

In addition, the electrode layer 113 may be formed through an electroless plating method. In addition, after the electrode layer 113 is formed through the spray method, the paste method, or the ink printing method, an electrolytic plating or an electroless plating of nickel (Ni) or tin (Sn) material having good bonding strength with the solder is additionally formed thereon. It is also possible to form more. That is, the electrode layer 113 may be formed through at least one selected from the spray method, the paste method, the ink printing method, the electrolytic plating and the electroless plating, or a combination thereof.

5 and 6D, the solder resist coating step S4 is a step of applying the solder resist 114 on the substrate member 111. The solder resist is formed to surround the edge of the electrode layer 113, so as to expose only the region where the solder is formed later in the electrode layer 113.

5 and 6E, the first conductive member forming step (S5) is a step of forming the first conductive member 140 by applying the solder 141 on the electrode layer 113. In this case, the solder 141 may be formed only on the upper portion of the electrode layer 113 exposed by the solder resist 114. In addition, the first conductive member 140 may be formed as an electrode terminal to be connected to an external circuit.

5 and 6F, the semiconductor chip forming step S6 is a step of forming the semiconductor chip 150 on the first conductive member forming step S6. In this case, the semiconductor chip 150 is physically and electrically connected to the first conductive member 140 by using a solder 151 thereunder.

5 and 6G, the second conductive member forming step (S7) is a step of connecting the electrode of the semiconductor chip 150 through the second conductive member 160. The second conductive member 160 may be connected to an electrode of the semiconductor chip 150 through a solder 161, and an extended end thereof may be connected to an external circuit.

In addition, the solders 141, 151, and 161 used in the first conductive member forming step S5 to the second conductive member forming step S7 may be reflowed in each step, and the first conductive member ( 150, the semiconductor chip 150, and the second conductive member 160 may be all reflowed at once.

Referring to FIGS. 5 and 6H, the heat sink coupling step S8 may include a substrate 110 including the substrate member 111, the insulating layer 112, the electrode layer 113, and the solder resist 114. Through the 130 is a step of coupling the heat sink 120. The heat dissipation plate 120 includes a plurality of heat dissipation fins 121 at the bottom thereof to increase the heat dissipation area. In addition, the coupling member 130 may be formed of a bolt to physically couple the substrate 110 to the heat sink 120. In this case, it is preferable that the heat sink 120 is tightly coupled so as not to form a gap between the lower portion of the substrate 110. This is because the air layer is reduced as the substrate 110 is in close contact with the substrate 110, thereby facilitating heat transfer of the substrate 110 to the heat sink 120.

What has been described above is only an embodiment for carrying out the semiconductor device and the method of manufacturing the same according to the present invention, and the present invention is not limited to the above embodiment, and as claimed in the following claims, the gist of the present invention Without departing from the scope of the present invention, any person having ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

100, 200, 300, 400; Semiconductor device
110, 310, 410; Substrates 111 and 411; Board member
112; Insulating layers 113, 313; Electrode layer
114, 314; Solder resist 120; Heat sink
130, 230; Coupling member 140; First conductive member
150; Semiconductor chips 160 and 360; Second conductive member

Claims (18)

delete delete delete delete delete delete delete delete delete delete delete Providing a substrate member comprising a substrate member formed of aluminum or an aluminum alloy;
An insulating layer forming step of anodizing an upper surface of the substrate member to form an anodizing insulating layer;
Forming an electrode layer on the anodizing insulating layer by using at least one method selected from among a spray method, a paste method, an ink printing method, an electrolytic plating and an electroless plating;
Applying a solder resist surrounding the edge of the electrode layer;
A semiconductor chip forming step of forming a semiconductor chip on the electrode layer;
And a conductive member forming step of connecting the electrode of the semiconductor chip and the electrode layer through a conductive member. delete delete delete 13. The method of claim 12,
Preparing a heat sink having an upper electrode layer formed of at least one of nickel and tin on an upper surface thereof;
Forming a lower electrode layer formed of at least one of nickel and tin on a lower surface of the substrate member; and
And soldering and bonding the heat sink and the substrate member. 13. The method of claim 12,
The method of manufacturing a semiconductor device comprising the step of providing the substrate member to have at least one heat radiation fin formed by engraving the substrate member below. The semiconductor device manufactured by the manufacturing method of any one of Claims 12, 16, and 17.
KR20100132704A 2010-12-22 2010-12-22 Semiconductor Device and Fabricating Method thereof KR101198848B1 (en)

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KR20100132704A KR101198848B1 (en) 2010-12-22 2010-12-22 Semiconductor Device and Fabricating Method thereof

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