KR101198848B1 - Semiconductor Device and Fabricating Method thereof - Google Patents
Semiconductor Device and Fabricating Method thereof Download PDFInfo
- Publication number
- KR101198848B1 KR101198848B1 KR20100132704A KR20100132704A KR101198848B1 KR 101198848 B1 KR101198848 B1 KR 101198848B1 KR 20100132704 A KR20100132704 A KR 20100132704A KR 20100132704 A KR20100132704 A KR 20100132704A KR 101198848 B1 KR101198848 B1 KR 101198848B1
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- KR
- South Korea
- Prior art keywords
- electrode layer
- substrate
- semiconductor device
- insulating layer
- semiconductor chip
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13062—Junction field-effect transistor [JFET]
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Disclosed is a semiconductor device and a method of manufacturing the same, which can improve heat dissipation efficiency.
For example, a semiconductor device according to the present invention may include a substrate including a substrate member formed of aluminum or an aluminum alloy, an insulating layer formed by being anodized on an upper surface of the substrate member, and an electrode layer formed on the insulating layer; A semiconductor chip formed on the substrate; Disclosed is a semiconductor device including a conductive member connecting an electrode of the semiconductor chip with the electrode terminal.
Description
The present invention relates to a semiconductor device and a method of manufacturing the same.
Modern electronic products are required to be small in size but high in performance. As a result, semiconductor devices, which are essential components for electronic products, also require miniaturization and high performance.
By the way, the semiconductor device has been miniaturized as the semiconductor integrated technology is improved, but in order to increase the performance, the heat dissipation function is required to be improved. This is because if the heat generated from the chip of the semiconductor device cannot be easily radiated, the performance of the semiconductor device may be degraded or the semiconductor chip may be damaged. In particular, in the case of power semiconductor devices, heat radiation is more important because a large amount of current flows.
The present invention provides a semiconductor device and a method of manufacturing the same that can improve heat dissipation efficiency.
A semiconductor device according to the present invention includes a substrate comprising a substrate member formed of aluminum or an aluminum alloy, an insulating layer formed by anodizing on an upper surface of the substrate member, and an electrode layer formed on the insulating layer; A semiconductor chip formed on the substrate; It may include a conductive member for connecting the electrode of the semiconductor chip with the electrode terminal.
Here, the substrate may further include a solder resist surrounding the edge of the electrode layer.
The conductive member may be formed between the electrode layer and the semiconductor chip to include an electrode terminal electrically connected to one of the electrodes of the semiconductor chip.
The conductive member may further include an electrode lead connected to another electrode of the semiconductor chip.
The conductive member may include a conductive wire connecting the semiconductor chip and the electrode layer.
In addition, a heat sink may be further coupled to the lower portion of the substrate.
In addition, the heat sink may be coupled to the substrate through a bolt.
In addition, an upper electrode layer may be further formed on an upper portion of the heat sink to be coupled to the lower portion of the substrate through soldering.
In addition, a lower electrode layer is further formed on the lower portion of the substrate, and may be coupled to the upper portion of the heat sink through solder.
In addition, the bottom surface of the substrate may be formed with a plurality of heat radiation fins engraved into the interior of the substrate.
In addition, the method of manufacturing a semiconductor device according to the present invention comprises the steps of: providing a substrate member having a substrate member formed of aluminum or an aluminum alloy; Forming an insulating layer by anodizing an upper surface of the substrate member; An electrode layer forming step of forming an electrode layer on the insulating layer by using at least one method selected from a spray method, a paste method, an ink printing method, an electrolytic plating and an electroless plating; And a semiconductor chip forming step of forming a semiconductor chip on the electrode layer. A conductive member forming step of connecting the electrode of the semiconductor chip and the electrode layer through a conductive member may be included.
Here, the electrode layer forming step may be formed of at least one or a combination of the electrode layer selected from copper, silver, nickel, gold, tin, aluminum, palladium.
After the electrode layer forming step, a heat sink coupling step of forming a heat sink under the substrate member may be further performed.
In addition, the heat sink coupling step may be to combine the heat sink with the substrate member through a bolt.
In addition, the heat sink coupling step may be to combine the substrate member and the heat sink through a solder.
In addition, the providing of the substrate member may include providing the substrate member to have at least one heat dissipation fin formed by being engraved below.
The semiconductor device according to the present invention is a semiconductor formed on an upper portion of a substrate by forming a substrate member for forming a substrate from aluminum or an aluminum alloy, anodizing the substrate member to form an insulating layer thereon, and forming an electrode layer formed thereon. The heat of the chip can be easily dissipated through the heat sink.
1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
3 is a cross-sectional view of a semiconductor device according to still another embodiment of the present invention.
4 is a cross-sectional view of a semiconductor device according to still another embodiment of the present invention.
5 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
6A to 6H are diagrams for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.
Hereinafter, a configuration of a semiconductor device according to an embodiment of the present invention will be described.
1 is a cross-sectional view of a
Referring to FIG. 1, a
The
The
The
The
The
The
The
The first
The
The second
As described above, in the
Hereinafter, a configuration of a semiconductor device according to another embodiment of the present invention will be described.
2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. Parts having the same configuration and operation as those of the foregoing embodiment are denoted by the same reference numerals, and will be described below with emphasis on differences.
2, a
The
The
The
The
The
Hereinafter, a configuration of a semiconductor device according to still another embodiment of the present invention will be described.
3 is a cross-sectional view of a semiconductor device according to still another embodiment of the present invention.
Referring to FIG. 3, a
The
The
The solder resist 314 is formed surrounding the edge of the
The second
Hereinafter, a configuration of a semiconductor device according to still another embodiment of the present invention will be described.
4 is a cross-sectional view of a semiconductor device according to still another embodiment of the present invention.
Referring to FIG. 4, a
The
The
In addition, the insulating
Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described.
5 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. 6A to 6H are diagrams for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
Referring to FIG. 5, a method of manufacturing a
5 and 6A, the step S1 of providing a substrate member includes a
5 and 6B, the insulating layer forming step S2 is a step of forming the insulating
5 and 6C, the electrode layer forming step S3 is a step of forming the
The
In addition, although not separately shown, the anodized layer may be physically protected from the metal powder, and may be easily combined with the metal powder through surface roughness. In addition, in the same principle, the anodizing forming the insulating
The
The
In addition, the
5 and 6D, the solder resist coating step S4 is a step of applying the solder resist 114 on the
5 and 6E, the first conductive member forming step (S5) is a step of forming the first
5 and 6F, the semiconductor chip forming step S6 is a step of forming the
5 and 6G, the second conductive member forming step (S7) is a step of connecting the electrode of the
In addition, the
Referring to FIGS. 5 and 6H, the heat sink coupling step S8 may include a
What has been described above is only an embodiment for carrying out the semiconductor device and the method of manufacturing the same according to the present invention, and the present invention is not limited to the above embodiment, and as claimed in the following claims, the gist of the present invention Without departing from the scope of the present invention, any person having ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.
100, 200, 300, 400; Semiconductor device
110, 310, 410;
112; Insulating
114, 314; Solder resist 120; Heat sink
130, 230; Coupling
150;
Claims (18)
An insulating layer forming step of anodizing an upper surface of the substrate member to form an anodizing insulating layer;
Forming an electrode layer on the anodizing insulating layer by using at least one method selected from among a spray method, a paste method, an ink printing method, an electrolytic plating and an electroless plating;
Applying a solder resist surrounding the edge of the electrode layer;
A semiconductor chip forming step of forming a semiconductor chip on the electrode layer;
And a conductive member forming step of connecting the electrode of the semiconductor chip and the electrode layer through a conductive member.
Preparing a heat sink having an upper electrode layer formed of at least one of nickel and tin on an upper surface thereof;
Forming a lower electrode layer formed of at least one of nickel and tin on a lower surface of the substrate member; and
And soldering and bonding the heat sink and the substrate member.
The method of manufacturing a semiconductor device comprising the step of providing the substrate member to have at least one heat radiation fin formed by engraving the substrate member below.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20100132704A KR101198848B1 (en) | 2010-12-22 | 2010-12-22 | Semiconductor Device and Fabricating Method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20100132704A KR101198848B1 (en) | 2010-12-22 | 2010-12-22 | Semiconductor Device and Fabricating Method thereof |
Publications (2)
Publication Number | Publication Date |
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KR20120071102A KR20120071102A (en) | 2012-07-02 |
KR101198848B1 true KR101198848B1 (en) | 2012-11-07 |
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KR20100132704A KR101198848B1 (en) | 2010-12-22 | 2010-12-22 | Semiconductor Device and Fabricating Method thereof |
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JP6711098B2 (en) * | 2016-04-15 | 2020-06-17 | オムロン株式会社 | Heat dissipation structure of semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002203942A (en) * | 2000-12-28 | 2002-07-19 | Fuji Electric Co Ltd | Power semiconductor module |
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Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002203942A (en) * | 2000-12-28 | 2002-07-19 | Fuji Electric Co Ltd | Power semiconductor module |
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KR20120071102A (en) | 2012-07-02 |
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