JPH05304072A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH05304072A
JPH05304072A JP4086763A JP8676392A JPH05304072A JP H05304072 A JPH05304072 A JP H05304072A JP 4086763 A JP4086763 A JP 4086763A JP 8676392 A JP8676392 A JP 8676392A JP H05304072 A JPH05304072 A JP H05304072A
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JP
Japan
Prior art keywords
pattern
region
pellet
semiconductor wafer
dummy pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4086763A
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Japanese (ja)
Inventor
Masayuki Yanagisawa
正之 柳澤
Original Assignee
Nec Corp
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Nec Corp, 日本電気株式会社 filed Critical Nec Corp
Priority to JP4086763A priority Critical patent/JPH05304072A/en
Publication of JPH05304072A publication Critical patent/JPH05304072A/en
Application status is Withdrawn legal-status Critical

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Abstract

PURPOSE: To enable a semiconductor device to be lessened in dispersion caused by a loading effect and a dummy pattern to be less separated from a semiconductor wafer by a method wherein the minimal dimension of a dummy pattern is set larger than that of a pellet region, and the pattern coverage of the dummy pattern is set nearly equal to that of a pellet region.
CONSTITUTION: An aluminum film is deposited on all the surface of a semiconductor wafer 101, a positive photoresist film is applied thereon, an inner region is divided into pellet regions 102, and a prescribed pattern is projected onto the pellet region 102. A dummy pattern on a reticule is shrunk and projected onto a peripheral region to form a dummy pattern of stripes 103B. The minimum line width of the dummy pattern is set larger that of the pellet region 102, and it is preferable that the minimum line width of the dummy pattern is set two or three times as large as that of the pellet region 102. By this setup, a pattern coverage is nearly uniform throughout the surface of the semiconductor wafer, so that a semiconductor device can be lessened in dispersion caused by a loading effect.
COPYRIGHT: (C)1993,JPO&Japio

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は半導体装置の製造方法に関し、特に半導体ウェーハのパターン転写工程に関する。 BACKGROUND OF THE INVENTION This invention relates to a method of manufacturing a semiconductor device, more particularly to a semiconductor wafer pattern transfer process.

【0002】 [0002]

【従来の技術】従来の半導体装置の製造方法では、パターンの転写・形成を通常縮小投影型露光装置を用いて行うので、例えば図3に示すように半導体ウェーハ201 In the method of manufacturing a conventional semiconductor device, it is performed using conventional reduction projection exposure apparatus transcription and formation of the pattern, a semiconductor wafer as shown in FIG. 3, for example 201
の内部領域をマトリクス状にペレット領域202に区画し周辺領域203には露光を施さないのが一般的であった。 The interior region not subjected to exposure in the peripheral region 203 is partitioned into pellets region 202 in a matrix were common for. すなわち、通常のポジ型フォトレジスト膜を用いれば周辺領域にはフォトレジスト膜が広範囲にわたって残っているという状態になる。 That is, a state that there remains widespread photoresist film in the peripheral region by using the conventional positive photoresist film. この場合、ペレット領域2 In this case, the pellet region 2
02内と周辺領域との間でパターン被覆率(パターンの占有面積の当該領域の面積に対する比率)に格差が生じている。 Pattern coverage between 02 in the peripheral region disparity (the ratio of the area of ​​the region of the area occupied by the pattern) is generated. すなわち、ペレット領域では100%未満であるが、周辺領域では100%になる。 That is, although the pellet region is less than 100% to 100% in the peripheral region. このことが半導体装置の製造に支障をきたすことがある。 This is sometimes hindered in the fabrication of semiconductor devices.

【0003】例えば、ドライエッチングの工程においては、パターン被覆率に応じてエッチング速度、エッチング形状が変化する現象があり、また、プラズマ励起型の化学的気相成長の工程においても炉内で半導体ウェーハが対向するように配置した場合などに対面した半導体ウェーハのパターン被覆率の影響を受けて成膜速度が変化する現象があることが知られている。 For example, in the step of dry etching, there is a phenomenon that the etching rate, the etching shape varies depending on the pattern density, also, the semiconductor wafers in a furnace even in the step of chemical vapor deposition of plasma enhanced there has been known that the deposition rate under the influence of pattern coverage of the semiconductor wafer faces in a case of arranging so as to face there is a phenomenon that changes. これらの現象はローディング効果と総称され、パターン形成の均一性を妨げる要因となっている。 These phenomena are referred to collectively as loading effect, which is a factor that hinders the uniformity of the pattern formation.

【0004】この対策として最も簡便で一般的なものは図4(a)に示すように半導体ウェーハ301の内部領域をペレット領域302でマトリクス状に占有し、周辺領域はダミーペレット領域303Aで占有させるというものである。 [0004] occupies the interior region of the semiconductor wafer 301 as shown in FIG. 4 is the most convenient and common ones as a countermeasure (a) in a matrix pellet region 302, the peripheral region is occupied by the dummy pellet region 303A is that. ダミーペレット領域303Aには、ペレット領域に転写されるパターンの一部が転写される。 The dummy pellet region 303A, a part of the pattern to be transferred to the pellet region is transferred. したがって半導体ウェーハの全面にわたってパターン被覆率がほぼ均一になり、前述したローディング効果によるばらつきを抑制することができる。 Therefore becomes substantially uniform pattern density over the entire surface of the semiconductor wafer, it is possible to suppress the variation due to the loading effect described above.

【0005】 [0005]

【発明が解決しようとする課題】しかしながら、図4 THE INVENTION Problems to be Solved] However, as shown in FIG. 4
(b)に示すように、半導体ウェーハの端部301Aにおいては、独立したダミー配線304aが形成されてしまうことにもなり、その独立したダミー配線は下地との接着強度が不十分になりやすいため容易に剥がれて他の部分に再付着してしまう。 (B), the at the end 301A of the semiconductor wafer, also will be independent dummy wiring 304a will be formed, the separate because the dummy wiring tends to become insufficient adhesion strength between the base resulting in reattached to other parts easily peeled off. また、運搬用キャリアの縁などで擦れると半導体ウェーハ端部の微細配線(ダミー配線304)は必ずしも独立していないものでも剥がれてしまうことが多い。 Also, edges etc. in rubbing the fine wiring of a semiconductor wafer end portion of the transport carrier (dummy wiring 304) is often peeled off even one that is not necessarily independent.

【0006】こうして剥がれた微細配線が他の部分に再付着すると、絶縁不良をひき起こし、製品の歩留りを下げ、また信頼性を低下させてしまう。 [0006] Thus peeled when fine wiring is reattached to other parts, it sparked poor insulation, lower the yield of the product, also resulting in reduced reliability. さらに、微細配線のくずで製造装置が汚染されてしまうと、その製造装置を用いるすべての製品に影響が出るため重大である。 Further, when manufactured by debris fine wiring device is contaminated, is critical because the influence comes into all products using the manufacturing apparatus.

【0007】 [0007]

【課題を解決するための手段】本発明の半導体装置の製造方法は、半導体ウェーハの表面に所定の被膜を形成する工程と、ポジ型レジスト膜を形成する工程と、前記半導体ウェーハ表面の内部領域に少なくとも一つのペレット領域を定義して、前記ペレット領域上の前記ポジ型レジスト膜に所定のパターンを転写し、前記ペレット領域を除く周辺領域上の前記ポジ型レジスト膜に前記パターンの最小寸法を少なくとも上回る最小寸法を有しパターン被覆率が前記パターンと実質的に等しいダミーパターンを転写する工程とを有するというものである。 The method of manufacturing a semiconductor device of the present invention, in order to solve the problems] includes a step of forming a predetermined film on the surface of a semiconductor wafer, a step of forming a positive resist film, the interior region of the semiconductor wafer surface at least define a single pellet regions, and transferring a predetermined pattern on the positive resist film on the pellet region, the minimum dimension of the pattern on the positive resist film on the peripheral region excluding the pellet region it is that a step of minimum dimension has a pattern coverage at least over the transferring the pattern substantially equal dummy pattern.

【0008】 [0008]

【実施例】次に本発明について図面を参照して説明する。 EXAMPLES The present invention will be described below with reference to the drawings.

【0009】図1は本発明の第1の実施例を説明するための半導体ウェーハの平面模式図、図2(a)はレティクル上のダミーパターンを示す平面模式図、図2(b) [0009] Figure 1 is a first schematic plan view of a semiconductor wafer for explaining the embodiments of the present invention, FIGS. 2 (a) is a plan view schematically showing a dummy pattern on the reticle, and FIG. 2 (b)
はレティクル上のダミーパターンの半導体ウェーハに投影した状態を示す平面模式図である。 Is a schematic plan view showing a state projected onto a semiconductor wafer dummy pattern on the reticle.

【0010】本実施例はアルミニウム配線形成におけるリソグラフィー工程に本発明を適用したものである。 [0010] This embodiment is an application of the present invention to a lithography process in the aluminum wiring formation.

【0011】半導体ウェーハ101の全面に図示しないアルミニウム膜を被着し、図示しないポジ型フォトレジスト膜を塗布し、内部領域を複数のペレット領域102 [0011] The aluminum film (not shown) on the entire surface of the semiconductor wafer 101 is deposited, by applying a not-shown positive type photoresist film, the inner region plurality of pellets areas 102
に分割し、各ペレット領域に所定のパターンを投影する。 Divided into, for projecting a predetermined pattern on each pellet region. この投影露光工程において、周辺領域には、図2 In the projection exposure process, the peripheral region, FIG. 2
(a)に示すレティクル105を用いてレティクル上のダミーパターン105Aを投影する。 Projecting the dummy pattern 105A on the reticle using the reticle 105 shown in (a).

【0012】レティクル105には線幅25μm、間隔50μmの縞状のダミーパターン105Aが描かれている。 [0012] linewidth 25μm to reticle 105, the stripe-shaped dummy pattern 105A spacing 50μm are depicted. 縮小投影型露光装置を用いて5分の1に縮小して半導体ウェーハ101のポジ型フォトレジスト膜に投影し、線幅5μm間隔10μmの縞状サブダミーパターン103Cの潜像を得る。 By reducing with reduction projection exposure apparatus by a factor of 5 by projecting the positive photoresist film of the semiconductor wafer 101, to obtain a latent image of the striped sub dummy patterns 103C having a line width of 5μm spacing 10 [mu] m. 位置をずらして同様の操作を半導体ウェーハ101の周辺領域全域にわたって繰り返すことによって図1に示すように、縞状ダミーパターン1 As shown in FIG. 1 by repeating the position the same operation by shifting the over peripheral regions whole area of ​​the semiconductor wafer 101, stripe dummy patterns 1
03Bを形成することができる。 It is possible to form a 03B.

【0013】周辺領域におけるパターン被覆率は約33 [0013] pattern coverage in the peripheral region is about 33
%となる。 % It becomes. ペレット領域102には、より複雑な形状のパターンが転写されることになるが、その最小線幅は1 Pellet region 102 is so that the pattern of more complex shape is transferred, the minimum line width 1
μmでパターン被覆率も約33%であるとする。 Pattern coverage in μm is also assumed to be about 33%.

【0014】ダミーパターンの最小線幅は、ペレット領域102での最小線幅より大きく、好ましくは2〜3倍程度以上にしておく。 [0014] minimum line width of the dummy pattern is greater than the minimum line width in the pellet region 102, preferably it should be at least 2 to 3 times. 半導体ウェーハ101の周辺領域に形成されるダミー配線が剥れ難しくするためである。 Dummy wiring formed in the peripheral region of the semiconductor wafer 101 is to difficult peeling.

【0015】パターン被覆率がウェーハ全面でほぼ均一になるのでローディング効果によるばらつきを抑止できる。 The pattern coverage can suppress the variation due to the loading effect since substantially uniform the entire wafer surface. 本実施例ではダミー配線が直線状をしているが、曲線状例えば正弦曲線状にしてもよい。 In the present embodiment has dummy wiring has a linear shape, but may be curved for example sinusoidal.

【0016】図5(a)は本発明の第2の実施例を説明するための半導体ウェーハの平面模式図、図5(b)は第2の実施例によるダミー配線を示す斜視図である。 [0016] FIG. 5 (a) second embodiment schematic plan view of a semiconductor wafer for explaining the present invention, FIG. 5 (b) is a perspective view showing a dummy wiring according to the second embodiment.

【0017】半導体ウェーハ401上には、アルミニウム配線のリソグラフィー工程においてペレット領域40 [0017] On the semiconductor wafer 401, the pellet area in the lithography process of the aluminum wiring 40
2がマトリクス状に配置され周辺領域にはダミーパターン403Bが形成されている。 2 is a dummy pattern 403B is formed in the peripheral region are arranged in a matrix.

【0018】このダミーパターンは線幅5μm、間隔2 [0018] The dummy pattern line width of 5μm, interval 2
0μmの縦縞と、線幅5μm、間隔25μmの横縞とが交差している格子縞状パターンであり、隣接する露光ショット間でパターンが接続するように形成している。 And vertical stripes of 0 .mu.m, a checkerboard-like pattern line width 5 [mu] m, and a lateral stripe spacing 25μm intersect is formed so as to pattern between adjacent exposure shots are connected. パターン被覆率は33%でありペレット領域内のアルミニウム配線のパターン被覆率と概略等しい値である。 Pattern coverage is pattern coverage and approximately equal values ​​of aluminum wiring in and pellet area 33%. こうして形成される格子縞状ダミー配線404は、半導体ウェーハの任意の端部401Aにおいても独立することがないので下地との接着性が強く、第1の実施例より一層剥がれにくい。 Checkerboard-like dummy wire 404 thus formed, there is no possible independent even in an arbitrary end 401A of the semiconductor wafer strong adhesion to the underlying, more difficult to peel off from the first embodiment.

【0019】本実施例では、直線状の縦縞と横縞が直交しているが、斜交していてもよい。 [0019] In this embodiment, the linear vertical stripes and horizontal stripes are orthogonal, may be obliquely intersect. あるいは互いに斜交する3本の縞を設けてもよい。 Or oblique three stripes may also be provided together. 更に、直線状に限らず、 In addition, not only in a straight line,
互いに交わる曲線状(例えば正弦曲線のような周期生の曲線状)の縞を用いてもよい。 May be used stripes curved (e.g. periodic generation of curved such as a sine curve) intersecting each other.

【0020】 [0020]

【発明の効果】以上説明したように本発明は半導体ウェーハにパターンを転写形成するリソグラフィー工程において、半導体ウェーハの周辺領域に、内部領域に存在するパターン最小寸法を少くとも上回る最小寸法を有し、 The present invention described above, according to the present invention in lithography process for transferring a pattern on a semiconductor wafer, a peripheral region of the semiconductor wafer, having a minimum dimension greater than the at least a pattern minimum dimension existing in the interior region,
かつ内部領域におけるパターン被覆率と概略等しいパターン被覆率を有するダミーパターンを形成するので、半導体装置の製造工程中でパターン被覆率に依存するローディング効果をよるばらつきを抑制するとともに、半導体ウェーハ端部からの微細パターンの剥がれを防止することができるという効果を有する。 And because it forms a dummy pattern having a pattern density and approximately equal pattern coverage inside region, it suppresses the variation due to the loading effect which depends on the pattern density in a manufacturing process of a semiconductor device, a semiconductor wafer edge It has the effect that it is possible to prevent peeling of a fine pattern.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の第1の実施例の説明に使用する半導体ウェーハの平面模式図である。 1 is a schematic plan view of a semiconductor wafer used in the description of the first embodiment of the present invention.

【図2】本発明の第1の実施例における露光工程の説明に使用するレティクルの平面模式図(図2(a))および半導体ウェーハの平面模式図(図2(b))である。 Schematic plan view of a reticle to be used to describe the exposure process in the first embodiment of the present invention; FIG (FIG. 2 (a)) and a schematic plan view of a semiconductor wafer is a (Figure 2 (b)).

【図3】従来の技術の説明に使用する半導体ウェーハの平面模式図である。 3 is a schematic plan view of a semiconductor wafer used in the description of the prior art.

【図4】従来の技術の説明に使用する半導体ウェーハの平面模式図(図4(a))、および斜視図(図4 [Figure 4] a schematic plan view of a semiconductor wafer used in the description of the prior art (FIG. 4 (a)), and a perspective view (FIG. 4
(b))である。 A (b)).

【図5】本発明の第2の実施例の説明に使用する半導体ウェーハの平面模式図(図5(a))、および斜視図(図5(b))である。 FIG. 5 is a plan schematic of a semiconductor wafer view for use in explanation of a second embodiment of the present invention (FIG. 5 (a)), and is a perspective view (Figure 5 (b)).

【符号の説明】 DESCRIPTION OF SYMBOLS

101,101,301,401 半導体ウェーハ 102,202,302,402 ペレット領域 103B ダミーパターン 103C サブダミーパターン 203 周辺領域 303A ダミーペレット領域 403B ダミーパターン 304,404 ダミー配線 101,101,301,401 semiconductor wafer 102, 202, 302, and 402 pellets region 103B dummy pattern 103C sub dummy pattern 203 peripheral region 303A dummy pellet region 403B dummy patterns 304, 404 dummy wiring

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 半導体ウェーハの表面に所定の被膜を形成する工程と、ポジ型レジスト膜を形成する工程と、前記半導体ウェーハ表面の内部領域に少なくとも一つのペレット領域を定義して、前記ペレット領域上の前記ポジ型レジスト膜に所定のパターンを転写し、前記ペレット領域を除く周辺領域上の前記ポジ型レジスト膜に前記パターンの最小寸法を少なくとも上回る最小寸法を有しパターン被覆率が前記パターンと実質的に等しいダミーパターンを転写する工程とを有することを特徴とする半導体装置の製造方法。 And 1. A process for forming a predetermined film on the surface of a semiconductor wafer, a step of forming a positive resist film, to define at least one pellet region within a region of the semiconductor wafer surface, the pellet region and transferring a predetermined pattern on the positive resist film above, pattern coverage has a minimum dimension of at least above the minimum dimension of the pattern on the positive resist film on the peripheral region excluding the pellet regions and said pattern the method of manufacturing a semiconductor device characterized by a step of transferring substantially equal dummy pattern.
  2. 【請求項2】 ダミーパターンが格子状である請求項1 2. A method according to claim 1 dummy pattern is grid-like
    記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according.
JP4086763A 1992-04-08 1992-04-08 Manufacture of semiconductor device Withdrawn JPH05304072A (en)

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Publications (1)

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