JPH05304072A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a semiconductor device to be lessened in dispersion caused by a loading effect and a dummy pattern to be less separated from a semiconductor wafer by a method wherein the minimal dimension of a dummy pattern is set larger than that of a pellet region, and the pattern coverage of the dummy pattern is set nearly equal to that of a pellet region. CONSTITUTION:An aluminum film is deposited on all the surface of a semiconductor wafer 101, a positive photoresist film is applied thereon, an inner region is divided into pellet regions 102, and a prescribed pattern is projected onto the pellet region 102. A dummy pattern on a reticule is shrunk and projected onto a peripheral region to form a dummy pattern of stripes 103B. The minimum line width of the dummy pattern is set larger that of the pellet region 102, and it is preferable that the minimum line width of the dummy pattern is set two or three times as large as that of the pellet region 102. By this setup, a pattern coverage is nearly uniform throughout the surface of the semiconductor wafer, so that a semiconductor device can be lessened in dispersion caused by a loading effect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a pattern transfer process for a semiconductor wafer.

[0002]

2. Description of the Related Art In a conventional method of manufacturing a semiconductor device, a pattern transfer / formation is usually performed by using a reduction projection type exposure apparatus, so that, for example, as shown in FIG.
It was general that the inner region of the above was partitioned into a matrix of pellet regions 202 and the peripheral region 203 was not exposed. That is, if a normal positive photoresist film is used, the photoresist film remains in a wide area in the peripheral region. In this case, the pellet area 2
There is a difference in the pattern coverage (ratio of the area occupied by the pattern to the area of the region) between 02 and the peripheral region. That is, it is less than 100% in the pellet region, but 100% in the peripheral region. This may hinder the manufacturing of semiconductor devices.

For example, in the process of dry etching, there is a phenomenon that the etching rate and etching shape change according to the pattern coverage, and also in the process of plasma-enhanced chemical vapor deposition, a semiconductor wafer is used in a furnace. It is known that there is a phenomenon in which the film formation rate is changed under the influence of the pattern coverage of the semiconductor wafer facing each other when they are arranged so as to face each other. These phenomena are collectively called the loading effect, and are a factor that hinders the uniformity of pattern formation.

The simplest and most common countermeasure is to occupy the internal region of the semiconductor wafer 301 with the pellet region 302 in a matrix and the peripheral region with the dummy pellet region 303A as shown in FIG. 4A. That is. A part of the pattern transferred to the pellet area is transferred to the dummy pellet area 303A. Therefore, the pattern coverage becomes substantially uniform over the entire surface of the semiconductor wafer, and the variation due to the loading effect described above can be suppressed.

[0005]

However, as shown in FIG.
As shown in (b), an independent dummy wiring 304a is also formed at the end portion 301A of the semiconductor wafer, and the independent dummy wiring tends to have insufficient adhesive strength with the base. It easily peels off and redeposits on other parts. In addition, when rubbing against the edge of the carrier for transportation, the fine wiring (dummy wiring 304) at the end of the semiconductor wafer is often peeled off even though it is not necessarily independent.

If the fine wiring thus peeled off is reattached to another portion, it causes insulation failure, lowers the product yield, and lowers the reliability. Further, if the manufacturing equipment is contaminated with the waste of fine wiring, it affects all the products using the manufacturing equipment, which is serious.

[0007]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a predetermined film on the surface of a semiconductor wafer, a step of forming a positive resist film, and an internal region of the surface of the semiconductor wafer. At least one pellet region is defined, a predetermined pattern is transferred to the positive resist film on the pellet region, and the minimum dimension of the pattern is set on the positive resist film on the peripheral region excluding the pellet region. Transferring a dummy pattern having a minimum dimension that is at least greater and having a pattern coverage substantially equal to the pattern.

[0008]

The present invention will be described below with reference to the drawings.

FIG. 1 is a schematic plan view of a semiconductor wafer for explaining a first embodiment of the present invention, FIG. 2A is a schematic plan view showing a dummy pattern on a reticle, and FIG.
FIG. 3 is a schematic plan view showing a state where a dummy pattern on a reticle is projected onto a semiconductor wafer.

In this embodiment, the present invention is applied to a lithography process for forming aluminum wiring.

An aluminum film (not shown) is deposited on the entire surface of the semiconductor wafer 101, a positive photoresist film (not shown) is applied, and an inner region is formed into a plurality of pellet regions 102.
Then, a predetermined pattern is projected on each pellet region. In this projection exposure process, the peripheral area is formed as shown in FIG.
The dummy pattern 105A on the reticle is projected using the reticle 105 shown in FIG.

A striped dummy pattern 105A having a line width of 25 μm and a space of 50 μm is drawn on the reticle 105. The image is reduced to 1/5 using a reduction projection type exposure apparatus and projected onto the positive photoresist film of the semiconductor wafer 101 to obtain a latent image of the striped sub-dummy pattern 103C having a line width of 5 μm and an interval of 10 μm. By shifting the position and repeating the same operation over the entire peripheral region of the semiconductor wafer 101, as shown in FIG.
03B can be formed.

The pattern coverage in the peripheral area is about 33.
%. A more complicated pattern is transferred to the pellet region 102, but the minimum line width is 1
The pattern coverage is about 33% in μm.

The minimum line width of the dummy pattern is larger than the minimum line width in the pellet region 102, preferably about 2 to 3 times or more. This is because it is difficult for the dummy wiring formed in the peripheral region of the semiconductor wafer 101 to peel off.

Since the pattern coverage is substantially uniform on the entire surface of the wafer, it is possible to suppress variations due to the loading effect. In the present embodiment, the dummy wiring has a linear shape, but it may have a curved shape, for example, a sinusoidal shape.

FIG. 5A is a schematic plan view of a semiconductor wafer for explaining a second embodiment of the present invention, and FIG. 5B is a perspective view showing a dummy wiring according to the second embodiment.

On the semiconductor wafer 401, the pellet region 40 is formed in the aluminum wiring lithography process.
2 are arranged in a matrix and a dummy pattern 403B is formed in the peripheral region.

This dummy pattern has a line width of 5 μm and an interval of 2
It is a lattice-striped pattern in which vertical stripes of 0 μm and horizontal stripes having a line width of 5 μm and an interval of 25 μm intersect each other, and the patterns are formed so as to connect between adjacent exposure shots. The pattern coverage is 33%, which is approximately the same as the pattern coverage of the aluminum wiring in the pellet region. The thus-formed lattice-striped dummy wiring 404 does not become independent even at any end portion 401A of the semiconductor wafer, and therefore has strong adhesiveness to the base and is more difficult to peel off than the first embodiment.

In the present embodiment, the straight vertical stripes and the horizontal stripes are orthogonal to each other, but they may be diagonally crossed. Alternatively, three stripes that are oblique to each other may be provided. Furthermore, not limited to a straight line,
It is also possible to use curvilinear (for example, a periodic curvilinear shape such as a sinusoidal) stripes that intersect with each other.

[0020]

As described above, according to the present invention, in the lithography process for transferring and forming a pattern on a semiconductor wafer, the peripheral region of the semiconductor wafer has a minimum dimension at least exceeding the minimum dimension of the pattern existing in the internal region,
Further, since the dummy pattern having the pattern coverage substantially equal to the pattern coverage in the internal region is formed, the variation due to the loading effect depending on the pattern coverage in the manufacturing process of the semiconductor device is suppressed, and the semiconductor wafer end portion It is possible to prevent the fine pattern from peeling off.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a semiconductor wafer used for explaining a first embodiment of the present invention.

2A and 2B are a schematic plan view of a reticle (FIG. 2A) and a schematic plan view of a semiconductor wafer (FIG. 2B) used for explaining an exposure step in the first embodiment of the present invention.

FIG. 3 is a schematic plan view of a semiconductor wafer used for explaining a conventional technique.

FIG. 4 is a schematic plan view (FIG. 4A) and a perspective view (FIG. 4) of a semiconductor wafer used for explaining a conventional technique.
(B)).

5A and 5B are a schematic plan view (FIG. 5A) and a perspective view (FIG. 5B) of a semiconductor wafer used for explaining a second embodiment of the present invention.

[Explanation of symbols]

 101, 101, 301, 401 Semiconductor wafer 102, 202, 302, 402 Pellet area 103B Dummy pattern 103C Sub dummy pattern 203 Peripheral area 303A Dummy pellet area 403B Dummy pattern 304, 404 Dummy wiring

Claims (2)

[Claims] 1. A step of forming a predetermined film on a surface of a semiconductor wafer, a step of forming a positive resist film, and defining at least one pellet area in an inner area of the surface of the semiconductor wafer, and the pellet area. A predetermined pattern is transferred to the positive resist film above, and the positive resist film on the peripheral region excluding the pellet region has a minimum dimension that exceeds at least the minimum dimension of the pattern, and the pattern coverage is the same as that of the pattern. And a step of transferring dummy patterns that are substantially equal to each other. 2. The dummy pattern has a grid pattern.
A method of manufacturing a semiconductor device according to claim 1.