JP2980061B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a plurality of photolithography steps.

[0002]

2. Description of the Related Art FIG. 3A is a general explanatory diagram of a repeat margin on a reticle, and FIG. 3B is a general explanatory diagram of an exposure region and a repeat margin on a wafer when step exposure is performed. FIG. 4 is a general plan view when a device pattern is exposed and transferred to a semiconductor wafer, and FIG.
FIG. 2B is a cross-sectional view of a main part of a semiconductor wafer in one step of an embodiment of a conventional method for manufacturing a semiconductor device, FIG. FIG. 6 is a cross-sectional view during one step after b), FIG. 6 is a plan view of a peripheral exposure reticle used in a conventional example, FIG. 7 is a plan view of a conventional reticle in which a device pattern region and a peripheral exposure region are mixed, FIG.
(A) is a sectional view of a main part of a semiconductor wafer during one step of the second embodiment of the conventional method of manufacturing a semiconductor device, (b)
Is a cross-sectional view during one step after (a), (c) is (b)
It is sectional drawing in one process after.

At present, an exposure method called step-and-repeat is used as the most common exposure method for photolithography. In this method, a pattern of one or more semiconductor chips formed on a reticle by one exposure is transferred onto a wafer. By repeating this operation step by step, a large number of semiconductor chips can be formed on one wafer. At the time of this step exposure, the reticle is placed on the reticle as shown in FIG.
An area called a repeat margin 8 having a width of several μm to several tens μm surrounded by a light shielding area 6 and a device area 9 as shown in FIG. The exposure area 10 is an area obtained by adding a repeat margin 8 to the device area 9.

FIG. 3B shows a first exposure area 101 and a second exposure area 10 ₁ on a wafer when stepwise exposure is performed twice in the horizontal direction using the reticle shown in FIG. it is a diagram showing a _second positional relationship. Figure 3 (b) is a state where there is no positional deviation, this time the first device region 9 ₁ and the second
Device region 9 ₂ is in a state of contact. Normally, when performing exposure transfer on a wafer, a 1/5 reduction exposure is performed, so that exposure is performed by overlapping with a neighboring device region by a width of 1/5 of a repeat margin on a reticle. Therefore, if the amount of displacement is within the width of the over-exposed region, there is no unexposed region between the first and second exposed regions.

When manufacturing a semiconductor device, the reticle used in each photolithography process has the same exposure area. Therefore, when the reticle is exposed by the step-and-repeat method, the reticle on the wafer shown in FIG. At the outermost peripheral edge 14 of the device pattern area 12, FIGS.
A problem as shown in FIG.

FIG. 5A shows that after an interlayer film 2 is grown on a semiconductor substrate 1, a photoresist 3 is applied by a spin coater, exposed using a reticle for a contact hole, and then developed. FIG. 6 is a cross-sectional view of a rearmost outer end 14 (see FIG. 4). Normally, the end portion of the exposure area of the reticle is a scribe line, and the contact hole pattern described here is set so as to open most of the scribe line. The reason why most of the scribe lines are opened is to establish electrical conduction with the semiconductor substrate. Therefore, the inside of the wafer is exposed at the boundary of the outermost peripheral edge 14 of the device pattern area, the wafer peripheral area 13 is not exposed, and the photoresist 3 remains as shown in FIG. Next, the interlayer film 2 is etched by anisotropic etching, the photoresist 3 is stripped, and a wiring material such as tungsten or aluminum is grown by a CVD method or a sputtering method to form a wiring layer 4.

Next, resist patterning is performed on the wiring layer 4 using a lithography technique. Since the wiring layer is generally not left on most of the scribe lines, the reticle of the wiring layer is formed with a reticle of the contact hole. It will have the same exposure area as the reticle. Therefore,
As shown in FIG. 5B, the end of the interlayer film 2 and the end of the photoresist 5 come to the same place. When the wiring layer 4 is etched using the photoresist 5 as a mask in this state, the etching residue 4c of the wiring layer 4 is formed at the step portion of the interlayer film 2 as shown in FIG. During the etching and in the process after the etching, they are peeled off and become dust, which causes a reduction in yield such as a short circuit of the wiring.
In order to prevent the peeling, as shown in FIGS. 8A to 8C, at the time of photolithography of the contact hole, there is no pattern inside the light shielding region 6 as shown in FIG. A method of exposing and removing the photoresist in the wafer peripheral region 13 using the reticle described above is conceivable. FIG. 8A is a cross-sectional view of the outermost peripheral edge of the device pattern after the interlayer film 2 is grown and the contact hole is patterned. However, since the peripheral portion of the wafer removes the photoresist, The photoresist is not shown in this figure. By this method, the interlayer film 2 in the wafer peripheral region 13 is completely removed by etching, and since the step of the interlayer film 2 cannot be formed as shown in FIG. However, in this method, after exposing the device area on the wafer, the reticle of the exposure apparatus must be replaced with a peripheral reticle and the alignment and exposure steps must be performed again, so that the throughput is greatly reduced.

As a solution to the decrease in the throughput, although different in purpose, Japanese Patent Laid-Open Publication No. Hei 3-23759 proposes a method of providing a region for full-surface exposure in a reticle on which a pattern of a semiconductor chip is formed. This is Figure 7
As shown in FIG. 5, a peripheral exposure area 16 is provided in a vacant area other than the device pattern 17 on the reticle with a light-shielding area interposed therebetween. If this reticle is used, it is not necessary to replace or align the reticles again, so that the throughput is improved accordingly.

[0009]

However, the peripheral exposure of the wafer is performed, for example, by the method described in Japanese Patent Laid-Open No. 3-23 / 1990.
Using a reticle such as that proposed in U.S. Pat. Moreover, since the area of the reticle is limited, the device pattern on the reticle is set so that the number of semiconductor chips is maximized in order to reduce the number of exposures per wafer. Therefore, since the area on the reticle that can be used for full-surface exposure is small, the number of exposures increases and it takes time to expose the peripheral portion of the wafer.

As described above, according to the conventional technique, it is impossible to prevent the peeling of the wiring layer occurring at the step portion of the interlayer film at the outermost peripheral edge of the device pattern on the wafer and the problem of the throughput at the same time.

An object of the present invention is to prevent the peeling without sacrificing the throughput, and to improve the yield of semiconductor device manufacturing.

[0012]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a plurality of photolithography steps, wherein a resist-covered region formed in at least one photolithography step is formed. In addition, it is characterized in that it is larger than a resist-covered region formed in a photolithography step before the photolithography step.

The method of claim 2 is a method of manufacturing a semiconductor device having a plurality of photolithography steps for performing step-and-repeat exposure.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a plurality of photolithography steps of exposing a positive resist by a step-and-repeat method. It is characterized in that the repeat margin of the reticle used in the process is smaller than the repeat margin of the reticle used in the photolithography process before the photolithography process.

More specifically, in the method of manufacturing a semiconductor device according to the present invention, the step of performing the first photolithography using the first reticle is different from the step of exposing the first reticle. Second using the second reticle
Performing photolithography. In the step-and-repeat exposure method, the first method is used.
Performing a first photolithography process using the reticle of the present invention and performing a second photolithography process using a second reticle having a different exposure region due to a difference in the width of the repeat margin from the first reticle. Contains.

[0016]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1A is a cross-sectional view of a main part of a semiconductor wafer during one step of an embodiment of a method of manufacturing a semiconductor device according to the present invention, and FIG. 1B is a step after FIG. Inside sectional view,
FIG. 2C is a cross-sectional view in a step after FIG.
Is a reticle of a contact hole used in the embodiment, and (b) is a reticle of a wiring.

FIG. 1A shows an interlayer film 2 on a semiconductor substrate 1.
After a 5000A oxide film is grown by a CVD method, a photoresist 3 is applied by a spin coater, exposed using a reticle for a contact hole, and then developed to the outermost periphery of a device pattern area on a wafer. It is sectional drawing in the part of the edge 14.

Next, the interlayer film 2 is anisotropically etched.
After etching the photoresist 3 and stripping the photoresist 3,
Tungsten to become the wiring layer 4 is deposited by CVD method for 500
Grow 0A. Then, as shown in FIG. 2, for example, 5 μm
When a reticle having a small exposure area is used to perform a 1/5 reduction exposure of the wiring layer 4, the interlayer film 2 is exposed as shown in FIG.
The edge of the photoresist 5 comes to the inside of the wafer by 1 μm with respect to the edge of the wafer.

In this state, if the wiring layer 4 is etched using the photoresist 5 as a mask, the wiring layer 4a at the step portion of the interlayer film 2 remains firmly without being etched as shown in FIG. Does not occur.

As shown in FIG. 1C, the wiring layer 4a at the stepped portion of the interlayer film 2 remains firmly without being etched, so that peeling does not occur and a reduction in yield due to the peeled dust can be prevented. In this embodiment, tungsten is used as the wiring layer. However, it is obvious that the present invention can be applied to the case of aluminum, polysilicon, or the like.

The manufacturing method described above can be similarly applied to an exposure method by a step-and-repeat method using a positive resist. In other words, referring to FIG. 1 again, a reticle having a repeat margin of, for example, 10 μm is used in the process of manufacturing the contact hole of FIG. 1A, and the repeat margin is reduced in the process of manufacturing the wiring layer of FIG. When a 5 μm reticle is used, a 1/5 reduction exposure is performed. Therefore, as shown in FIG. 1B, the edge of the photoresist 5 comes to the inside of the wafer by 1 μm with respect to the edge of the interlayer film 2. As shown in FIG. 1C, the wiring layer 4a at the step portion of the interlayer film 2 remains without being etched and does not peel off.

On the other hand, the only difference between the exposure areas of the reticles shown in FIGS. 2A and 2B is the difference in the width of the repeat margin. No part can be made. Therefore, the number of steps is exactly the same as in the prior art, and peeling can be prevented without sacrificing throughput.

As described above, the present invention adopts a method of using reticles having different repeat margins depending on the process, so that the contact step is covered with the resist and is not etched, so that dust is generated. In addition, there is an effect that a method of manufacturing a semiconductor device can be provided in which the number of steps is not increased as compared with the conventional method and there is no fear of peeling at the outermost peripheral end.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view of a main part of a semiconductor wafer during one step of an embodiment of a method for manufacturing a semiconductor device according to the present invention;
(B) is a cross-sectional view in one step after (a), (c) is
It is sectional drawing in one process after (b).

2A is a reticle of a contact hole used in the embodiment, and FIG. 2B is a reticle of a wiring.

FIG. 3A is a general explanatory diagram of a repeat margin on a reticle, and FIG. 3B is a general explanatory diagram of an exposure region and a repeat margin on a wafer when step exposure is performed.

FIG. 4 is a general plan view when a device pattern is exposed and transferred to a semiconductor wafer.

FIG. 5A is a cross-sectional view of a main part of a semiconductor wafer during one step of an embodiment of a conventional method for manufacturing a semiconductor device,
(B) is a cross-sectional view in one step after (a), (c) is
It is sectional drawing in one process after (b).

FIG. 6 is a plan view of a reticle for peripheral exposure used in a conventional example.

FIG. 7 is a plan view of a conventional reticle in which a device pattern region and a peripheral exposure region are mixed.

FIG. 8A shows a second example of a conventional method for manufacturing a semiconductor device.
FIG. 3B is a cross-sectional view of a main part of the semiconductor wafer during one step of the embodiment example of FIG.
FIG. 7B is a cross-sectional view in a step after FIG.

[Explanation of symbols]

1 semiconductor substrate 2 interlayer film 3,5 photoresist 4, 4a, 4d wiring layer 4b etching residue of the wiring layers 6, 6 ₁ the step portion of the wafer remaining wiring layers in the peripheral region 4c interlayer film 2, 6 ₂ shielding region 7 Exposed area by reticle for contact hole 8 Repeat margin 9 Device area 9 ₁ First device area 9 ₂ Second device area 10 Exposure area 10 ₁ First exposure area 10 ₂ Second exposure area 11 Semiconductor wafer 12 Device pattern exposure area on wafer 13 Wafer peripheral area 14 Outermost peripheral edge of device pattern area on wafer 15, 16 Peripheral exposure area on reticle (no pattern) 17 Device pattern area on reticle 18 Edge of interlayer film 2 19 Edge of photoresist 5

Claims (3)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a plurality of photolithography steps, wherein a resist coating area formed in at least one photolithography step is formed in a photolithography step before the photolithography step. A method of manufacturing a semiconductor device. 2. A method of manufacturing a semiconductor device having a plurality of photolithography steps for performing step-and-repeat exposure, wherein a resist-covered region formed in at least one photolithography step is a photolithography step prior to the photolithography step. A method for manufacturing a semiconductor device, wherein the semiconductor device is larger than a resist-covered region formed in a step. 3. A method of manufacturing a semiconductor device having a plurality of photolithography steps of exposing a positive resist by a step-and-repeat method, wherein a repeat margin of a reticle used in at least one photolithography step is reduced. A method for manufacturing a semiconductor device, wherein a repeat margin of a reticle used in a photolithography process before a photolithography process is smaller than a reticule used in the photolithography process.