JPH05267935A - Oscillating circuit for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce an area of the oscillating circuit in the semiconductor integrated circuit, and to obtain a stable oscillation without consuming excessive power by connecting selectively in parallel one or two or more sets of plural transistor sets in accordance with an oscillation frequency to be used. CONSTITUTION:In the inside of an IC, an amplifying inverter 40 and a self-bias resistance 42 are connected in parallel, and also, connected to terminals 44, 46 of the IC. In the outside of the IC, a crystal resonator 48 is connected to the terminals 44, 46, and also, grounded through capacitors 50, 52. Also, the inverter 40 contains three resistor sets 58, 60 and 62, and by switching switches 60c, 60d of a second transistor set 60 and switches 62c, 62d of a third transistor set 62, size of the inverter 40 can be varied. In such a way, in accordance with an oscillation frequency to be used, optimal size of the inverter can be selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit for semiconductor integrated circuits. In recent years, LSI has been used in various industries,
Its uses are also diverse. When an LSI is used for an oscillation circuit, the same LSI is not limited to one oscillation frequency, and is used at various frequencies. Therefore, it is necessary to change the amplification degree of the amplification inverter in the oscillation circuit according to the frequency.

[0002]

2. Description of the Related Art FIG. 9 shows the structure of an oscillator circuit. In FIG. 9 (A), inside the IC, an amplification inverter 10 and a self-biasing resistor 12 are connected in parallel and are also connected to terminals 14 and 16 of the IC. I
Outside C, the crystal oscillator 18 is connected to the terminals 14 and 16 and is grounded via the capacitors 20 and 22. An inverter 24 is connected to the terminal 16 inside the IC, and an oscillation signal 26 having a predetermined frequency is output from the inverter 24.

[0003]

In the oscillator circuit shown in FIG. 9A, the size of the inverter 10 is fixed regardless of the frequency used, so that there is the following problem.

First, considering the case where the frequency is high, in this case, the absolute value of the negative resistance becomes large as shown in the negative resistance characteristic of the oscillation circuit of FIG. It becomes difficult to oscillate. To prevent this, it is necessary to increase the size of the inverter 10 when the frequency is high.

On the other hand, considering the case where the frequency is low, in this case, the oscillation circuit easily oscillates, but the through current flowing from the power source side through the inverter 10 to the ground side is large. More specifically, FIG. 9B shows the configuration of the inverter 10. When the frequency is low, the through current 32 that flows from the power supply V _CC side to the ground side through the P-type transistor 28 and the N-type transistor 30. Will grow. in this way,
If the through current 32 flowing into the ground side is large, there is a problem that the ground level rises and the threshold value of the MOS transistor inside the IC is changed. To prevent this, it is necessary to reduce the size of the inverter 10 when the frequency is low.

As described above, the inverter 10 of the oscillation circuit
When the size is fixed, there is a problem when the frequency is high and when the frequency is low, and it is necessary to change the size of the inverter 10 according to the frequency used.

In order to solve the above-mentioned problems, Japanese Patent Laid-Open No. Sho 63-63
In the semiconductor integrated circuit for an oscillation circuit disclosed in Japanese Patent Laid-Open No. 82108, a plurality of inverters having different mutual conductances are provided in the IC, and one of the plurality of inverters is selected and used according to the frequency to be used. ..
That is, when the frequency is high, the inverter with a large mutual conductance is selected and used, while when the frequency is low, the inverter with a small mutual conductance is selected and used, which allows stable oscillation over a wide range of frequencies. You can get it.

However, in the configuration of the above publication, there is a problem that the chip size of the IC becomes large because a plurality of inverters having different mutual conductances are previously provided inside the IC. Therefore, it is necessary to reduce the IC chip size and achieve low power consumption.

Therefore, an object of the present invention is to make the size of the amplifying inverter variable so that the area of the oscillation circuit in the semiconductor integrated circuit can be reduced, and stable oscillation can be obtained without consuming extra power. An object of the present invention is to provide an oscillation circuit for a semiconductor integrated circuit that can be used.

[0010]

According to the present invention, in an oscillation circuit for a semiconductor integrated circuit including an amplification inverter (40), the amplification inverter (40) includes a plurality of transistor groups (58, 60, 62). A plurality of transistor groups (58, 60, 6) are provided according to the oscillation frequency used.
It is characterized in that the transistor size is made variable by selectively connecting in parallel one or more sets of 2).

FIG. 1 shows an oscillator circuit according to the principles of the present invention. In FIG. 1A, inside the IC, an amplification inverter 40 and a self-biasing resistor 42 are connected in parallel and are also connected to terminals 44 and 46 of the IC. Outside the IC, the crystal oscillator 48 is connected to the terminal 4
4, 46 and capacitors 50, 52
Grounded through. An inverter 54 is connected to the terminal 46 inside the IC.
4 outputs an oscillation signal 56 having a predetermined frequency.

The structure of the inverter 40 is shown in FIG. 1 (B). In FIG. 1B, the inverter 40 includes three transistor groups 58, 60, 62.
The first transistor group 58 includes a P-type transistor 58a and an N-type transistor 58b, and the gates of the transistors 58a and 58b are both the input signal IN.
It is connected to the. The second transistor group 60 includes a P-type transistor 60a and an N-type transistor 60b,
The gate of the transistor 60a is switch-connected to the input signal IN or the power supply V _CC via the switch 60c, and the gate of the transistor 60b is switch-connected to the input signal IN or the ground side via the switch 60d. Similarly, the third transistor set 62 includes the P-type transistor 6
2a, an N-type transistor 62b, and a transistor 6
The gate of 2a receives the input signal IN via the switch 62c.
Alternatively, the transistor 62b is connected to the power source V _CC by switching.
The gate of is switched and connected to the input signal IN or the ground side through the switch 62d.

[0013]

In the inverter shown in FIG. 1B, the switches 60c and 60d of the second transistor set 60, and
The size of the inverter 40 (transistor size) can be changed by switching the switches 62c and 62d of the third transistor set 62.

That is, the gates of the transistors 60a and 60b of the second transistor group 60 are respectively connected to the power source V _CC and the ground side, and similarly, the gates of the transistors 62a and 62b of the third transistor group 62 are respectively powered. When connected to V _CC and the ground side, only the first transistor set 58 is in the selected state, and the second transistor set 60 and the third transistor set 62 are in the non-selected state. Therefore, the size of the inverter 40 is
It is defined by the first transistor set 58.

Although the gates of the transistors 60a and 60b of the second transistor group 60 are both connected to the input signal IN, the gates of the transistors 62a and 62b of the third transistor group 62 are the power source V _CC and the ground, respectively. When connected to the side, the first transistor set 58 and the second transistor set 60 are in the selected state,
The third transistor set 62 is in the non-selected state. Therefore, the size of the inverter 40 is determined by the first transistor set 58 and the second transistor set 60.

Further, the gates of the transistors 60a and 60b of the second transistor group 60 are both connected to the input signal IN, and similarly, the gates of the transistors 62a and 62b of the third transistor group 62 are both input signal I.
When connected to N, the first transistor set 5
8, the second transistor set 60, and the third transistor set 62 are all in the selected state. Therefore, the size of the inverter 40 depends on these three transistor groups 58,
60, 62.

As described above, the second transistor group 60
Since the size of the inverter 40 can be changed by switching the switches 60c and 60d of No. 6 and the switches 62c and 62d of the third transistor set 62, the optimum inverter size is selected according to the oscillation frequency to be used. be able to.

Further, as compared with the case where a plurality of different types of inverters are provided, the area of the oscillating circuit in the semiconductor integrated circuit can be made smaller, and extra power is not consumed, and stable oscillation can be obtained. ..

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows an inverter of the oscillation circuit according to the embodiment of the present invention.

The inverter shown in FIG. 2 has the same structure as that of the inverter shown in FIG. 1B, and switches 60c, 6 of the second transistor set 60 are selected depending on the oscillation frequency used.
0d and the switch 62 of the third transistor set 62
The size of the inverter can be changed by switching between c and 62d. That is, when the frequency is low, the gates of the transistors 60a and 60b of the second transistor group 60 are connected to the power supply V _CC and the ground side, respectively, and similarly, the transistors 62a and 62a of the third transistor group 62 are connected.
The gates of 62b are connected to the power supply V _CC and the ground side, respectively, and only the first transistor set 58 is in the selected state.
Therefore, the size of the inverter is defined by the first transistor set 58 and is the smallest size.

When the frequency is high, the gates of the transistors 60a and 60b of the second transistor set 60 are both connected to the input signal IN, and both the first transistor set 58 and the second transistor set 60 are connected. The selected state is set. Therefore, the size of the inverter is determined by the first transistor set 58 and the second transistor set 60 and becomes large.

When the frequency is higher, the gates of the transistors 60a and 60b of the second transistor set 60 are both connected to the input signal IN, and the gates of the transistors 62a and 62b of the third transistor set 62 are similarly set. Are connected to the input signal IN, and the three first transistor sets 58, the second transistor set 60, and the third transistor set 62 are all selected. Therefore, the size of the inverter is the first transistor set 5
8, the second transistor set 60, and the third transistor set 62 determine the maximum size.

As described above, according to the inverter of FIG. 2, the size of the inverter can be changed according to the oscillation frequency to be used by switching the switches 60c, 60d, 62c and 62d, that is, the frequency is increased. As such, the size of the inverter can be increased.

In the inverter of FIG. 2, three transistor groups 58, 60, 62 are provided, but the number of transistor groups of the inverter is not limited to three, and two transistor groups are provided.
It may be one or four or more.

In the inverter shown in FIG. 2, the switches 60c, 60d, 62c and 62d may be constituted by a mask option using a wiring mask, may be stored as ROM data, or may be selected by an external terminal. Good. Hereinafter, a configuration for switching the transistor size of the inverter of the oscillation circuit will be described.

First, FIG. 3 shows a first configuration in which the transistor size of the inverter is switched by a mask option. In FIG. 3A, the inverter includes three transistor groups 64, 66, and 68, the first transistor group 64 includes a P-type transistor 64a and an N-type transistor 64b, and similarly, the second transistor group. The set 66 includes a P-type transistor 66a and an N-type transistor 66b, and the third transistor set 68 includes a P-type transistor 68a and an N-type transistor 68b.
The transistors 64a, 64b, 66a, 66b, 6
The gates of 8a and 68b are connected to the input signal IN, and the transistors 64a and 64b of the first transistor set 64 are connected.
And the coupling portion 66c of the transistors 66a and 66b of the second transistor group 66 are connected to the output side OUT via the switch 70, and the transistors 68a and 68b of the third transistor group 68 are coupled to each other. The coupling portion 68c is directly connected to the output OUT.

When the switch 70 is off, only the third transistor set 68 is in the selected state,
The transistor size of the inverter is small. On the other hand, when the switch 70 is in the on state, all the three transistor groups 64, 66, 68 are in the selected state, the transistor size of the inverter is large, and three times as large as when the switch 70 is off. Is the size.

The circuit of FIG. 3 (A) is the same as the circuit of FIG. 3 (B).
Achieved with a line structure. In FIG. 3B, the input signal I
The N polysilicon layer 72 includes a transistor set 64,
Gate layers 74, 76 and 78 for 66 and 68 are in an orthogonal state
Are joined together. Reference numerals 80 and 82 respectively indicate P
Channel transistor region (diffusion layer), N-channel transistor
A region for the transistor (diffusion layer) is shown, and in the P-type region 80,
Power supply V _CCAluminum layer 84 for contact is contact 84a,
84b, and the N-type region 82 has a ground side V
_SSAluminum layer 86 for use as contacts 86a, 86b
Are joined by. Reference numeral 88 is an output-side OUT
The output aluminum layer 88 is a
Contact 88a with the P-type region 80,
It is coupled to N-type region 82 at contact 88b. Na
The reference numeral 90 indicates an N-well boundary.

In the above structure, along the gate layer 74, the transistors 64a of the first transistor set 64,
64b are formed, and similarly, along the gate layer 76, the transistors 66a of the second transistor set 66,
66b is formed, and the transistors 68a and 68b of the third transistor set 68 are formed along the gate layer 78.

When the contacts 88c and 88d of the output side aluminum layer 88 are not coupled to the P-type region 80 and the N-type region 82, respectively, only the third transistor set 68 is in the selected state and the inverter of the inverter is not selected. The transistor size is small. This is switch 7 in FIG.
This corresponds to the case where 0 is in the off state. On the other hand, the contacts 88c and 88d of the aluminum layer 88 on the output side are P
When bonded to the mold region 80 and the N-type region 82,
All three transistor groups 64, 66, 68 are in the selected state, and the transistor size of the inverter is large,
The size is three times as large as that when the contacts 88c and 88d are not joined. This corresponds to the case where the switch 70 is on in FIG.

As described above, in the structure of FIG. 3, the contacts 88c, 88d of the aluminum layer 88 on the output side are provided.
Depending on whether or not is coupled to the P-type region 80 and the N-type region 82, that is, the mask option can change the transistor size of the inverter.

Next, FIGS. 4 and 5 show a second configuration in which the transistor size of the inverter is switched by a mask option, and FIGS. 4 and 5 show the cases where the transistor size is large and small, respectively. Show. Note that FIG.
Since the circuit of FIG. 5A is similar to the circuit of FIG. 2 described above, in FIGS. 4A and 5B, the same parts as those of the circuit of FIG. Is omitted.

First, in FIG. 4A, the switches 60c,
Since 60d, 62c, and 62d are all switched to the input signal IN side, three transistor groups 58, 60,
All of 62 are in the selected state. Therefore, the transistor size of the inverter is three transistor sets 58,6.
0,62, and the transistor size is large.

The circuit of FIG. 4A is achieved by the wiring structure of FIG. 4B. In FIG. 4B, the input signal I
The N polysilicon layer 92 includes transistor sets 58,
Polysilicon gate layers 94, 96, 98 for 60, 62
Are arranged in an orthogonal state, and the gate layers 94, 96, 98
Are coupled to polysilicon layer 92 at contacts 94a, 96a, 98a, respectively. Reference numerals 100 and 10
2 denotes a P-channel transistor region (diffusion layer) and an N-channel transistor region (diffusion layer), respectively, and an aluminum layer 104 for a power supply V _CC is coupled to the P-type region 100 by contacts 104a and 104b. Further, an aluminum layer 106 for the ground side V _SS is coupled to the N-type region 102 by contacts 106a and 106b. Reference numeral 108 indicates an aluminum layer for the output side OUT, and the aluminum layer 108 is the contact 108.
a and 108b are bonded to the P-type region 100,
The contacts 108c and 108d are coupled to the N-type region 102. Note that reference numeral 110 indicates an N-well boundary.

In the above structure, the transistors 58a, 58a of the first transistor group 58 are arranged along the gate layer 94.
58b is formed, and similarly, along the gate layer 96, the transistors 60a of the second transistor group 60,
60b is formed, and the transistors 62a and 62b of the third transistor set 62 are formed along the gate layer 98.

Then, the second transistor group 60, the third transistor group 60
Since the gate layers 96 and 98 of the transistor set 62 of FIG. 3 are coupled to the polysilicon layer 92 for the input signal IN via the contacts 96a and 98a, respectively, the three transistor sets 58, 60 and 62 are all in the selected state. .. Therefore, the transistor size of the inverter is determined by the three transistor groups 58, 60, 62, and the transistor size is large.

Next, in FIG. 5A, the switches 60c,
62c is switched to the power supply V _CC side, and the switch 6
Since 0d and 62d are switched to the ground side, the first
Only the transistor group 58 of is selected. Therefore,
The transistor size of the inverter is determined by the first transistor set 58, and the transistor size is small.

The circuit shown in FIG. 5A is achieved by the wiring structure shown in FIG. 5B. In FIG. 5B, the input signal I
A polysilicon gate layer 94 for the first transistor set 58 is arranged in an orthogonal state on the N polysilicon layer 92, and the gate layer 94 is coupled to the polysilicon layer 92. The polysilicon gate layers 96-1 and 96-2 for the second transistor set 60 and the polysilicon gate layers 98-1 and 98 for the third transistor set 62 are provided.
-2 is arranged parallel to the polysilicon gate layer 94. Reference numerals 100 and 102 denote a P-channel region (diffusion layer) and an N-channel region (diffusion layer), respectively. In the P-type region 100, an aluminum layer 104 for a power supply V _CC is coupled by contacts 104a and 104b. Further, the N-type region 102 has a ground-side V _SS luminium layer 106 coupled thereto by contacts 106a and 106b. Reference numeral 108 indicates an aluminum layer for the output side OUT, and the aluminum layer 108 is the contact 108.
a and 108b are bonded to the P-type region 100,
The contacts 108c and 108d are coupled to the N-type region 102. In addition, the gate layers 96-1 and 98-1
Are coupled to the aluminum layer 104 at contacts 96-1a and 98-1a, and are connected to the gate layers 96-2 and 98-2.
Are coupled to aluminum layer 106 at contacts 96-2a and 98-2a. Incidentally, reference numeral 110 is N-
Indicates a well boundary.

In the above structure, along the gate layer 94, the transistors 58a of the first transistor set 58,
58b is formed. Further, the gate layers 96-1, 96-
2, transistors 60a and 60b of the second transistor set 60 are formed, and the gate layer 98 is formed in the same manner.
Transistors 62a and 62b of the third transistor set 62 are formed along −1 and 98-2.

The gate layers 96-1 and 96-2 of the transistors 60a and 60b of the second transistor group 60 are then included.
Are coupled to the aluminum layers 104 and 106 via contacts 96-1a and 96-2a, respectively, and similarly transistor 62 of the third transistor set 62.
The gate layers 98-1 and 98-2 of a and 62b are coupled to the aluminum layers 104 and 106 via contacts 98-1a and 98-2a, respectively. Therefore, the second transistor set 60 and the third transistor set 62 are in the non-selected state, and only the first transistor set 58 is in the selected state. Therefore, the transistor size of the inverter is defined by the first transistor set 58 and the transistor size is small.

Comparing the wiring structure of FIG. 4 (B) with the wiring structure of FIG. 5 (B), the polysilicon gate layer 92 and the masks for the gate layers 94, 96, 98, and the gate layers 96, 98 are compared. It is understood that the transistor size of the inverter can be changed by switching a total of two masks for contact for.

Next, FIG. 6 shows a third configuration in which the transistor size of the inverter is switched by a mask option, and the wiring structure of FIG. 6 corresponds to the circuit of FIG. 2 described above.

In FIG. 6, the polysilicon gate layer 11 for the first transistor set 58 is provided in parallel with the portions 112a and 112b of the polysilicon layer 112 for the input signal IN.
4-1 and 114-2, polysilicon gate layers 116-1 and 116-2 for the second transistor set 60, and polysilicon gate layers 118- for the third transistor set 62.
1, 118-2 are arranged. Reference numerals 120 and 122
Indicate a P-channel region (diffusion layer) and an N-channel region (diffusion layer), respectively. In the P-type region 120, an aluminum layer 124 for a power supply V _CC is provided with contacts 124a,
And an N-type region 122 has an aluminum layer 126 for the ground side V _{SS in} contact 126.
a and 126b are connected. Reference numeral 128 indicates an aluminum layer for the output side OUT, and the aluminum layer 1
Reference numeral 28 denotes contacts 128a and 128b, which are P-type regions 12
0 and coupled to contacts 128c, 128
It is coupled to the N-type region 122 at d. Note that reference numeral 13
0 indicates an N-well boundary.

In the above structure, the gate layer 114-
1, 114-2, transistors 58a and 58b of the first transistor group 58 are formed, and similarly,
Transistors 60a and 60b of the second transistor set 60 are formed along the gate layers 116-1 and 116-2, and transistors 62a of the third transistor set 62 are formed along the gate layers 118-1 and 118-2. , 62b are formed.

The gate layer 116-1 of the second transistor set 60 and the gate layer 118-1 of the third transistor set 62 are connected to the contacts 116-1a and 11-1, respectively.
8-1a is coupled to the polysilicon layer 112 for the input signal IN, and is also the gate layer 11 of the second transistor set 60.
6-2 and the gate layer 118 of the third transistor set 62
-2 are contacts 116-2a and 118-2a, respectively.
When coupled to the polysilicon layer 112 for the input signal IN at, all three transistor groups 58, 60 and 62 are in the selected state. Therefore, the transistor size of the inverter is determined by the three transistor groups 58, 60, 62, and the transistor size is large.

On the other hand, the gate layer 116-1 of the second transistor set 60 and the gate layer 118-1 of the third transistor set 62 are connected to the contacts 116-1b and 118, respectively.
−1b to the aluminum layer 124, and the gate layer 116-2 of the second transistor set 60 and the gate layer 118-2 of the third transistor set 62 are connected to the aluminum layer 124 at the contacts 116-2b and 118-2b, respectively. 1
26, the second transistor set 60 and the third transistor set 62 are in the non-selected state, and
Only the transistor group 58 of is selected. Therefore,
The size of the inverter is defined by the first transistor set 58, and the size of the transistors is small.

In the wiring structure shown in FIG. 6, the gate layers 116-1 and 116-2 of the second transistor group 60 and the third transistor group 60 are formed.
Layers 118-1 and 118- of the transistor set 62 of
By changing the position of the two contacts, ie,
Gate layers 116-1, 116-2, 118-1, 118
The transistor size of the inverter can be changed by switching the contact mask for -2 (by switching one mask for contact).

Next, FIG. 7 shows a configuration in which the transistor size of the inverter is switched by ROM data. A circuit diagram of an inverter is shown in FIG. 7A, and the inverter includes a first transistor set 132 and a second transistor set 134. First transistor set 13
2 includes a P-type transistor 132a and an N-type transistor 132b, and similarly, the second transistor set 1
34 includes a P-type transistor 134a and an N-type transistor 134b. A second connecting portion 132c of the transistors 132a and 132b of the first transistor set 132;
134a, 13 of the transistor set 134 of
The coupling portion 134c of 4b is coupled to the output OUT.

Reference numeral 136 indicates the first transistor group 13
4 shows four control circuits for four N-type transistors 138a, 138b, 140a, 1
40b and two inverters 142 and 144 are included. Note that the symbol IN represents the first transistor set 132,
An input signal to the second transistor set 134 is shown, and a symbol CONT is a control signal to the control circuit 136.

In the above structure, when the control signal CONT is at "H" level, the transistors 138a and 138a.
0a is off, and transistors 138b and 140
Since b is in the ON state, the input signal IN is supplied to the gates of the transistors 132a and 132b of the first transistor set 132 via the transistors 138b and 140b. Therefore, in this case, the first transistor set 132 is in the selected state.

On the other hand, when the control signal CONT is at "L" level, the transistors 138a and 140a are in the on state and the transistors 138b and 140b are in the off state, so that the power supply V _CC passes through the transistor 138a. Transistor 132 of first transistor set 132
It is supplied to the gate of a, and the ground side is supplied to the gate of the transistor 132b of the first transistor 132 via the transistor 140a. Therefore, in this case, the first transistor set 132 is in the non-selected state.

As described above, by switching the level of the control signal CONT to the control circuit 136, the first transistor set 132 can be switched to the selected state or the non-selected state.

A second control circuit (not shown) similar to the control circuit 136 is also connected to the second transistor set 134, and the second control circuit causes the second control circuit to operate as a second control circuit.
The transistor set 134 can be switched to the selected state or the non-selected state.

Therefore, according to the inverter of FIG. 7A, the first transistor set 132 and the second transistor set 134 are controlled by the control circuit 136 and the second control circuit.
Can be switched to a selected state or a non-selected state to change the transistor size of the inverter. That is, when only one of the transistor groups 132 and 134 is selected, the transistor size of the inverter is small, while
When both of the two are in the selected state, the transistor size of the inverter is large.

A control signal CONT to the control circuit 136.
May be output as ROM data, or I
It may be supplied from the external terminal of C. And FIG. 7 (B)
Shows an example of ROM data. In FIG. 7B, one of the transistors 146 and 148 is an enhancement-type or depletion-type transistor.
The control signal CONT from the coupling unit 150 of 6,168 is
It is an "H" level or an "L" level.

In the embodiments described above, the present invention is applied to the inverter in the oscillation circuit, but the present invention can also be applied to an oscillation circuit including a NAND circuit or a NOR circuit instead of the inverter. That is, a semiconductor device according to another embodiment of the present invention is shown in FIG.
Shows a NAND circuit, and FIG. 8B shows a NOR circuit. When using a NAND circuit or a NOR circuit, there is an advantage that power consumption can be reduced.

First, in FIG. 8A, the NAND circuit includes a first transistor set 152, 152 ', a second transistor set 154, 154', and a third transistor set 156, 156 '. Reference symbols A1 and A2 indicate input signals, and reference symbol B indicates output signals. The first transistor set 152 includes a P-type transistor 152a and N-type transistors 152b and 152c, and the first transistor set 152 ′ includes a P-type transistor 152′a. The second transistor set 154 includes a P-type transistor 154a and N-type transistors 154b and 154c.
And the second set of transistors 154 'includes a P-type transistor 154'a.
The inputs of the gates of 4b, 154c and 154'a are switched by switches 158a, 158b, 158c and 158'a, respectively. Similarly, the third transistor set 156 includes a P-type transistor 156a and N-type transistors 156b and 156c, and the third transistor set 156 'includes a P-type transistor set 156'a. 15
The gates of 6c and 156'a are connected to the switch 16 respectively.
The input can be switched by 0a, 160b, 160c, 160'a.

In the above structure, the switches 158a,
158b, 158c, 158'a and switch 160
By switching a, 160b, 160c, 160'a, the transistor size of the NAND circuit can be changed.

That is, the second transistor set 154,
When both 154 'and the third transistor set 156, 156' are in the non-selected state, only the first transistor set 152, 152 'is in the selected state, and the transistor size of the NAND circuit is the first. Transistor set 15
2,152 ', and the transistor size is small. Further, only one of the second transistor set 154, 154 'or the third transistor set 156, 156' is, for example, the second transistor set 154, 15 '.
When 4'is in the selected state, the first transistor set 152, 152 'and the second transistor set 154, 1
54 'is in the selected state, and the transistor size of the NAND circuit is determined by the first transistor set 152, 152' and the second transistor set 154, 154 '.
The transistor size is large. Further, the second transistor set 154, 154 'and the third transistor set 15
When both 6 and 156 'are in the selected state, three transistor sets 152, 152'; 154, 154 ';
156 and 156 'are all in the selected state, and the transistor size of the NAND circuit is set to these three transistor groups 152, 152'; 154, 154 '; 156, 15
6 ', which is the maximum transistor size.

Next, in FIG. 8B, the NOR circuit includes a first transistor set 162, 162 ', a second transistor set 164, 164', and a third transistor set 166, 166 '. , Symbols A1 and A2 indicate input signals, and symbol B indicates output signals. The first transistor set 162 includes P-type transistors 162a and 162a.
b, an N-type transistor 162c, and the first transistor set 162 'includes an N-type transistor 162'a. The second transistor set 164 includes P-type transistors 164a and 164b and an N-type transistor 164c.
And the second set of transistors 164 'includes an N-type transistor 164'a, the transistors 164a, 1
The gates of 64b, 164c and 164'a are respectively
The inputs are switched by the switches 168a, 168b, 168c, 168'a. Similarly, the third transistor set 166 includes P-type transistors 166a and 166b and an N-type transistor 166c.
And a third transistor set 166 'includes an N-type transistor 166'a, the transistors 166a, 1
The gates of 66b, 166c and 166'a are respectively
The inputs are switched by the switches 170a, 170b, 170c, 170'a.

In the above structure, the switches 168a,
168b, 168c, 168'a and switch 170
The transistor size of the NOR circuit can be changed by switching a, 170b, 170c, 170'a.

That is, the second transistor set 164,
When both 164 'and the third transistor set 166, 168' are in the non-selected state, only the first transistor set 162, 162 'is in the selected state, and the transistor size of the NOR circuit is the first. Transistor group 16
2, 162 ', and the transistor size is small. Further, only one of the second transistor set 164, 164 'or the third transistor set 166, 166' is, for example, the second transistor set 164, 16 '.
When 4'is in the selected state, the first transistor set 162, 162 'and the second transistor set 164, 1
64 ′ is in the selected state, and the transistor size of the NOR circuit is determined by the first transistor set 162, 162 ′ and the second transistor set 164, 164 ′, and the transistor size is large. Further, the second transistor set 164, 164 'and the third transistor set 166,
If both 166 'are in the selected state, three transistor sets 162, 162'; 164, 164 '; 16
6, 166 'are all in the selected state, and the transistor size of the NOR circuit is set to these three transistor groups 16
2, 162 '; 164, 164'; 166, 166 ', and the transistor size is the maximum.

[0063]

As described above, according to the present invention,
Since the size of the inverter can be changed, the optimum inverter size can be selected according to the oscillation frequency used.

Further, as compared with the case where a plurality of different types of inverters are provided, the area of the oscillation circuit in the semiconductor integrated circuit can be reduced, and extra oscillation is not consumed, so that stable oscillation can be obtained. ..

The present invention can be applied not only to the inverter in the oscillation circuit for semiconductor integrated circuit, but also to the NAND circuit or the NOR circuit.

[Brief description of drawings]

FIG. 1 shows an oscillator circuit according to the principle of the present invention, (A) shows the overall configuration, and (B) shows the configuration of an inverter.

FIG. 2 shows an inverter of an oscillator circuit according to an embodiment of the present invention.

3A and 3B show a first configuration in which a transistor size of an inverter is switched by a mask option, FIG. 3A shows a circuit diagram, and FIG. 3B shows a wiring structure.

FIG. 4 shows a second configuration (when the transistor size is large) in which the transistor size of the inverter is switched by a mask option, (A) shows a circuit diagram, and (B) shows a wiring structure.

FIG. 5 shows a second configuration (when the transistor size is small) in which the transistor size of the inverter is switched by a mask option, (A) shows a circuit diagram, and (B) shows a wiring structure.

FIG. 6 shows a third configuration in which the transistor size of the inverter is switched by a mask option.

FIG. 7 shows a configuration in which the transistor size of the inverter is switched by ROM data, (A) shows a circuit diagram,
(B) shows an example of ROM data.

FIG. 8 shows a semiconductor device according to another embodiment of the present invention,
(A) shows a NAND circuit, (B) shows a NOR circuit.

9A and 9B show a configuration of an oscillation circuit, FIG. 9A shows an overall configuration, and FIG. 9B shows a configuration of an inverter.

FIG. 10 shows a negative resistance characteristic of an oscillator circuit.

[Explanation of symbols]

 40 ... Inverter 58 ... First transistor set 60 ... Second transistor set 62 ... Third transistor set

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[Procedure amendment]

[Submission date] June 19, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 10

[Correction method] Change

[Correction content]

[Figure 10]

Claims (3)

[Claims] 1. An oscillation circuit for a semiconductor integrated circuit including an amplification inverter (40), wherein the amplification inverter (40) includes a plurality of transistor groups (58, 60, 62) and is adapted to an oscillation frequency to be used. Then, a plurality of transistor groups (58, 60, 62)
An oscillation circuit for a semiconductor integrated circuit, characterized in that one or two or more of them are selectively connected in parallel to make the transistor size variable. 2. The oscillation circuit for semiconductor integrated circuit according to claim 1, wherein a NAND is used instead of the inverter (40).
An oscillation circuit for a semiconductor integrated circuit, comprising a circuit or a NOR circuit. 3. The oscillation circuit for a semiconductor integrated circuit according to claim 1, wherein a crystal oscillator (48) is connected to the inverter (40).