JPH07170167A - Level shifter for ac signal - Google Patents

Level shifter for ac signal

Info

Publication number
JPH07170167A
JPH07170167A JP5313452A JP31345293A JPH07170167A JP H07170167 A JPH07170167 A JP H07170167A JP 5313452 A JP5313452 A JP 5313452A JP 31345293 A JP31345293 A JP 31345293A JP H07170167 A JPH07170167 A JP H07170167A
Authority
JP
Japan
Prior art keywords
inverter
resistor
channel mos
level shifter
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5313452A
Other languages
Japanese (ja)
Inventor
Yasuhiro Sakurai
保宏 桜井
Original Assignee
Citizen Watch Co Ltd
シチズン時計株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd, シチズン時計株式会社 filed Critical Citizen Watch Co Ltd
Priority to JP5313452A priority Critical patent/JPH07170167A/en
Publication of JPH07170167A publication Critical patent/JPH07170167A/en
Pending legal-status Critical Current

Links

Abstract

(57) [Summary] [Purpose] To eliminate the self-excited oscillation of the AC signal level shifter and achieve low power consumption. [Structure] A DC cut capacitor 1, an inverter 3, a first resistor 5 and a second resistor 7 are provided, and a power supply voltage on the high voltage side is divided by the first resistor 5 and the second resistor 7. The operating point of the inverter 3 as an amplifier is set to the midpoint of the inverting operation region of the inverter 3. [Effect] It is possible to provide a level shifter for AC signals having low shunt ratio power by making the amplification factor of the inverter a minimum necessary margin without self-excited oscillation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device having multiple power supplies for handling AC signals, or a plurality of constant voltage generating circuits having different output voltages even with a single power supply. The present invention relates to the configuration of an AC signal level shifter in such an electronic device.

[0002]

2. Description of the Related Art Many electronic devices, such as a digital temperature-compensated crystal oscillator mounted on a mobile phone or a car phone, are provided with a plurality of constant voltage generating circuits and are effectively multi-power sources.

In such a multi-power source electronic device, in order to transmit a signal from a low voltage side to a high voltage side, a level shifter is required unless the voltage difference is small.

If the signal to be transmitted has a direct current level, or if the frequency is low even if it is an alternating current, a general level shifter called a "plow type" may be used.
Since the plow-type level shifter has a low operation speed, it is not suitable for transmitting an AC signal having a high frequency.

Therefore, when an AC signal having a high frequency is transmitted from the low voltage side to the high voltage side, the DC component is usually removed by the DC cut capacitor, and then the amplitude is increased to the voltage level on the high voltage side by using the amplifier. The means of lifting is adopted.

The operating point of an amplifier is normally determined by applying a certain DC bias, but conventionally, the operating point is determined by a so-called feedback resistance in which an input and an output are connected by a resistor. FIG. 3 is a circuit diagram showing the structure of a conventional AC signal level shifter.

The construction of the conventional AC signal level shifter shown in FIG. 3 will be described below. An AC signal on the low voltage side is input to one terminal of the DC cut capacitor 1, the DC component is removed, and the other terminal of the DC cut capacitor 1 is connected to the input of an inverter 3 that operates on a high voltage side power source. The amplitude of the signal is raised to the level on the high voltage side by the amplifying action of the inverter 3.

In order to efficiently amplify the signal,
An operating point as an amplifier must be present at a place where the amplification factor is large, that is, at the midpoint of the inversion operation region of the inverter 3, but by connecting the output of the inverter 3 and the input of the inverter 3 with the feedback resistor 17. The operating point is secured near the midpoint of the inversion operation area of the inverter 3.

[0009]

In the conventional level shifter as shown in FIG. 3, the output of the inverter 3 is a feedback resistor 17.
Since it is fed back to the input of the inverter 3 through the circuit, there is a problem that self-excited oscillation occurs when no AC signal is input.

Further, in the conventional level shifter as shown in FIG. 3, when the inversion operating voltage of the inverter 3 deviates from the half of the power source voltage due to variations in the manufacturing process, the operating point of the amplifier is the amplification factor. There is a risk that the signal will not be correctly transmitted due to the movement to a small area and the amplification efficiency will be reduced. Therefore, there is no choice but to design the amplification factor of the inverter in advance, which causes a problem that power consumption increases.

An object of the present invention is to solve the above problems and provide an AC signal level shifter which does not cause self-oscillation, and an AC signal level shifter of low power consumption.

[0012]

In order to achieve the above object, the AC signal level shifter according to the present invention has the following configuration.

That is, in order to prevent self-excited oscillation, a DC cut capacitor for removing a DC component from an AC signal on the low voltage side, an inverter connecting an input to the DC cut capacitor, a DC cut capacitor and an input of the inverter. A first resistor that connects one terminal to the connection point of
A second resistor connecting one terminal to a connection point between the cut capacitor and the input of the inverter is provided, and the other terminal of the first resistor is connected to the high potential side of the power source on the high voltage side.
The other terminal of the resistor is connected to the low potential side of the high voltage side power source.

Further, in order to achieve low power consumption by setting the amplification factor of the inverter to the minimum necessary margin, the following configuration is adopted.

That is, the inverter is a p-channel MOS
The transistor and the n-channel MOS transistor form a complementary metal oxide semiconductor structure, the first resistance is a p-channel MOS resistance formed at the same time as the p-channel MOS transistor forming the inverter, and the second resistance is the inverter. Is an n-channel MOS resistor formed at the same time as the n-channel MOS transistor forming
A value obtained by dividing the channel width of the p-channel MOS resistor forming the first resistance by the channel length and n forming the second resistance.
The ratio of the channel width of the channel MOS resistance divided by the channel length is calculated by dividing the channel width of the p-channel MOS transistor forming the inverter by the channel length and the channel width of the n-channel MOS transistor forming the inverter. It is characterized in that it is equal to the ratio divided by the channel length.

[0016]

In the AC signal level shifter according to the present invention, the operating point is determined by the resistance division between the power supplies, and there is no path through which the output returns to the input. Therefore, self-sustained pulsation can be prevented.

According to the present invention, the inverter is formed of a complementary metal oxide semiconductor (hereinafter, referred to as CMOS) including a p-channel MOS transistor and an n-channel MOS transistor, and resistors for dividing the power supplies are formed by these resistors. M
Since the MOS transistor is formed at the same time as the OS transistor, the operating point always coincides with the middle point of the inversion operation region of the inverter regardless of the manufacturing process variation, and therefore the amplification factor of the inverter is set to the minimum necessary margin. Thus, a low power consumption AC signal level shifter can be realized.

[0018]

[Embodiment 1] Hereinafter, Embodiment 1 of the present invention will be described with reference to the drawings.
Will be described in detail. First Embodiment FIG. 1 is a circuit diagram showing the configuration of an AC signal level shifter according to a first embodiment of the present invention.

In FIG. 1, the first resistor 5 and the second resistor 7 are connected to the intersection of the DC cut capacitor 1 for removing the DC component and the input of the inverter 3, and the other of the first resistor 5 is connected. The terminal is connected to the high potential side of the high voltage side power supply, and the other terminal of the second resistor 7 is connected to the low potential side of the high voltage side power supply.

In FIG. 1, the operating point of the inverter 3 as an amplifier is determined by dividing the power supply voltage by the first resistor 5 and the second resistor 7, and the output of the inverter 3 is the inverter 3. There is no route to return to the input of.

Therefore, the AC signal level shifter shown in FIG. 1 does not cause self-excited oscillation.

In order to maximize the efficiency of the amplifier, it is necessary to set the operating point at the midpoint of the inverting operation region of the inverter 3. Therefore, the first resistor 5 and the second resistor 5
It is necessary to choose the size ratio of the resistor 7 and the resistor 7.

Further, in order for the AC signal to be inverted by the inverter 3, it must be input with a sufficiently large amplitude to the input, so that the first resistor 5 and the second resistor 5 are compared with the impedance of the DC cut capacitor 1. It goes without saying that the size of the resistor 7 is sufficiently increased.

[0024]

Second Embodiment A second embodiment of the present invention will be described below with reference to the drawings.
Will be described in detail. Second Embodiment FIG. 2 is a circuit diagram showing the configuration of an AC signal level shifter according to a second embodiment of the present invention. The basic circuit configuration is equivalent to that of FIG.

As shown in FIG. 2, C is formed between the p-channel MOS transistor 9 and the n-channel MOS transistor 11.
A p-channel MOS resistor 13 that forms the MOS inverter 3 and is formed simultaneously with the p-channel MOS transistor 9
To form a first resistor, and an n-channel MOS resistor 15 formed simultaneously with the n-channel MOS transistor 11 forms a second resistor.
Constitutes the resistance of.

Then, the ratio of the value obtained by dividing the channel width of the p-channel MOS resistor 13 by the channel length and the value obtained by dividing the channel width of the n-channel MOS resistor 15 by the channel length is
A value obtained by dividing the channel width of the p-channel MOS transistor 9 by the channel length, and the n-channel MOS transistor 11
The ratio of the channel width to the value obtained by dividing the channel width by the channel length.

The value obtained by dividing the channel width by the channel length, p
The ratio of the channel to the n-channel is called the pn ratio. The pn ratio of the p-channel MOS transistor 9 and the n-channel MOS transistor 11 determines the middle point of the inversion operation region of the inverter 3, and the p-channel MOS resistor 13 and the n-channel MOS resistor 13 are connected to each other. The pn ratio of the channel MOS resistor 15 determines the operating point of the amplifier.

In the present invention, the MOS transistor and the MOS resistor are formed at the same time, and their pn ratios are made equal, so that the operating point is always the middle point of the inversion operating region of the inverter 3 regardless of manufacturing variations. Therefore, the margin of the amplification factor of the inverter requires only the minimum margin.

As described with reference to FIG. 1, it is needless to say that the sizes of the p-channel MOS resistor 13 and the n-channel MOS resistor 15 need to be set sufficiently larger than the impedance of the DC cut capacitor 1. Absent.

Although the present invention has been described in detail with reference to the embodiments shown in FIGS. 1 and 2, the present invention is not limited to the embodiments shown in FIGS. 1 and 2, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is possible to change.

For example, in FIG. 1, the first resistor 5 and the second resistor 7 are fixed resistors, but either one is a variable resistor, and an operating point as an amplifier depends on the finished state of the inverter 3. A mechanism for adjusting the inverter 3 so as to coincide with the midpoint of the reversal operation region may be provided.

For example, although the CMOS configuration is used in FIG. 2, if the ratio of the electrical characteristics of the high potential side and the low potential side of the inverter and the MOS resistance is made equal, only the p channel MOS or the n channel MOS is used.
It does not matter even if it is composed only.

Whatever the change, if the operating point is determined by dividing the resistance of the power supply,
If the purpose of eliminating self-excited oscillation can be achieved, and if the inverter and the resistance are the same device and the ratio of the electrical characteristics on the high potential side and the low potential side are equal, the inverter The purpose of providing an AC signal level shifter with low power consumption is achieved by constructing the amplification factor with a necessary minimum margin.

[0034]

As described above, by determining the operating point by dividing the power supply by resistance division, it is possible to provide a level shifter for alternating current signals without self-excited oscillation. By using the same device as the device to be configured, the operating point always matches the midpoint of the inverter's reversal operation area, regardless of manufacturing process variations, so the inverter amplification factor is set to the minimum necessary margin. As a result, it is possible to provide a low power consumption AC signal level shifter.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an AC signal level shifter according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an AC signal level shifter according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of an AC signal level shifter in a conventional example.

[Explanation of symbols]

 1 DC Cut Capacitor 3 Inverter 5 First Resistor 7 Second Resistor 9 p-Channel MOS Transistor 11 n-Channel MOS Transistor 13 p-Channel MOS Resistor 15 n-Channel MOS Resistor 17 Feedback Resistor

Claims (2)

[Claims]
1. A level shifter for converting a low-voltage AC signal into an AC signal of a voltage higher than the voltage, and a DC cut capacitor for removing a DC component from the low-voltage AC signal and an input to the DC cut capacitor. A first resistor that connects one terminal to a connection point between an inverter to be connected, a DC cut capacitor and an input of the inverter, and a second resistor that connects one terminal to a connection point between a DC cut capacitor and an input of the inverter. A resistor, and the other terminal of the first resistor is connected to the high potential side of the high voltage side power source, and the other terminal of the second resistor is connected to the low potential side of the high voltage side power source. A level shifter for AC signals, which is characterized in that
2. The inverter comprises a structure of a complementary metal oxide film semiconductor composed of a p-channel MOS transistor and an n-channel MOS transistor, and the first resistor is formed at the same time as a p-channel MOS transistor forming the inverter. The second resistance is an n-channel MOS resistance formed at the same time as the n-channel MOS transistor forming the inverter, and the channel width of the p-channel MOS resistance forming the first resistance is divided by the channel length. The ratio of the value and the value obtained by dividing the channel width of the n-channel MOS resistor forming the second resistor by the channel length is the value obtained by dividing the channel width of the p-channel MOS transistor forming the inverter by the channel length, and the inverter Divide the channel width of the n-channel MOS transistor that constitutes A level shifter for an AC signal, which is equal to a ratio with a value.
JP5313452A 1993-12-14 1993-12-14 Level shifter for ac signal Pending JPH07170167A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5313452A JPH07170167A (en) 1993-12-14 1993-12-14 Level shifter for ac signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5313452A JPH07170167A (en) 1993-12-14 1993-12-14 Level shifter for ac signal

Publications (1)

Publication Number Publication Date
JPH07170167A true JPH07170167A (en) 1995-07-04

Family

ID=18041477

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5313452A Pending JPH07170167A (en) 1993-12-14 1993-12-14 Level shifter for ac signal

Country Status (1)

Country Link
JP (1) JPH07170167A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100724559B1 (en) * 2004-12-15 2007-06-04 삼성전자주식회사 Level shifter
US7362796B2 (en) 2003-02-19 2008-04-22 Nec Corporation Signal relay circuit for securing amplitude of voltage of transmitting signals
JP2008312214A (en) * 2007-06-18 2008-12-25 Internatl Business Mach Corp <Ibm> System and method for level shifting using ac coupling

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7362796B2 (en) 2003-02-19 2008-04-22 Nec Corporation Signal relay circuit for securing amplitude of voltage of transmitting signals
KR100724559B1 (en) * 2004-12-15 2007-06-04 삼성전자주식회사 Level shifter
JP2008312214A (en) * 2007-06-18 2008-12-25 Internatl Business Mach Corp <Ibm> System and method for level shifting using ac coupling

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