JP3197601B2 - Oscillation circuits for semiconductor integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit for a semiconductor integrated circuit. In recent years, LSI has been used in various industries,
Its uses are diverse. When an LSI is used for an oscillation circuit, the oscillation frequency is not limited to one even for the same LSI, and is used at various frequencies. Therefore, it is necessary to change and use the amplification degree of the amplification inverter in the oscillation circuit according to the frequency.

[0002]

2. Description of the Related Art FIG. 9 shows a configuration of an oscillation circuit. In FIG. 9A, inside the IC, an amplifying inverter 10 and a self-biasing resistor 12 are connected in parallel and connected to terminals 14 and 16 of the IC. I
Outside of C, the crystal oscillator 18 is connected to the terminals 14 and 16 and grounded via capacitors 20 and 22. Inside the IC, an inverter 24 is connected to the terminal 16, and the inverter 24 outputs an oscillation signal 26 having a predetermined frequency.

[0003]

In the oscillation circuit shown in FIG. 9A, the size of the inverter 10 is fixed regardless of the frequency used.

First, consider the case where the frequency is high. In this case, the absolute value of the negative resistance becomes small as shown in the negative resistance characteristic of the oscillation circuit in FIG. Oscillation becomes difficult. In order to prevent this, when the frequency is high, it is necessary to increase the size of the inverter 10.

On the other hand, when the frequency is low, in this case, the oscillation circuit easily oscillates, but a large through current flows from the power supply side to the ground side through the inverter 10. More specifically, FIG. 9B shows the configuration of the inverter 10. When the frequency is low, the through current 32 flowing from the power supply V _CC to the ground through the P-type transistor 28 and the N-type transistor 30 is shown. Becomes larger. in this way,
If the through current 32 flowing into the ground side is large, there is a problem that the ground level rises and changes the threshold value of the MOS transistor inside the IC. To prevent this, it is necessary to reduce the size of the inverter 10 when the frequency is low.

As described above, the inverter 10 of the oscillation circuit
Is fixed, there is a problem when the frequency is high and when the frequency is low. It is necessary to change the size of the inverter 10 according to the frequency to be used.

In order to address the above problems, Japanese Patent Application Laid-Open
In the semiconductor integrated circuit for an oscillation circuit disclosed in Japanese Patent Application No. -82108, a plurality of inverters having different mutual conductances are provided in an IC, and one of the plurality of inverters is selectively used according to a frequency to be used. .
In other words, when the frequency is high, an inverter having a large transconductance is selectively used, while when the frequency is low, an inverter having a small transconductance is selectively used, whereby stable oscillation is achieved over a wide range of frequencies. You can get it.

However, in the configuration of the above publication, a plurality of inverters having different mutual conductances are provided beforehand in the IC, so that there is a problem that the chip size of the IC becomes large. Therefore, it is necessary to reduce the chip size of the IC and achieve low power consumption.

Therefore, an object of the present invention is to make the size of the amplifying inverter variable so that the area of the oscillation circuit in the semiconductor integrated circuit can be reduced and stable oscillation can be obtained without consuming extra power. It is another object of the present invention to provide an oscillation circuit for a semiconductor integrated circuit that can perform the above.

[0010]

[MEANS FOR SOLVING THE PROBLEMS] FIG.
Show the logic. FIG. 1A is a circuit diagram of an oscillation circuit for a semiconductor integrated circuit.
FIG. 1B is a circuit diagram for amplification in the oscillation circuit.
FIG. 4 is a circuit diagram of the inverter of FIG. In the semiconductor integrated circuit oscillator this comprising amplifying inverter (40), increasing <br/> width inverter (40) comprises a plurality of transistor set (5
8, 60, 62), and one or two or more of the plurality of transistor sets (58, 60, 62) are selectively connected in parallel according to the oscillation frequency to be used, thereby reducing the transistor size. It has a variable configuration.

Referring to FIG . 1A , inside an IC, an amplifying inverter 40 and a self-biasing resistor 42 are connected in parallel and connected to terminals 44 and 46 of the IC. Outside the IC, the crystal oscillator 48 is connected to the terminals 44,
46 and grounded via capacitors 50 and 52. Inside the IC, the terminal 46
An inverter 54 is connected, and the inverter 54 outputs an oscillation signal 56 having a predetermined frequency.

Further, in FIG. 1 (B), the inverter 4
0 includes three transistor sets 58, 60, 62;
The first transistor set 58 includes a P-type transistor 58.
a, an N-type transistor 58b;
The gates of 8a and 58b are both connected to the input signal IN. The second transistor set 60 includes a P-type transistor 60a and an N-type transistor 60b. The gate of the transistor 60a is switchably connected to the input signal IN or the power supply VCC via the switch 60c, and the gate of the transistor 60b is connected to the switch 60d. To the input signal IN or the ground side. Similarly,
The third transistor set 62 includes a P-type transistor 62
a, an N-type transistor 62b;
The gate of the transistor 62b is connected to the input signal IN or the power supply VCC via the switch 62c.
Are switched to the input signal IN or the ground side via the switch 62d. Having such a configuration
This allows the oscillation circuit to operate in the second transistor set 60
Switches 60c and 60d and a third transistor
By switching the switches 62c and 62d of the set 62,
Changing the size of the data 40 (transistor size)
Can be. That is, the transistor of the second transistor set 60
The gates of the transistors 60a and 60b are connected to the power supply VC, respectively.
C, connected to the ground side, and
The gates of the transistors 62a and 62b of the data set 62
If they are connected to the power supply VCC and the ground side,
Only one transistor set 58 is in a selected state, and the second
The transistor set 60 and the third transistor set 62 are non-
It is in the selected state. Therefore, the size of the inverter 40 is
It is determined by the first transistor set 58. Also,
The transistors 60a and 60b of the second transistor set 60
Are connected to the input signal IN,
The transistors 62a and 62b of the third transistor set 62
Are connected to the power supply VCC and the ground side, respectively.
The first transistor set 58 and the second transistor set.
Transistor set 60 is in the selected state, and the third transistor
The set 62 is in a non-selected state. Therefore, the inverter 40
The size depends on the first transistor set 58 and the second transistor set.
It is determined by the register set 60 . In addition, the second transition
The gates of the transistors 60a and 60b of the star set 60
Is also connected to the input signal IN, and similarly, the third
Gates of transistors 62a and 62b of transistor set 62
Are connected to the input signal IN, the first
Transistor set 58, second transistor set 60, and so on.
And all of the third transistor sets 62 are in the selected state.
You. Therefore, the size of the inverter 40 is
It is determined by the transistor sets 58, 60, 62. This
As a result, the switches 60c,
60d and the switch 6 of the third transistor set 62
The size of the inverter 40 is changed by switching between 2c and 62d.
Can be changed, depending on the oscillation frequency used
You can select the optimal inverter size
You. Also, when installing multiple inverters of different types
The area of the oscillation circuit in the semiconductor integrated circuit is smaller than
And no extra power is consumed.
You can get a shake. For semiconductor integrated circuits as described above
In the oscillation circuit, the invention according to claim 1 is a PMOS transistor.
CMO including transistor and NMOS transistor
Multiple S inverters are connected in parallel to the input signal line.
Semiconductor integrated circuit with amplifying inverter
A plurality of CMOS inverters for a road oscillation circuit;
Select each of the parameters according to the oscillation frequency used.
By setting to either selected or unselected state.
To reduce the transistor size of the amplification inverter.
Method of manufacturing oscillator circuit for semiconductor integrated circuit manufactured by replacement
The CMOS device in the selected state.
The PMOS transistor in an inverter and the
Connect the gate of the NMOS transistor to the input signal line
And the CMOS set to the non-selected state.
The PMOS transistor and the inverter in the inverter
Connect each gate of the NMOS transistor to the power line and
And connecting to a ground line . Further, the invention according to claim 2 provides a PMOS transistor.
CMOS including inverter and NMOS transistor
Data connected in parallel to the input signal line
Amplifying inverter connected to the input signal line
Rutotomoni, put on the multi several respective CMOS inverters
The PMOS transistor and the NMOS transistor
Connected to the gate of the
Each of the PMOS transistor and the NMOS transistor.
A control circuit for controlling on / off of the transistor,
Oscillation using the plurality of respective CMOS transistors
Either selected or unselected state corresponding to the frequency
Setting the transformer of the amplification inverter.
A semiconductor integrated circuit with variable register size,
The control circuit enters the selected state based on the control signal.
The PMOS transistor in the set CMOS inverter
A transistor and each of the NMOS transistors
Connected to the input signal line, and
In the CMOS transistor set to the selected state.
PMOS transistor and NMOS transistor
Connect each gate of the power supply to the power line and the ground line
It is characterized by the following. The invention according to claim 3 is a contractor.
3. The oscillation circuit for a semiconductor integrated circuit according to claim 2, wherein
A crystal oscillator is connected to the CMOS inverter.
And features.

[0013]

According to the first aspect of the present invention, the apparatus is set in the selected state.
PMOS transistor in fixed CMOS inverter
Input and output signal lines
CMOS connected to a non-selected state
PMOS transistor and NMO in inverter
Connect each gate of S transistor to power supply line and ground
Manufactures oscillator circuits for semiconductor integrated circuits connected to wires. I
Therefore, the manufactured oscillator circuit for a semiconductor integrated circuit is
NM in CMOS inverter set to selected state
OS transistor and PMOS transistor
By connecting these gates to the power and ground lines,
The transistor can be reliably turned off.
Of the CMOS inverter set to the non-selected state
CMO set to the selected state without causing operation
A malfunction in the S inverter can be prevented.
According to the second aspect of the present invention, the control circuit outputs the control signal
CMOS inverter set to the selected state based on
Transistors and NMOS transistors
Connected to the input signal line
In a CMOS transistor set to a non-selected state,
Of PMOS and NMOS transistors
Each gate is connected to a power line and a ground line. I
Therefore, the CMOS inverter set to the non-selected state
Transistor and PMOS transistor
Connect the respective gates of the
To ensure that the transistor is turned off.
CMOS in the non-selected state
Set to selected state without causing barter malfunction
To prevent malfunctions in a CMOS inverter
Can be. According to the third aspect of the present invention, C
A crystal oscillator is connected to the MOS inverter. I
Therefore, the signal transmitted by the crystal unit is
It can be amplified by an S inverter.

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows an inverter of an oscillation circuit according to an embodiment of the present invention.

The inverter of FIG. 2 has the same configuration as that of the inverter of FIG. 1B, and switches 60c, 6c of the second transistor set 60 according to the oscillation frequency to be used.
0d and the switch 62 of the third transistor set 62
By switching between c and 62d, the size of the inverter can be changed. That is, when the frequency is low, the gates of the transistors 60a and 60b of the second transistor set 60 are connected to the power supply _Vcc and the ground side, respectively.
The gate of 62b is connected to the power supply V _CC and the ground side, respectively, and only the first transistor set 58 is in the selected state.
Therefore, the size of the inverter is determined by the first transistor set 58 and is the minimum size.

When the frequency is high, the gates of the transistors 60a and 60b of the second transistor set 60 are both connected to the input signal IN, and both the first transistor set 58 and the second transistor set 60 are connected. Becomes selected. Therefore, the size of the inverter is determined by the first transistor set 58 and the second transistor set 60 and becomes large.

When the frequency is higher, the gates of the transistors 60a and 60b of the second transistor set 60 are both connected to the input signal IN. Similarly, the gates of the transistors 62a and 62b of the third transistor set 62 are connected. Are connected to the input signal IN, and all of the three first transistor sets 58, the second transistor sets 60, and the third transistor sets 62 are in the selected state. Therefore, the size of the inverter is the first transistor set 5
8, the maximum size is determined by the second transistor set 60 and the third transistor set 62.

As described above, according to the inverter of FIG. 2, the size of the inverter can be changed in accordance with the oscillation frequency to be used by switching the switches 60c, 60d, 62c, and 62d. As the size of the inverter increases, the size of the inverter can be increased.

In the inverter shown in FIG. 2, three transistor sets 58, 60, and 62 are provided. However, the number of transistor sets in the inverter is not limited to three.
Or four or more.

In the inverter shown in FIG. 2, the switches 60c, 60d, 62c, and 62d may be constituted by a mask option using a wiring mask, may be stored as ROM data, or can be selected by an external terminal. Is also good. Hereinafter, a configuration for switching the transistor size of the inverter of the oscillation circuit will be described.

First, FIG. 3 shows a first configuration in which the transistor size of the inverter is switched by a mask option. In FIG. 3A, the inverter includes three transistor sets 64, 66, and 68. The first transistor set 64 includes a P-type transistor 64a and an N-type transistor 64b. The set 66 includes a P-type transistor 66a and an N-type transistor 66b, and the third transistor set 68 includes a P-type transistor 68a and an N-type transistor 68b.
The transistors 64a, 64b, 66a, 66b, 6
The gates of 8a and 68b are connected to the input signal IN, and the transistors 64a and 64b of the first transistor set 64
The coupling portion 64c of the second transistor set 66 and the coupling portion 66c of the transistors 66a and 66b of the second transistor set 66 are connected to the output OUT via the switch 70, and are connected to the transistors 68a and 68b of the third transistor set 68. The coupling unit 68c is directly connected to the output OUT.

When the switch 70 is off, only the third transistor set 68 is in the selected state.
The transistor size of the inverter is small. On the other hand, when the switch 70 is on, all three transistor sets 64, 66, and 68 are in the selected state, and the transistor size of the inverter is large, which is three times as large as when the switch 70 is off. Size.

The circuit shown in FIG. 3A is similar to the circuit shown in FIG.
Achieved with a line structure. In FIG. 3B, the input signal I
The N polysilicon layer 72 includes a transistor set 64,
Gate layers 74, 76, 78 for 66, 68
Are combined. Symbols 80 and 82 are P
Channel transistor region (diffusion layer), N-channel transistor
5 shows a transistor region (diffusion layer).
Power supply V _CCAluminum layer 84 for contact 84a,
84b, and the N-type region 82 has a ground side V
_SSAluminum layer 86 for contacts 86a, 86b
Are joined by Reference numeral 88 denotes an output side output OUT.
The output side aluminum layer 88 is a core layer.
While being coupled to the P-type region 80 at the contact 88a,
The contact 88b is coupled to the N-type region 82. What
Reference numeral 90 indicates an N-well boundary.

In the above configuration, along the gate layer 74, the transistors 64a, 64a of the first transistor set 64
64b, and similarly, along the gate layer 76, the transistors 66a, 66a of the second transistor set 66 are formed.
66b are formed, and the transistors 68a, 68b of the third transistor set 68 are formed along the gate layer 78.

When the contacts 88c and 88d of the output-side aluminum layer 88 are not coupled to the P-type region 80 and the N-type region 82, respectively, only the third transistor set 68 is in the selected state, and The transistor size is small. This is the switch 7 in FIG.
0 corresponds to the off state. On the other hand, the contacts 88c and 88d of the aluminum layer 88 on the output side
When coupled to the mold region 80 and the N-type region 82,
All three transistor sets 64, 66, and 68 are in the selected state, and the transistor size of the inverter is large.
The size is three times that of the case where the contacts 88c and 88d are not joined. This corresponds to the case where the switch 70 is on in FIG.

As described above, in the structure of FIG. 3, the contacts 88c and 88d of the aluminum layer 88 on the output side are formed.
Can be changed depending on whether or not is coupled to the P-type region 80 and the N-type region 82, that is, by the mask option.

Next, FIGS. 4 and 5 show a second configuration in which the transistor size of the inverter is switched by a mask option. FIGS. 4 and 5 show the case where the transistor size is large and the case where the transistor size is small, respectively. Show. In addition, FIG.
Since the circuit in FIG. 5A is the same as the circuit in FIG. 2 described above, in FIG. 4A and FIG. 5B, the same parts as those in FIG. Is omitted.

First, in FIG. 4A, the switch 60c,
Since all of 60d, 62c, and 62d are switched to the input signal IN side, three transistor sets 58, 60,
All of 62 are in the selected state. Therefore, the transistor size of the inverter is three transistor sets 58, 6
0, 62, and the transistor size is large.

The circuit shown in FIG. 4A is achieved by the wiring structure shown in FIG. In FIG. 4B, the input signal I
In the N polysilicon layer 92, the transistor set 58,
Polysilicon gate layers 94, 96, 98 for 60, 62
Are arranged in an orthogonal state, and the gate layers 94, 96, 98
Are coupled to the polysilicon layer 92 at contacts 94a, 96a, 98a, respectively. Symbols 100 and 10
2, respectively, regions for P-channel transistor (diffusion layer), shows the N-channel transistor region (diffusion layer), the P-type region 100, the aluminum layer 104 of the power supply V _CC is coupled with the contact 104a, 104b , the N-type region 102, the aluminum layer 106 is coupled with the contact 106a, 106b of the ground-side V _SS. Reference numeral 108 denotes an aluminum layer for the output OUT, and the aluminum layer 108
a, 108b are coupled to the P-type region 100,
The contacts 108c and 108d are connected to the N-type region 102. Note that reference numeral 110 indicates an N-well boundary.

In the above configuration, the transistors 58a, 58a of the first transistor set 58 are arranged along the gate layer 94.
58b are formed, and the transistors 60a, 60a of the second transistor set 60 are similarly formed along the gate layer 96.
60b are formed, and the transistors 62a and 62b of the third transistor set 62 are formed along the gate layer 98.

Then, the second transistor set 60, the third
Are connected to the polysilicon layer 92 for the input signal IN through the contacts 96a and 98a, respectively, so that the three transistor sets 58, 60 and 62 are all in the selected state. . Therefore, the transistor size of the inverter is determined by the three transistor sets 58, 60, and 62, and the transistor size is large.

Next, in FIG. 5A, the switch 60c,
62c is switched to the power supply V _CC side and the switch 6
0d and 62d are switched to the ground side,
Are in the selected state. Therefore,
The transistor size of the inverter is determined by the first transistor set 58, and the transistor size is small.

The circuit shown in FIG. 5A is achieved by the wiring structure shown in FIG. In FIG. 5B, the input signal I
A polysilicon gate layer 94 for the first transistor set 58 is arranged in the N polysilicon layer 92 in an orthogonal state, and the gate layer 94 is coupled to the polysilicon layer 92. The polysilicon gate layers 96-1 and 96-2 for the second transistor set 60 and the polysilicon gate layers 98-1 and 98 for the third transistor set 62 are provided.
-2 is arranged in parallel with the polysilicon gate layer 94. Reference numeral 100 and 102, respectively, regions for P-channel (diffusion layer), shows the region for N-channel (diffusion layer), the P-type region 100, coupling aluminum layer 104 contacts 104a, at 104b for supply V _CC are, also, the N-type region 102, is Uruminiumu layer 106 for ground V _SS are coupled contact 106a, in 106b. Reference numeral 108 denotes an aluminum layer for the output OUT, and the aluminum layer 108
a, 108b are coupled to the P-type region 100,
The contacts 108c and 108d are connected to the N-type region 102. Further, the gate layers 96-1, 98-1
Are connected to the aluminum layer 104 by contacts 96-1a and 98-1a, and are connected to the gate layers 96-2 and 98-2.
Are coupled to the aluminum layer 106 by contacts 96-2a and 98-2a. In addition, the code 110 is N-
Indicates a well boundary.

In the above configuration, the transistors 58a, 58a of the first transistor set 58 are arranged along the gate layer 94.
58b are formed. Also, the gate layers 96-1, 96-
2, the transistors 60 a and 60 b of the second transistor set 60 are formed, and similarly, the gate layer 98 is formed.
The transistors 62a and 62b of the third transistor set 62 are formed along −1 and 98-2.

The gate layers 96-1 and 96-2 of the transistors 60a and 60b of the second transistor set 60
Are coupled to aluminum layers 104 and 106 via contacts 96-1a and 96-2a, respectively, and similarly, transistors 62 of third transistor set 62.
a, 62b are coupled to aluminum layers 104, 106 via contacts 98-1a, 98-2a, respectively. Therefore, the second transistor set 60 and the third transistor set 62 are in a non-selected state, and only the first transistor set 58 is in a selected state. Therefore, the transistor size of the inverter is determined by the first transistor set 58, and the transistor size is small.

A comparison between the wiring structure shown in FIG. 4B and the wiring structure shown in FIG. 5B shows that the masks for the polysilicon gate layer 92 and the gate layers 94, 96, 98, and the gate layers 96, 98 are provided. It is understood that the size of the transistor of the inverter can be changed by switching a total of two masks, that is, a mask for contact for the inverter.

Next, FIG. 6 shows a third configuration in which the transistor size of the inverter is switched by a mask option. The wiring structure of FIG. 6 corresponds to the circuit of FIG.

In FIG. 6, the polysilicon gate layer 11 for the first transistor set 58 is parallel to the portions 112a and 112b of the polysilicon layer 112 for the input signal IN.
4-1 and 114-2, the polysilicon gate layers 116-1 and 116-2 for the second transistor set 60, and the polysilicon gate layer 118- for the third transistor set 62.
1,118-2 are arranged. Reference numerals 120 and 122
Respectively, P-channel area (diffusion layer), shows the region for N-channel (diffusion layer), the P-type region 120, the aluminum layer 124 of the power supply V _CC is the contact 124a,
Are combined in 124b, The N-type region 122, an aluminum layer 126 for ground V _SS contact 126
a, 126b. Reference numeral 128 indicates an aluminum layer for the output OUT, and the aluminum layer 1
28 denotes P-type regions 12 at contacts 128a and 128b.
0 and contacts 128c, 128
It is coupled to the N-type region 122 at d. Note that reference numeral 13
0 indicates an N-well boundary.

In the above structure, the gate layer 114-
1, 114-2, the transistors 58a and 58b of the first transistor set 58 are formed.
The transistors 60a and 60b of the second transistor set 60 are formed along the gate layers 116-1 and 116-2, and the transistors 62a of the third transistor set 62 are formed along the gate layers 118-1 and 118-2. , 62b are formed.

Then, the gate layers 116-1 of the second transistor set 60 and the gate layer 118-1 of the third transistor set 62 are respectively connected to the contacts 116-1a and 116-1a.
8-1a, the gate layer 11 of the second transistor set 60 is coupled to the polysilicon layer 112 for the input signal IN.
Gate Layer 118 of 6-2 and Third Transistor Set 62
-2 to contacts 116-2a and 118-2a, respectively.
, The three transistor sets 58, 60, and 62 are all in the selected state. Therefore, the transistor size of the inverter is determined by the three transistor sets 58, 60, and 62, and the transistor size is large.

On the other hand, the gate layer 116-1 of the second transistor set 60 and the gate layer 118-1 of the third transistor set 62 are connected to the contacts 116-1b and 118-1, respectively.
-1b to the aluminum layer 124, and connects the gate layer 116-2 of the second transistor set 60 and the gate layer 118-2 of the third transistor set 62 to the aluminum layer by contacts 116-2b and 118-2b, respectively. 1
26, the second transistor set 60 and the third transistor set 62 are in a non-selected state, and
Are in the selected state. Therefore,
The size of the inverter is determined by the first transistor set 58, and the size of the transistor is small.

In the wiring structure shown in FIG. 6, the gate layers 116-1 and 116-2 of the second transistor set 60 and the third
Gate layers 118-1 and 118- of the transistor set 62 of FIG.
By changing the position of the second contact,
Gate layers 116-1, 116-2, 118-1, 118
By switching the mask for the contact for -2 (by switching one mask for the contact), the transistor size of the inverter can be changed.

Next, FIG. 7 shows a configuration in which the transistor size of the inverter is switched by ROM data. FIG. 7A shows a circuit diagram of the inverter, and the inverter includes a first transistor set 132 and a second transistor set 134. First transistor set 13
2 includes a P-type transistor 132a and an N-type transistor 132b, and similarly, a second transistor set 1
34 includes a P-type transistor 134a and an N-type transistor 134b. The coupling 132c of the transistors 132a and 132b of the first transistor set 132 and the second
Transistors 134a and 13 of the transistor set 134
4b is coupled to the output side OUT.

Reference numeral 136 denotes the first transistor set 13
4 shows a control circuit for the four N-type transistors 138a, 138b, 140a, 1
40b and two inverters 142 and 144. The symbol IN denotes the first transistor set 132,
An input signal to the second transistor set 134 is shown, and a symbol CONT indicates a control signal to the control circuit 136.

In the above configuration, when control signal CONT is at "H" level, transistors 138a, 138
0a is off and the transistors 138b, 140
Since b is in the ON state, the input signal IN is supplied to the gates of the transistors 132a and 132b of the first transistor set 132 via the transistors 138b and 140b. Therefore, in this case, the first transistor set 132 is in the selected state.

On the other hand, when the control signal CONT is at the "L" level, the transistors 138a and 140a are on and the transistors 138b and 140b are off, so that the power supply V _CC is supplied via the transistor 138a. Transistor 132 of first transistor set 132
a, and the ground side is supplied to the gate of the transistor 132b of the first transistor 132 via the transistor 140a. Therefore, in this case, the first transistor set 132 is in a non-selected state.

As described above, by switching the level of the control signal CONT to the control circuit 136, the first transistor set 132 can be switched between the selected state and the non-selected state.

The second transistor set 134 is also connected to a second control circuit (not shown) similar to the control circuit 136, and the second control circuit
Can be switched between a selected state and a non-selected state.

Therefore, according to the inverter shown in FIG. 7A, the first transistor set 132 and the second transistor set 134 are controlled by the control circuit 136 and the second control circuit.
Can be switched to a selected state or a non-selected state to change the transistor size of the inverter. That is, when only one of the transistor sets 132 and 134 is in the selected state, the transistor size of the inverter is small.
When both of them are in the selected state, the transistor size of the inverter is large.

The control signal CONT to the control circuit 136
May be output as ROM data, or
It may be supplied from an external terminal of C. And FIG. 7 (B)
Shows an example of ROM data. In FIG. 7B, one of the transistors 146 and 148 is an enhancement-type or depletion-type transistor.
The control signal CONT from the 6,168 coupling unit 150 is
This is the “H” level or the “L” level.

In the embodiment described above, the present invention is applied to the inverter in the oscillation circuit. However, the present invention is also applicable to an oscillation circuit including a NAND circuit or a NOR circuit instead of the inverter. That is, FIG. 8 shows a semiconductor device according to another embodiment of the present invention, and FIG.
Shows a NAND circuit, and FIG. 8B shows a NOR circuit. Note that when a NAND circuit or a NOR circuit is used, there is an advantage that power consumption can be reduced.

First, in FIG. 8A, the NAND circuit includes a first transistor set 152, 152 ', a second transistor set 154, 154', and a third transistor set 156, 156 '. Symbols A1 and A2 indicate input signals, and symbol B indicates an output signal. The first transistor set 152 includes a P-type transistor 152a and N-type transistors 152b and 152c, and the first transistor set 152 'includes a P-type transistor 152'a. The second transistor set 154 includes a P-type transistor 154a, N-type transistors 154b and 154c.
And the second transistor set 154 'includes P-type transistors 154'a.
The inputs of the gates of 4b, 154c, 154'a are respectively switched by switches 158a, 158b, 158c, 158'a. Similarly, the third transistor set 156 includes a P-type transistor 156a and N-type transistors 156b and 156c, and the third transistor set 156 'includes a P-type transistor set 156'a, and 156a, 156b, Fifteen
The gates of 6c and 156'a are connected to the switch 16 respectively.
The input is switched by 0a, 160b, 160c, 160'a.

In the above configuration, the switches 158a,
158b, 158c, 158'a and switch 160
By switching among a, 160b, 160c and 160'a, the transistor size of the NAND circuit can be changed.

That is, the second transistor set 154,
When both 154 'and the third transistor set 156, 156' are in the non-selected state, only the first transistor set 152, 152 'is in the selected state, and the transistor size of the NAND circuit is the first. Transistor set 15
2, 152 ', and the transistor size is small. Further, only one of the second transistor set 154, 154 'or the third transistor set 156, 156', for example, the second transistor set 154, 154 '
4 'is in the selected state, the first transistor set 152, 152' and the second transistor set 154, 1
54 'is in the selected state, and the transistor size of the NAND circuit is determined by the first transistor set 152, 152' and the second transistor set 154, 154 '.
The transistor size is large. Further, the second transistor set 154, 154 'and the third transistor set 15
6 and 156 'are in the selected state, the three transistor sets 152, 152'; 154, 154 ';
156, 156 'are all in the selected state, and the transistor size of the NAND circuit is the three transistor sets 152, 152'; 154, 154 '; 156, 15
6 ', the transistor size is maximum.

Next, in FIG. 8B, the NOR circuit includes a first transistor set 162, 162 ', a second transistor set 164, 164', and a third transistor set 166, 166 '. , A1 and A2 indicate input signals, and B indicates an output signal. The first transistor set 162 includes P-type transistors 162a and 162
b, an N-type transistor 162c, and the first transistor set 162 'includes an N-type transistor 162'a. The second transistor set 164 includes P-type transistors 164a and 164b and an N-type transistor 164c.
And the second transistor set 164 'includes an N-type transistor 164'a, and the transistors 164a, 1
The gates of 64b, 164c and 164'a are respectively
The input is switched by switches 168a, 168b, 168c, 168'a. Similarly, the third transistor set 166 includes P-type transistors 166a and 166b and an N-type transistor 166c.
And the third transistor set 166 ′ includes an N-type transistor 166′a, and the transistors 166a, 1
The gates of 66b, 166c and 166'a are respectively
The inputs are switched by switches 170a, 170b, 170c, 170'a.

In the above configuration, the switches 168a,
168b, 168c, 168'a and switch 170
By switching between a, 170b, 170c and 170'a, the transistor size of the NOR circuit can be changed.

That is, the second transistor set 164,
When both the transistor set 164 'and the third transistor set 166, 168' are in the non-selected state, only the first transistor set 162, 162 'is in the selected state, and the transistor size of the NOR circuit is the first. Transistor set 16
2,162 ', and the transistor size is small. Further, only one of the second transistor set 164, 164 'or the third transistor set 166, 166', for example, the second transistor set 164, 164 '
4 'is in the selected state, the first transistor set 162, 162' and the second transistor set 164, 1
64 'is in the selected state, and the transistor size of the NOR circuit is determined by the first transistor set 162, 162' and the second transistor set 164, 164 ', and the transistor size is large. Furthermore, a second transistor set 164, 164 'and a third transistor set 166,
When both of 166 'are selected, three transistor sets 162, 162'; 164, 164 ';
6, 166 'are all in the selected state, and the transistor size of the NOR circuit is
2, 162 '; 164, 164'; 166, 166 ', and the transistor size is the largest.

[0063]

As described above, according to the first aspect,
According to the invention, the transistor size of the amplification inverter
When setting CMOS, the CMOS
NMOS and PMOS transistors in the converter
Connect each gate of transistor to power supply line and ground line
This ensures that the transistor is turned off.
Of oscillator circuits for semiconductor integrated circuits that can be controlled
Can be set, so that the CMOS
It can be set to the selected state without causing the converter to malfunction.
To prevent malfunction in specified CMOS inverter
Manufacturing oscillator circuits for semiconductor integrated circuits
Can be.

According to the second aspect of the present invention, the number of
When setting the transistor size of the width inverter,
N in a CMOS inverter set to a non-selected state
MOS transistor and PMOS transistor
Connect each gate to the power and ground lines
The transistor can be reliably turned off.
Therefore, the error of the CMOS inverter set to the non-selected state
CM set to the selected state without causing any action
Malfunction in OS inverter can be prevented
You.

According to the third aspect of the present invention, water
Inverts the signal transmitted by the crystal oscillator to a CMOS inverter
Can be amplified.

[Brief description of the drawings]

FIGS. 1A and 1B show an oscillation circuit according to the principle of the present invention, wherein FIG. 1A shows an overall configuration and FIG.

FIG. 2 shows an inverter of an oscillation circuit according to an embodiment of the present invention.

3A and 3B show a first configuration in which a transistor size of an inverter is switched by a mask option, FIG. 3A shows a circuit diagram, and FIG. 3B shows a wiring structure.

4A and 4B show a second configuration (when the transistor size is large) in which the transistor size of the inverter is switched by a mask option, FIG. 4A shows a circuit diagram, and FIG. 4B shows a wiring structure.

5A and 5B show a second configuration (when the transistor size is small) in which the transistor size of the inverter is switched by a mask option. FIG. 5A shows a circuit diagram, and FIG. 5B shows a wiring structure.

FIG. 6 shows a third configuration in which the transistor size of the inverter is switched by a mask option.

7A and 7B show a configuration in which the transistor size of the inverter is switched by ROM data, and FIG. 7A shows a circuit diagram;
(B) shows an example of ROM data.

FIG. 8 shows a semiconductor device according to another embodiment of the present invention;
(A) shows a NAND circuit, and (B) shows a NOR circuit.

9A and 9B illustrate a configuration of an oscillation circuit, FIG. 9A illustrates an entire configuration, and FIG. 9B illustrates a configuration of an inverter.

FIG. 10 shows a negative resistance characteristic of the oscillation circuit.

[Explanation of symbols]

 40 ... inverter 58 ... first transistor set 60 ... second transistor set 62 ... third transistor set

Claims (3)

(57) [Claims] 1. A PMOS transistor and an NMOS transistor.
A CMOS inverter including a transistor is connected to the input signal line.
For amplification
Each of the plurality of CMOS inverters is used for an oscillation circuit for a semiconductor integrated circuit having a
Either selected or unselected according to the oscillation frequency
By setting to one state, the amplification inversion
The semiconductor manufactured by switching the transistor size of the
A method of manufacturing a transmission circuit for a body integrated circuit, comprising:
The PMOS transistor and the NMOS transistor
A step of connecting the gate of Njisuta to said input signal line, the CMOS inverter in which the set in the unselected state
The PMOS transistor and the NMOS transistor
Connect each gate of transistor to power supply line and ground line
Connecting the semiconductor integrated circuit to the oscillator circuit.
Construction method. 2. A PMOS transistor and an NMOS transistor.
CMOS inverter including transistor for input signal line
Amplifying inverter configured by connecting multiple units in parallel
Connected to the input signal line, and
The PMOS transistor in each CMOS inverter of FIG.
And the gate of the NMOS transistor.
And each of the PMOS transistors is controlled by an input control signal.
ON / OFF of the transistor and the NMOS transistor
A control circuit for controlling the plurality of CMOSs
Select the transistor according to the oscillation frequency used.
By setting to either one of
The transistor size of the amplification inverter is made variable.
Semiconductor integrated circuit, wherein the control circuit is in the selected state based on the control signal
The PMOS in the CMOS inverter set to
Transistor and said NMOS transistor
Connected to the input signal line,
In the CMOS transistor set to the selected state,
The PMOS transistor and the NMOS transistor
Connect the respective gates of the
A semiconductor integrated circuit characterized by: 3. The oscillation circuit for a semiconductor integrated circuit according to claim 2 , wherein a crystal oscillator is connected to said CMOS inverter .