JP2007158035A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that has a macro-cell for receiving power supply from annular wirings, and is capable of reducing power consumption. <P>SOLUTION: The semiconductor integrated circuit is provided with the macro-cell MC1 for achieving prescribed functions, the annular wiring L1 connected to the macro-cell MC1 while being arranged so as to surround the macro-cell MC1, the annular wiring L2 connected to power supply potential V<SB>DD</SB>while being arranged so as to surround the annular wiring L1, the annular wiring L3 connected to power supply potential V<SB>SS</SB>and the macro-cell MC1 while being arranged so as to surround the annular wiring L2, and CMOS inverters INV1, INV2 as a switch circuit for connecting between the two sets of annular wiring L1, L2 or between the two sets of annular wiring L1, L3 corresponding to a control signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having an annular wiring for supplying a power supply potential to a functional block.

Conventionally, in a semiconductor integrated circuit, in order to supply a power supply potential to a macro cell, which is a functional block for realizing a predetermined function, an annular power supply wiring is disposed so as to surround the macro cell. FIG. 5 is a diagram showing an example of such a conventional macro cell and annular power supply wiring. In this semiconductor integrated circuit, an annular power supply line L7 is disposed so as to surround the macro cell MC3, and an annular power supply line L8 is disposed so as to surround the annular power supply line L7. The annular power supply line L7 is connected to a power supply potential on the high potential side (here, V _DD ) and supplies the power supply potential V _DD to the macro cell MC3. The annular power supply line L8 is connected to the power supply potential on the low potential side (here, V _SS ) to supply the power supply potential V _SS to the macro cell MC3. In the semiconductor integrated circuit shown in FIG. 5, even when the macro cell MC3 is in a standby state (during non-operation), the power supply potentials V _DD and V _SS are supplied to the macro cell MC3 and the standby current is consumed. It was consumed.

By the way, a semiconductor integrated circuit capable of reducing the power consumption of an unselected circuit block is known (for example, see Patent Documents 1 and 2 below).
Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique for shutting off a power switch for a circuit block that is not selected.
In Patent Document 2, as the problems of the technique disclosed in Patent Document 1, (1) if the power switch is turned on / off unnecessarily, the current consumption increases, and (2) the speed of the integrated circuit decreases due to the power switch being turned on / off. It has been pointed out.

In order to solve the problems of the technique disclosed in Patent Document 1, Patent Document 2 corresponds to each of a power line, a plurality of circuit blocks including at least one first circuit block, and the at least one first circuit block. And at least one switch for controlling the supply of power from the power supply line to the first circuit block, and a processor for executing a task with at least one of the plurality of circuit blocks being used. In the execution of the task of the processor, the first circuit block receives a state signal instructing the transition to the non-use state, turns off the corresponding switch, and the first circuit block enters the use state. A semiconductor integrated circuit is described in which the switch is turned on prior to receiving a state signal instructing transition.
The technique disclosed in Patent Document 2 controls a switch of a circuit block according to the task execution status of a processor, and does not relate to a semiconductor integrated circuit in which a ring wiring is arranged so as to surround a macro cell.

JP-A-10-208473 JP 2004-21574 A

  Accordingly, in view of the above points, the present invention provides a semiconductor integrated circuit that has an annular wiring for supplying a power supply potential to a functional block and can reduce power consumption when the functional block is not operating. For the purpose.

  In order to solve the above problems, a semiconductor integrated circuit according to the present invention includes a functional block for realizing a predetermined function, a first annular wiring arranged so as to surround the functional block, and connected to the functional block. The second annular wiring arranged so as to surround the functional block and connected to the first power supply potential, and arranged so as to surround the functional block, connected to the second power supply potential and connected to the functional block And a third annular wiring and a switch circuit for connecting between the first annular power supply and the second annular power supply when a control signal supplied from the outside is activated.

  In this semiconductor integrated circuit, the second annular wiring is arranged so as to surround the first annular wiring, and the third annular wiring is arranged so as to surround the second annular wiring. Also good. Furthermore, the switch circuit may be arranged between the first annular wiring and the second annular wiring or between the second annular wiring and the third annular wiring.

  The first power supply potential may be a high-potential side power supply potential, the second power supply potential may be a low-potential side power supply potential, and the switch circuit may include at least one P-channel MOS transistor. .

  The switch circuit may connect the first annular power source and the third annular power source when the control signal is inactivated. Further, the switch circuit may include at least one CMOS inverter.

  The semiconductor integrated circuit may be a gate array type or an embedded array type ASIC. Furthermore, the switch circuit may be configured using at least one basic cell.

  According to the present invention, current consumption when the functional block is not operating can be cut off. Thereby, power consumption can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, about the same component, it has shown with the same reference number.
FIG. 1 is a diagram showing an outline of a part of the semiconductor integrated circuit according to the first embodiment of the present invention. In the present embodiment, the present invention is applied to a gate array type ASIC (application specific integrated circuit). As shown in FIG. 1, this semiconductor integrated circuit is arranged so as to surround a macro cell MC1, a macro cell MC1 for realizing a predetermined function, an annular wire L1 connected to the macro cell MC1, and an annular wire L1. An annular wiring L2 connected to a high-potential-side power supply potential (here, V _DD ) and a low-potential-side power supply potential (here, V _SS ) are arranged so as to surround the annular wiring L2. And the annular wiring L3 connected to the macro cell MC1 and the annular wiring L1 and the annular wiring L2 or the annular wiring L1 and the annular wiring L3 according to a control signal supplied from the outside. It has two CMOS inverters INV1 and INV2 as switch circuits.

  In general, annular wirings L1 to L3 are divided into a vertical pattern and a horizontal pattern in a plurality of metal wiring layers formed on a polysilicon layer via an interlayer insulating film.

  FIG. 2 is a diagram illustrating a circuit configuration of the inverters INV1 and INV2. As shown in FIG. 2, the inverter INV1 includes a P-channel MOS transistor QP1 and an N-channel MOS transistor QN1 whose source-drain paths are arranged in series between the annular wiring L2 and the annular wiring L3. The inverter INV2 includes a P-channel MOS transistor QP2 and an N-channel MOS transistor QN2 whose source-drain paths are arranged in series between the annular wiring L2 and the annular wiring L3.

An active-low control signal is supplied to the input terminal of the inverter INV1 (the gates of the transistors QP1 and QN1) and the input terminal of the inverter INV2 (the gates of the transistors QP2 and QN2).
The output terminal of the inverter INV1 (the drains of the transistors QP1 and QN1) and the output terminal of the inverter INV2 (the drains of the transistors QP2 and QN2) are connected to the annular wiring L1.

  FIG. 3 is a diagram showing a layout of the inverters INV1 and INV2. In general, in a gate array type ASIC, a plurality of basic cells are arranged in an array, and each basic cell has two P-channel MOS transistors and two N-channel MOS transistors. FIG. 3 shows a layout of one basic cell BC1 among a plurality of basic cells arranged in an array.

  As shown in FIG. 3, the basic cell BC1 includes impurity diffusion regions 11 and 12, and polysilicon gate electrodes P1 and P2 formed above the impurity diffusion regions 11 and 12 via a gate insulating film. Yes. Impurity diffusion regions 11 and 12 and gate electrodes P1 and P2 constitute transistors QP1, QP2, PN1, and QN2.

The source of the transistor QP1 is connected to the annular wiring L2 of the first metal layer via the wiring 21 of the second metal layer, and the source of the transistor QN1 is connected to the first metal layer 22 via the wiring 22 of the second metal layer. It is connected to the annular wiring L3 of the metal layer.
Similarly, the source of the transistor QP2 is connected to the annular wiring L2 via the wiring 23 of the second metal layer, and the source of the transistor QN1 is connected to the annular wiring L3 via the wiring 24 of the second metal layer. It is connected.

The gate electrodes P1 and P2 are connected to the wiring 31 of the second metal layer and the wiring 32 of the first metal layer. A control signal is supplied to the wiring 31.
The drains of the transistors QP1, QP2, QN1, and QN2 are connected to the annular wiring L1 via the second metal layer wiring 33, the first metal layer wiring 34, and the second metal layer wiring 35.

When the control signal is activated (here, at a low level), the transistors QP1 and QP2 are turned on, the transistors QN1 and QN2 are turned off, and the annular wiring L1 is connected to the power supply potential V _DD . As a result, power is supplied to the macro cell MC1, and the macro cell MC1 can realize a predetermined function.

On the other hand, when the control signal is inactivated (here, at a high level), the transistors QP1 and QP2 are turned off, the transistors QN1 and QN2 are turned on, and the annular wiring L1 is connected to the power supply potential _VSS . Is done. As a result, the supply of power to the macro cell MC1 is stopped, and the macro cell MC1 stops operating. At this time, the consumption current (standby current) of the macro cell MC1 is cut off.

As described above, according to the present embodiment, it is possible to reduce power consumption by cutting off current consumption when the macro cell MC1 is not operating.
In a conventional semiconductor integrated circuit (see FIG. 5), the basic cell arranged between the annular wiring L7 and the annular wiring L8 is often not used. In the present embodiment, the basic cell arranged between the annular wiring L2 and the annular wiring L3 is effectively used as a switch circuit. Therefore, the number of basic cells is not increased in order to perform power switching to the macro cell MC1.

  In the present embodiment, two inverters INV1 and INV2 are used to switch power to the macro cell MC1, but one inverter may be used, and three or more inverters may be used. It is good also as using. The number of inverters may be determined according to the peak power consumption of the macro cell MC1.

  Further, in the present embodiment, the inverters INV1 and INV2 are arranged between the annular wiring L2 and the annular wiring L3, but may be arranged between the annular wiring L1 and the annular wiring L2.

In the present embodiment, the power supply potential V _DD is connected to the second annular wiring (here, the annular wiring L2) from the inside, but may be connected to another annular wiring. Further, although the power supply potential _VSS is connected to the outermost annular wiring (here, the annular wiring L3), it may be connected to another annular wiring. Further, the macro cell MC1 is supplied with power from the innermost annular wiring (here, the annular wiring L1) and the outermost annular wiring (here, the annular wiring L3). You may make it receive supply.

  In the present embodiment, the present invention is applied to a gate array type ASIC. However, the present invention may be applied to an embedded array type ASIC. In this case, the macro cell MC1 may be a hard macro cell.

Next, a second embodiment of the present invention will be described.
FIG. 4 is a diagram showing an outline of a part of the semiconductor integrated circuit according to the second embodiment of the present invention. As shown in FIG. 4, this semiconductor integrated circuit surrounds a macro cell MC2 for realizing a predetermined function, an annular wiring L4 that is disposed so as to surround the macro cell MC2, and is connected to the macro cell MC2, and an annular wiring L4. An annular wiring L5 connected to a power supply potential on the high potential side (here, V _DD ) and a power supply potential on the low potential side (here, V _SS ) arranged so as to surround the annular wiring L5. And P-channel MOS transistors QP3 and QP4 as switch circuits for connecting the annular wiring L6 connected to the macro cell MC2 and the annular wiring L4 and the annular wiring L5 in accordance with a control signal supplied from the outside. And have.

  The source-drain paths of the transistors QP3 and QP4 are connected between the annular wiring L5 and the annular wiring L4, respectively. An active low control signal is supplied to the gates of the transistors QP3 and QP4.

When the control signal is activated (here, at a low level), the transistors QP3 and QP4 are turned on, and the annular wiring L4 is connected to the power supply potential V _DD . As a result, power is supplied to the macro cell MC2, and the macro cell MC2 can realize a predetermined function.

  On the other hand, when the control signal is inactivated (here, at a high level), the transistors QP3 and QP4 are turned off, and the annular wiring L4 is in a high impedance state. As a result, the supply of power to the macro cell MC2 is stopped, and the macro cell MC2 stops operating. At this time, the current consumption of the macro cell MC2 can be cut off.

  Thus, according to the present embodiment, the current consumption of the macro cell MC2 can be cut off with a smaller number of elements than in the first embodiment, as in the first embodiment. Thereby, power consumption can be reduced.

  In the present embodiment, two transistors QP3 and QP4 are used to supply power to the macro cell MC2. However, one transistor may be used, and three or more transistors may be used. It is good also as using. The number of transistors may be determined according to the peak value of power consumption of the macro cell MC2.

  Further, in the present embodiment, the transistors QP3 and QP4 are disposed between the annular wiring L4 and the annular wiring L5, respectively, but may be disposed between the annular wiring L5 and the annular wiring L6, respectively. .

In the present embodiment, the power supply potential V _DD is connected to the second annular wiring (here, the annular wiring L5) from the inside, but may be connected to another annular wiring. Further, the power supply voltage V _SS (here, the annular wiring L6) outermost annular wires are connected to, may be connected to another annular wire. The macro cell MC2 is supplied with power from the innermost annular wiring (here, the annular wiring L4) and the outermost annular wiring (here, the annular wiring L6). You may make it receive supply.

  The present embodiment may be applied to a gate array type or embedded array type ASIC. In this case, the transistors QP3 and QP4 may be realized by a basic cell.

  The present invention can be used for a semiconductor integrated circuit having an annular wiring for supplying a power supply potential to a functional block. Further, it can be used in a gate array type or embedded array type ASIC.

1 is a diagram showing an outline of a part of a semiconductor integrated circuit according to a first embodiment of the present invention. The figure which shows the circuit structure of inverter INV1, INV2 of FIG. The figure which shows the layout of inverter INV1, INV2 of FIG. FIG. 5 is a diagram showing an outline of a part of a semiconductor integrated circuit according to a second embodiment of the present invention. The figure which shows the one part outline | summary of the conventional semiconductor integrated circuit.

Explanation of symbols

  MC1, MC2, MC3 macro cell, L1-L8 ring wiring, INV1, INV2 inverter, QP1-QP4, QN1, QN2 transistor, BC1 basic cell, P1, P2 gate electrode, 11,12 impurity diffusion region, 21-24, 311- 35 Wiring

Claims (8)

Functional blocks for realizing a predetermined function;
A first annular wiring arranged to surround the functional block and connected to the functional block;
A second annular wiring arranged to surround the functional block and connected to a first power supply potential;
A third annular wiring disposed so as to surround the functional block, connected to a second power supply potential and connected to the functional block;
A switch circuit for connecting between the first annular power supply and the second annular power supply when an externally supplied control signal is activated;
A semiconductor integrated circuit comprising: The second annular wiring is disposed so as to surround the first annular wiring;
The semiconductor integrated circuit according to claim 1, wherein the third annular wiring is disposed so as to surround the second annular wiring.   3. The semiconductor according to claim 2, wherein the switch circuit is disposed between the first annular wiring and the second annular wiring or between the second annular wiring and the third annular wiring. Integrated circuit.   The first power supply potential is a power supply potential on a high potential side, the second power supply potential is a power supply potential on a low potential side, and the switch circuit includes at least one P-channel MOS transistor. Item 4. The semiconductor integrated circuit according to Item 3.   4. The switch circuit according to claim 1, wherein the switch circuit connects between the first annular power source and the third annular power source when the control signal is inactivated. 5. Semiconductor integrated circuit.   The semiconductor integrated circuit according to claim 5, wherein the switch circuit includes at least one CMOS inverter.   The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a gate array type or an embedded array type ASIC. The semiconductor integrated circuit according to claim 7, wherein the switch circuit is configured using at least one basic cell.

Images